數(shù)字設(shè)計(jì)原理與實(shí)踐：第三章 DIGITAL CIRCUITS-part 2

1Chapter3

DIGITALCIRCUITS

3.4ElectronicBehaviorofCMOSCircuits(CMOS電路的電氣特性)LogicVoltageLevels(邏輯電壓電平)DCNoiseMargins

(直流噪聲容限)Fun-Out(扇出)物理上的而不是邏輯上的

23.4ElectronicBehaviorofCMOSCircuits(CMOS電路的電氣特性)Speed,PowerConsumption

(速度、功耗)Noise,ElectrostaticDischarge

(噪聲、靜電放電)Open-DrainOutputs,ThreeStateOutputs(漏極開(kāi)路輸出、三態(tài)輸出)DataSheet（數(shù)據(jù)表）Specifications(規(guī)格說(shuō)明)（Table3-3）

33.5CMOSStatic/Steady-StateElectricalBehavior(CMOS靜態(tài)/穩(wěn)態(tài)電氣特性)LogicLevelsandNoiseMargins

(邏輯電平和噪聲容限)VDD=+5.0VVOUTVINTpTnVOUTVIN5.01.53.55.0CMOS反向器電壓傳輸特性

4LogicLevelsSpecifications(邏輯電平規(guī)格)HIGH(高態(tài))ABNOMAL(不正常狀態(tài))LOW(低態(tài))VOLmaxVILmaxVIHminVOHminVCC－0.1V地＋0.1V0.7VCC0.3VCC3.5CMOSSteady-StateElectricalBehavior

VCC0

53.5CMOSSteady-StateElectricalBehavior

DCNoiseMargin（直流噪聲容限）HIGH(高態(tài))ABNOMAL(不正常狀態(tài))LOW(低態(tài))VOLmaxVILmaxVIHminVOHmin30%VCC－0.1VHowmuchnoiseittakestocorruptaworse-caseoutputvoltageintoavaluethatmaynotberecognizedproperlybyaninput.(多大的噪聲會(huì)使最壞輸出電壓被破壞得不可識(shí)別)

63.5.2CircuitBehaviorwithResistiveLoads(帶電阻性負(fù)載的電路特性)Requirenontrivialamountsofcurrenttooperate(要求有一定的驅(qū)動(dòng)電流才能工作)VCCAZVCCRThevRpRnVThev

+VOUTVIN

7VCC=+5.0VRp>1MRnResistiveLoads(電阻性負(fù)載)VOLmaxIOLmaxWhentheOutputintheLOWstate(輸出為低態(tài)時(shí))VOUT<=VOLmaxTheOutputsinkCurrent(輸出端吸收電流)TheMaximumCurrenttheOutputcansink[能吸收的最大電流IOLmax（灌電流）]3.5.2CircuitBehaviorwithResistiveLoads

8VCC=+5.0VRpRn>1MResistiveLoads(電阻性負(fù)載)VOHminIOHmaxWhentheOutputintheHIGHstate(輸出為高態(tài)時(shí))VOUT>=VOHminTheOutputSourceCurrent(輸出端提供電流)TheMaximumCurrenttheOutputcanSource[能提供的最大電流IOHmax（拉電流）]3.5.2CircuitBehaviorwithResistiveLoads

9VCC=+5.0VRThevVThev

+WhentheOutputintheHIGHstate,EstimatetheSourcecurrent(輸出為高態(tài)時(shí)，估計(jì)提供電流)：3.5.2CircuitBehaviorwithResistiveLoads

10VCC=+5.0VRThevVThev

+WhentheOutputintheLOWstate,EstimatetheSinkcurrent(輸出為低態(tài)時(shí)，估計(jì)吸收電流)：3.5.2CircuitBehaviorwithResistiveLoads

11VCC=+5.0V4002.5kVIN1.5VVOUT4.31VVCC=+5.0V4k200VIN3.5VVOUT0.24VOutputvoltageawayfromthepower-supplyrail(Furtherwitharesistiveload[輸出電壓變壞（有電阻性負(fù)載時(shí)更差）]What’sworse:Outputcurrent,PowerConsumption(更糟糕的是：輸出端電流，功耗)3.5.3CircuitBehaviorwithNon-idealInputs(非理想輸入時(shí)的電路特性)

123.5.4Fan-out（扇出）TheNumberofInputsthattheGatecandrivewithoutexceedingitsworst-caseloadingspecifications.(在不超出其最壞情況負(fù)載規(guī)格的條件下，一個(gè)邏輯門(mén)能驅(qū)動(dòng)的輸入端個(gè)數(shù)。)Fan-outmustbeexaminedforbothpossibleoutputstates,HIGNandLOW

(扇出需考慮輸出高電平和低電平兩種狀態(tài))OverallFan-out=Min(HIGH-stateandLOW-state)[總扇出＝min（高態(tài)扇出，低態(tài)扇出）]DCFan-outandACFan-out

(直流扇出和交流扇出)

1374HCTDrives74LSLOWFan-Out

(低態(tài)扇出):Fan-out(扇出)

HIGHFan-Out(高態(tài)扇出)：高態(tài)剩余驅(qū)動(dòng)能力：CMOS:74HCTIOH=–4mAIOL=4mAIIH=1AIIL=–1ATTL:74LSIOH=–400AIOL=8mAIIH=20AIIL=–0.4mA總扇出

143.5.5EffectsofLoading(負(fù)載效應(yīng))LoadinganOutputBeyonditsratedFan-out：

[當(dāng)輸出負(fù)載大于它的扇出能力時(shí)]1、OutputVoltagebecomeWorse

[輸出電壓變差（不符合邏輯電平的規(guī)格）]2、PropagationDelay,RiseandFalltimemayIncrease

(傳輸延遲和轉(zhuǎn)換時(shí)間變長(zhǎng))3、TemperatureofthedevicemayIncrease,ReducingReliability,CausingdeviceFailure

(溫度可能升高，可靠性降低，器件失效)

153.5.6UnusedInputs

(不用的CMOS輸入端)NeverbeleftUnconnected(orFloating)

(不用的CMOS輸入端絕不能懸空)XZ1k+5VXZXZIncreasethecapacitiveloadonthedrivingsignalandmayslowthingsdown.(增加了驅(qū)動(dòng)信號(hào)的電容負(fù)載，使操作變慢)

163.5.7HowtoDestroyaCOMSDevice?如何毀壞COMS器件？

P112

173.6CMOSDynamicElectricalBehavior(CMOS動(dòng)態(tài)電氣特性)

BoththeSpeedandPowerConsumptionofaCMOSdevicedependtoalargeextentonACorDynamicCharacteristicsofthedeviceanditsload(CMOS器件的速度和功耗在很大程度上取決于器件及其負(fù)載的動(dòng)態(tài)特性。)

183.6CMOSDynamicElectricalBehavior(CMOS動(dòng)態(tài)電氣特性)Speeddependsontwocharacteristics(速度取決于兩個(gè)特性)：TransitionTime（轉(zhuǎn)換時(shí)間）PropagationDelay（傳播延遲）TheamountofTimethattheOutputofalogiccircuittakestoChangefromonestatetoanother.(邏輯電路的輸出從一種狀態(tài)變?yōu)榱硪环N狀態(tài)所需的時(shí)間)TheamountofTimethatittakesforaChangeintheInputsignaltoproduceaChangeintheOutputsignal.(從輸入信號(hào)變化到產(chǎn)生輸出信號(hào)變化所需的時(shí)間)Figure3-36Figure3-42

193.6.1TransitionTime(轉(zhuǎn)換時(shí)間)

Risetime(tr)andFalltime(tf)

(上升時(shí)間tr

和下降時(shí)間tf)The“On”transistorResistance

(晶體管的“導(dǎo)通”電阻)StrayCapacitance（寄生電容）VCC=+5.0VRLRpRnVL+CL電容兩端電壓不能突變“Time-ConstantequalsTransition-Time”(在實(shí)際電路中,可用時(shí)間常數(shù)近似轉(zhuǎn)換時(shí)間)

203.6.2PropagationDelay(傳播延遲)VINVOUTSignalPath:theelectricalpathfromaparticularinputsignaltoaparticularoutputsignalofalogicelement.(信號(hào)通路：一個(gè)特定輸入信號(hào)到邏輯元件的特定輸出信號(hào)所經(jīng)歷的電氣通路。)

Figure3-42

213.6.3PowerConsumption(功率損耗)StaticPowerDissipation(靜態(tài)功耗)DynamicPowerDissipation(動(dòng)態(tài)功耗)兩個(gè)管子瞬間同時(shí)導(dǎo)通產(chǎn)生的功耗PT對(duì)負(fù)載電容充、放電所產(chǎn)生的功耗PLPL與負(fù)載電容、輸入信號(hào)頻率、(VCC)2

成正比PT

與VCC的大小、輸入波形的好壞、輸入信號(hào)頻率有關(guān)

223.6.4CurrentSpikesandDecouplingCapacitors

(電流尖峰和去耦電容器)電流傳輸特性iDvI12VDDVDD=+5.0VVOUTVINTpTn見(jiàn)書(shū)P124

233.7OtherCMOSInputandOutputStructures

（其他CMOS輸入輸出結(jié)構(gòu)）TransmissionGates(傳輸門(mén))WhenEN=0，EN_L=1，TransistorOff,A,BOff(晶體管截止，A、B斷開(kāi))WhenEN=1，EN_L=0，TransistorOn,A,BOn(晶體管導(dǎo)通，A、B之間低阻抗連接)雙向器件傳播延遲非常短ENEN_LAB

24Schmitt-TriggerInputs

(施密特觸發(fā)器輸入)VOUTVIN5.02.12.95.0Input-OutputTransferCharacteristic(電壓傳輸特性)VT+VT-輸入門(mén)限電壓VT+VT-UseFeedbackInternally(采用內(nèi)部反饋，邊沿更陡)LogicSymbol(邏輯符號(hào))Hysteresis:DifferenceBetweentheTwoThresholds(滯后：兩個(gè)門(mén)限電壓之差)

25ApplicationsofSchmitt-Trigger

(施密特觸發(fā)器的應(yīng)用)波形變換

26脈沖整形ApplicationsofSchmitt-Trigger

(施密特觸發(fā)器的應(yīng)用)

27脈沖鑒幅ApplicationsofSchmitt-Trigger

(施密特觸發(fā)器的應(yīng)用)

28Three-StateOutputs(三態(tài)輸出)VCCOUTENAWhenEN=0，C=1,TpOff(截止)

B=1,D=0,TnOff

Hi-Z,High-Impedance/FloatingState(高阻態(tài)/懸空態(tài)）BCDTpTn

29Three-StateOutputs(三態(tài)輸出)VCCOUTENAWhenEN=1，C=A’,B=0,D=A’OutputControlledbyAisLogicLevels:HighorLow(由A控制輸出為:

邏輯0或邏輯1)BCDTpTnAENOUT邏輯符號(hào)

30輸出電平？？造成邏輯混亂很大的負(fù)載電流同時(shí)流過(guò)輸出級(jí)可使門(mén)電路損壞Open-DrainOutputs(漏極開(kāi)路輸出)VCCAZActivePull-Up(有源上拉)VCCB低高有源上拉的CMOS器件其輸出端不能直接相聯(lián)100>1M100>1M

31ABZVCCVCC’R上拉電阻ABZ邏輯符號(hào)希望盡量小，減少上升時(shí)間太小則吸收電流太大應(yīng)用：驅(qū)動(dòng)LED、線與、驅(qū)動(dòng)多源總線Open-DrainOutputs(漏極開(kāi)路輸出)LogicSymbol

32ABZVCCVCCRCDVCCZ=Z1·Z2=(A·B)’·(C·D)’=(A·B+C·D)’WiredLogicofOpen-DrainOutputs

(漏極開(kāi)路輸出的線連邏輯)Z1Z2WiredAND(線與)第4章反演定理

333.9BipolarLogic(雙極邏輯)DiodeTransfer

Characteristic(二極管開(kāi)關(guān)特性)Thresholds(門(mén)限電壓)Breakdown(反向擊穿)LeakageCurrent(漏電流)viVTI

s＋

343.9BipolarLogic(雙極邏輯)DiodeTransfer

Characteristic(二極管開(kāi)關(guān)特性)viVTI

sForwardBiased(正偏（導(dǎo)通）)+ReverseBiased(反偏（截止）)+RfVd250.6V

35DiodeLogic

(二極管邏輯)ABD1D2RVCCY0～2VLow(低電平)0(邏輯0)2～3VNoiseMargin(噪聲電平）

Undefined(未定義)3～5VHigh(高電平)1(邏輯1)DiodeANDGate(二極管與門(mén))3.9BipolarLogic(雙極邏輯)

36DiodeLogic

(二極管邏輯)ABD1D2RVCCY

電平偏移：輸出和輸入的數(shù)值不相等不能直接驅(qū)動(dòng)負(fù)載通常用于集成電路內(nèi)部的邏輯單元DiodeANDGate(二極管與門(mén))3.9BipolarLogic(雙極邏輯)

37BipolarJunctionTransistors

(雙極結(jié)型晶體管)截止區(qū)放大區(qū)飽和區(qū)Base(基極)Collector(集電極)Emitter發(fā)射極VCCvo+-vi+-RBRCiCTransistorLogicInverter(三極管反相器)

38SchottkyTransistors

(肖特基晶體管)三極管內(nèi)部電荷的建立和消散都需要時(shí)間

——存儲(chǔ)時(shí)間（傳輸延遲的重要部分）確保晶體管正常工作時(shí)不進(jìn)入深度飽和利用肖特基二極管Vd=0.25V基極集電極發(fā)射極

393.10Transistor-TransistorLogic

(晶體管－晶體管邏輯)TTLNANDGateOperatingPrinciple(TTL與非門(mén)工作原理)TTLLogicElectricalBehavior(TTL邏輯的電氣特性)LogicLevelsandNoiseMargins

(邏輯電平和噪聲容限)Fan-out,Drivingability,BehaviorofResistiveloads

(扇出、驅(qū)動(dòng)能力、電阻性負(fù)載特性)UnusedInputs

(不用的輸入端)——TTL系列

LOW(低態(tài))：0.0～0.8V

HIGH(高態(tài))：2.0~5.0V

40AdditionalTTLGateTypes

(其它TTL電路)Tri-Stateoutput,Open-CollectorGate

(三態(tài)輸出、集電極開(kāi)路OC門(mén))NORGate,Non-inverter

(或非門(mén)、非反相門(mén))3.10Transistor-TransistorLogic

(晶體管－晶體管邏輯)

41ABZVCC=+5VQ2Q3Q4Q5Q6D1AD1BPush-PullOutput(推拉式輸出)

42Push-PullOutput推拉式輸出二極管與門(mén)輸入保護(hù)低導(dǎo)通截止截止高低ABZVCC=+5VQ2Q3Q4Q5Q6D1AD1B

43分相器二極管與門(mén)輸入保護(hù)高導(dǎo)通導(dǎo)通1.0V0.7VABZVCC=+5VQ2Q3Q4Q5Q6D1AD1BPush-PullOutput(推拉式輸出)２輸入ＴＴＬ與非門(mén)

44LogicFamilies(邏輯系列)3.8CMOSFamiliesHC、HCTHighspeed(高速)AHC、AHCTFCT、FCT-T3.11TTLFamiliesHHighSpeed(高速)SSchottkey(肖特基)LLowPower[低功耗（LS）]AAdvanced(高級(jí))（AS、ALS）FFastSpeed(快速)7454FAMnnDeviceMarks(器件標(biāo)號(hào))對(duì)稱(chēng)輸出驅(qū)動(dòng)

453.12CMOS/TTLInterfacing(接口)NeedConsider:NoiseMargin,Fan-out,CapacitanceLoads（需要考慮：噪聲容限、扇出、電容負(fù)載）Abnormal(不正常狀態(tài))VOLmax0.5VOHmin2.7VIHmin2.0VILmax0.8TTLAbnormal(不正常狀態(tài))VOLmax0.33VILmax0.8VIHmin2.0VOHmin3.84CMOS

4674HCTDrives74LS

HIGH:3.84–2.0=1.84V

LOW:|0.33–0.8|=0.47VABNORMAL(不正常狀態(tài))VOLmax0.33VILmax0.8VIHmin2.0VOHmin3.8474HCTABNORMAL(不正常狀態(tài))VOLmax0.5VOHmin2.7VIHmin2.0VILmax0.874LS74LSDrives74HCT

HIGH:2.7–2.0=0.7V

LOW:|0.5–0.8|=0.3V1、DCNoiseMargin(直流噪聲容限)

4774HCTDrives74LSLOWFan-Out

(低態(tài)扇出):2、Fan-OUT(扇出)

HIGHFan-Out(高態(tài)扇出)：高態(tài)剩余驅(qū)動(dòng)能力：CMOS:74HCTIOH=–4mAIOL=4mAIIH=1AIIL=–1ATTL:74LSIOH=–400AIOL=8mAIIH=20AIIL=–0.4mA總扇出

482、Fan-Out(扇出)CMOS:74HCTIOH=–4mAIOL=4mAIIH=1AIIL=–1ATTL:74LSIOH=–400AIOL=8mAIIH=20AIIL=–0.4mA思考：74LS(TTL)驅(qū)動(dòng)74HCT(CMOS)的情況？為什么說(shuō)用TTL驅(qū)動(dòng)TTL兼容的CMOS輸入端幾乎不用考慮直流扇出的限制？P96表3-6P97表3-7P115表3-11

493.13Low-VoltageCMOSLogicandInterfacing(低電壓CMOS邏輯和接口)

50LVTTL輸出可直接驅(qū)動(dòng)TTL輸入端如果輸入是5V容許的，TTL輸出可驅(qū)動(dòng)LVTTL輸入端如果LVTTL輸出是5V容許的，TTL和LVTTL三態(tài)輸出可驅(qū)動(dòng)同一總線

513.14Emitter-CoupledLogic

(發(fā)射極耦合邏輯ECL)Howtoimprovespeed(如何提高速度)？

——

PreventingTransistorSaturation(防止晶體管飽和)Current-ModeLogic(CML,電流型邏輯)OrEmitter-CoupledLogic（ECL,也稱(chēng)為：發(fā)射極耦合）

52LOWInput：3.6VVCC=5.0VR1300R2330INOUT1O