同濟控制系復試-微機原理課件余有靈

Chapter12

InterruptsInstructor：Dr.YuYoulingContentBasicInterruptProcessingHardwareInterruptsExpandingtheInterruptStructure8259AProgrammableInterruptControllerExamples2023/1/17第2頁InterruptsInterruptprocessingisanalternativetopolling.TheIntelmicroprocessorssupporthardwareinterruptsthrough:Twopinsthatallowinterruptrequests,INTRandNMIOnepinthatacknowledges,INTA,theinterruptrequestedonINTR.Andsoftwareinterruptsthroughinstructions:INT,INTO,INT3,BOUNDControlisprovidedthroughIFandTFflagbitsIRETandIRETD2023/1/17第3頁InterruptVectorTableINTandINT3behaveinasimilarway.INTn:CallsISRlocatedatvectorn(n*4).TheINTinstructionrequirestwobytesofmemory,opcodeplusn.BOUNDandINTOarebothconditional.BOUND: BOUNDAX,DATAparesAXwithDATAAXiscomparedwithDATAandDATA+1,iflessthananinterruptoccurs.AXiscomparedwithDATA+2andDATA+3,ifgreaterthananinterruptoccurs.INTO:Checkstheoverflowflag(OF).IfOF=1,theISRiscalled.IRETremoves6bytesfromthestack,2forIP,2forCSand2forFLAGS.2023/1/17第4頁InterruptVectorTableTheinterruptvectortableislocatedinthefirst1024bytesofmemoryataddresses00000Hthrough003FFH.Thereare2564-byteentries(segmentandoffsetinrealmode).2023/1/17第5頁RealModeInterruptsAftertheexecutionofeachinstruction,themicroprocessordetermineswhetheraninterruptisactivebychecking,inorder:Single-stepNMICoprocessorsegmentoverrunINTRINTIfoneormoreoftheseconditionsarepresent,then:FLAGSispushedontothestackBoththeinterrupt(IF)andtrap(TF)flagsarecleared,whichdisablestheINTRpinandthetraporsingle-stepfeature.TheCSandIParepushedontothestack.TheinterruptvectorcontentsarefetchedandloadedintoCSandIPandexecutionresumesintheISR.OnIRET,CS,IPandFLAGSarepopped.2023/1/17第6頁RealandProtectedModeInterruptsThereturnaddress(CS/IP)ispushedontothestackduringtheinterrupt.Thereturnaddresscanpointto:Thenextinstruction.Theoffending(current)instruction.Thismakesitpossibletotrytheinstructionagain.2023/1/17第7頁HardwareInterruptsTheINTRpinmustbeexternallydecodedtoselectavector.Anyvectorispossible,buttheinterruptvectorsbetween20HandFFHareusuallyused(Intelreservesvectorsbetween00Hand1FH).INTAisanoutputofthemicroprocessortosignaltheexternaldecodertoplacetheinterruptnumberondatabusconnectionsD7-D0.TheINTRpinissetbyanexternaldevice(8259A)andclearedintheISR.Theinputisautomaticallydisabledbythemicroprocessoronceitisrecognizedandre-enabledbyIRETorIRETDinstruction.Timingdiagramofthehandshake.2023/1/17第8頁HardwareInterruptsSimpliestmethodofgeneratinganinterruptvector:2023/1/17第9頁Tri-stateBufferforGeneratingtheInterruptVector2023/1/17第10頁Handlingmorethan1IRQIfanyofIRQxgoeslow,theNANDoutputgoeshighrequestinganinterrupt.NotethatifmorethanoneIRQgoeslow,auniqueinterruptvectorisgeneratedandaninterruptpriorityneedstobedefined.TheInterruptVectortablemustbeexpandedtomodatethis.2023/1/17第11頁Example2023/1/17第12頁2023/1/17第13頁Instruction2023/1/17第14頁ExternalHardwareInterruptsExternalhardwareinterruptinterfacecircuitry-ResponsiblefordeterminingwhichofanypendinginterruptshashighestpriorityINTR:InterruptrequestLevel-triggered–“1”mustbemaintaineduntilINTA.Mustgobackto“0”beforeserviceroutineisdone.INTA:InterruptacknowledgeTwopulses...theCPUissaying:PULSE1:“Gotit–nowsendthetypenumber”PULSE2:“PlacetheTypenumberondatabus”2023/1/17第15頁Read/WriteInterruptVectorTable設置中斷向量把由AL指定的中斷類型的中斷向量DS:DX放置在中斷向量表的相應位置中。 AH=25H執(zhí)行：INT21H AL=中斷類型號 DS:DX=中斷向量取中斷向量把由AL指定的中斷類型的中斷向量從中斷向量表中取到ES:BX中

預置：AH=35H執(zhí)行：INT21H AL=中斷類型號

返回：ES:BX=中斷向量2023/1/17第16頁ExampleMOVAL,N;typeNInterruptMOVAH,35H;getInterruptvectorINT21H;PUSHES; savetheoldbaseandPUSHBX;offsetofinterruptNPUSHDS;MOVAX,SEGINTHAND;MOVDS,AX;baseofINTHANDinDSMOVDX,OffsetINTHAND;offsetinDXMOVAL,N;MOVAH,25H;SetInterruptVectorINT21H;2023/1/17第17頁POPDS;…POPDX; restoretheoldoffsetPOPDS; andbaseofinterruptMOVAL,N;MOVAH,25H;setinterruptvectorINT21H;RET;returnINTHAND:….InterruptProcessingRoutineIRET例：使用DOS功能調用存取中斷向量TypicalArchitecture2023/1/17第18頁The8259Aadds8vectoredpriorityencodedinterruptstothemicroprocessor.Itcanbeexpandedto64interruptrequestsbyusingonemaster8259Aand8slaveunits.8259AProgrammableInterruptController2023/1/17第19頁8259AProgrammableInterruptControllerINTConnectstotheINTRpinonthemicroprocessor.INTAConnectstotheINTApinonthemicroprocessor.A0Selectsdifferentcommandwordsinthe8259A.SP/ENSlaveProgram(1formaster,0forslave)/EnableBuffer(controlsthedatabustransceiverswheninbufferedmode).CAS2-CAS0Usedasoutputsfromthemastertotheslavesincascadedsystems.2023/1/17第20頁8259AProgrammableInterruptControllerAsingle8259Aconnectedinthe8086.2023/1/17第21頁Programmingthe8259AProgrammedbyInitialization(ICWs)andOperation(OCWs)CommandWords.Thereare4ICWs.Atpower-up,ICW1,ICW2andICW4mustbesent.IfICW1indicatescascademode,thenICW3mustalsobesent.ICW1:LTIMindicatesifIRQlinesarepositiveedge-triggeredorlevel-triggered.2023/1/17第22頁ICW2:ThesebitsdeterminethevectornumbersusedwiththeIRQinputs.Forexample,ifprogrammedtogeneratevectors08H-0FH,08Hisplacedintothesebitpositions.ICW3:Programmingthe8259A2023/1/17第23頁Programmingthe8259AICW4:Fullynestedmodeallowsthehighest-priorityinterruptrequestfromaslavetoberecognizedbythemasterwhileitisprocessinganotherinterruptfromaslave.AEOI,if1,indicatesthataninterruptautomaticallyresetstheinterruptrequestbit,otherwiseOCW2isconsultedforEOIprocessing.2023/1/17第24頁InitializationFlow2023/1/17第25頁Programmingthe8259ATheOperationCommandWords(OCWs)areusedtodirecttheoperationofthe8259A.OCW1:OCW1isusedtoreadorsettheinterruptmaskregister.Ifabitisset,itwillturnoff(mask)thecorrespondinginterruptinput.OCW2:OnlyprogrammedwhentheAEOImodeinICW4is0.Allowsyoutocontrolprioritiesaftereachinterruptisprocessed.2023/1/17第26頁Programmingthe8259AOCW2Non-specificEOI:Here,theISRsetsthisbittoindicateEOI.The8259Aautomaticallydetermineswhichinterruptwasactiveandre-enablesitandlowerpriorityinterrupts.SpecificEOI:ISRresetsaspecificinterruptrequestgivenbyL2-L0.Rotatecommandscauseprioritytoberotatedw.r.t.thecurrentonebeingprocessed.Setpriority:allowsthesettingofthelowestpriorityinterrupt(L2-L0).2023/1/17第27頁Programmingthe8259AOCW3Ifpollingisset,thenextreadoperationwillreadthepollword.Iftheleftmostbitissetinthepollword,therightmost3bitsindicatetheactiveinterruptrequestwithhighestpriority.AllowsISRtoservicehighestpriorityinterrupt.Therearethreestatusregisters,InterruptRequestRegister(IRR),In-ServiceRegister(ISR)andInterruptMaskRegister(IMR).IRR:Indicateswhichinterruptrequestlinesareactive.ISR:Leveloftheinterruptbeingserviced.IMR:Amaskthatindicateswhichinterruptsareon/off.2023/1/1