8051系列微控制器-畢業(yè)論文外文文獻翻譯畢業(yè)論文

PAGEPAGE17英文資料及中文翻譯OverviewThe8051familyofmicrocontrollersisbasedonanarchitecturewhichishighlyoptimizedforembeddedcontrolsystems.ItisusedinawidevarietyofapplicationsfrommilitaryequipmenttoautomobilestothekeyboardonyourPC.SecondonlytotheMotorola68HC11ineightbitprocessorssales,the8051familyofmicrocontrollersisavailableinawidearrayofvariationsfrommanufacturerssuchasIntel,Philips,andSiemens.Thesemanufacturershaveaddednumerousfeaturesandperipheralstothe8051suchasI2Cinterfaces,analogtodigitalconverters,watchdogtimers,andpulsewidthmodulatedoutputs.Variationsofthe8051withclockspeedsupto40MHzandvoltagerequirementsdownto1.5voltsareavailable.Thiswiderangeofpartsbasedononecoremakesthe8051familyanexcellentchoiceasthebasearchitectureforacompany'sentirelineofproductssinceitcanperformmanyfunctionsanddeveloperswillonlyhavetolearnthisoneplatform.Thebasicarchitectureconsistsofthefollowingfeatures:1aneightbitALU232descreteI/Opins(4groupsof8)whichcanbeindividuallyaccessed3two16bittimer/counters4fullduplexUART56interruptsourceswith2prioritylevels6128bytesofonboardRAM7separate64KbyteaddressspacesforDATAandCODEmemoryOne8051processorcycleconsistsoftwelveoscillatorperiods.Eachofthetwelveoscillatorperiodsisusedforaspecialfunctionbythe8051coresuchasopcodefetchesandsamplesoftheinterruptdaisychainforpendinginterrupts.Thetimerequiredforany8051instructioncanbecomputedbydividingtheclockfrequencyby12,invertingthatresultandmultiplyingitbythenumberofprocessorcyclesrequiredbytheinstructioninquestion.Therefore,ifyouhaveasystemwhichisusingan11.059MHzclock,youcancomputethenumberofinstructionspersecondbydividingthisvalueby12.Thisgivesaninstructionfrequencyof921583instructionspersecond.Invertingthiswillprovidetheamountoftimetakenbyeachinstructioncycle(1.085microseconds).MemoryOrganizationThe8051architectureprovidestheuserwiththreephysicallydistinctmemoryspaceswhichcanbeseeninFigureA-1.Eachmemoryspaceconsistsofcontiguousaddressesfrom0tothemaximumsize,inbytes,ofthememoryspace.Addressoverlapsareresolvedbyutilizinginstructionswhichreferspecificallytoagivenaddressspace.Thethreememoryspacesfunctionasdescribedbelow.TheCODESpaceThefirstmemoryspaceistheCODEsegmentinwhichtheexecutableprogramresides.Thissegmentcanbeupto64K(sinceitisaddressedby16addresslines).TheprocessortreatsthissegmentasreadonlyandwillgeneratesignalsappropriatetoaccessamemorydevicesuchasanEPROM.However,thisdoesnotmeanthattheCODEsegmentmustbeimplementedusinganEPROM.ManyembeddedsystemsthesedaysareusingEEPROMwhichallowsthememorytobeoverwritteneitherbythe8051itselforbyanexternaldevice.ThismakesupgradestotheproducteasytodosincenewsoftwarecanbedownloadedintotheEEPROMratherthanhavingtodisassembleitandinstallanewEPROM.Additionally,batterybackedSRAMcanbeusedinplaceofanEPROM.ThismethodoffersthesamecapabilitytouploadnewsoftwaretotheunitasdoesanEEPROM,anddoesnothaveanysortofread/writecyclelimitationssuchasanEEPROMhas.However,whenthebatterysupplyingtheRAMeventuallydies,sodoesthesoftwareinit.UsinganSRAMinplaceofanEPROMindevelopmentsystemsallowsforrapiddownloadingofnewcodeintothetargetsystem.Whenthiscanbedone,ithelpsavoidthecycleofprogramming/testing/erasingwithEPROM,andcanalsohelpavoidhasslesoveranincircuitemulatorwhichisusuallyararecommodity.Inadditiontoexecutablecode,itiscommonpracticewiththe8051tostorefixedlookuptablesintheCODEsegment.Tofacilitatethis,the8051providesinstructionswhichallowrapidaccesstotablesviathedatapointer(DPTR)ortheprogramcounterwithanoffsetintothetableoptionallyprovidedbytheaccumulator.Thismeansthatoftentimes,atable'sbaseaddresscanbeloadedinDPTRandtheelementofthetabletoaccesscanbeheldintheaccumulator.Theadditionisperformedbythe8051duringtheexecutionoftheinstructionwhichcansavemanycyclesdependingonthesituation.Anexampleofthisisshownlaterinthischapterin.TheDATASpaceThesecondmemoryspaceisthe128bytesofinternalRAMonthe8051,orthefirst128bytesofinternalRAMonthe8052.ThissegmentistypicallyreferredtoastheDATAsegment.TheRAMlocationsinthissegmentareaccessedinoneortwocyclesdependingontheinstruction.ThisaccesstimeismuchquickerthanaccesstotheXDATAsegmentbecausememoryisaddresseddirectlyratherthanviaamemorypointersuchasDPTRwhichmustfirstbeinitialized.Therefore,frequentlyusedvariablesandtemporaryscratchvariablesareusuallyassignedtotheDATAsegment.Suchallocationmustbedonewithcare,however,duetothelimitedamountofmemoryinthissegment.VariablesstoredintheDATAsegmentcanalsobeaccessedindirectlyviaR0orR1.Theregisterbeingusedasthememorypointermustcontaintheaddressofthebytetoberetrievedoraltered.Theseinstructionscantakeoneortwoprocessorcyclesdependingonthesource/destinationdatabyte.TheDATAsegmentcontainstwosmallersegmentsofinterest.Thefirstsubsegmentconsistsofthefoursetsofregisterbankswhichcomposethefirst32bytesofRAM.The8051canuseanyofthesefourgroupsofeightbytesasitsdefaultregisterbank.TheselectionofregisterbanksischangeableatanytimeviatheRS1andtheRS0bitsintheProcessorStatusWord(PSW).Thesetwobitscombineintoanumberfrom0to3(withRS1beingthemostsignificantbit)whichindicatestheregisterbanktobeused.Registerbankswitchingallowsnotonlyforquickparameterpassing,butalsoopensthedoorforsimplifyingtaskswitchingonthe8051.Thesecondsub-segmentintheDATAspaceisabitaddressablesegmentinwhicheachbitcanbeindividuallyaccessed.ThissegmentisreferredtoastheBDATAsegment.Thebitaddressablesegmentconsistsof16bytes(128bits)abovethefourregisterbanksinmemory.The8051containsseveralsinglebitinstructionswhichareoftenveryusefulincontrolapplicationsandaidinreplacingexternalcombinatoriallogicwithsoftwareinthe8051thusreducingpartscountonthetargetsystem.Itshouldbenotedthatthese16bytescanalsobeaccessedona"byte-wide"basisjustlikeanyotherbyteintheDATAspace.SpecialFunctionRegistersControlregistersfortheinterruptsystemandtheperipheralsonthe8051arecontainedininternalRAMatlocations80hexandabove.Theseregistersarereferredtoasspecialfunction.Registers(orSFRforshort).Manyofthemarebitaddressable.ThebitsinthebitaddressableSFRcaneitherbeaccessedbyname,indexorbitaddress.Thus,youcanrefertotheEAbitoftheInterruptEnableSFRasEA,IE.7,or0AFH.TheSFRcontrolthingssuchasthefunctionofthetimer/counters,theUART,andtheinterruptsourcesaswellastheirpriorities.TheseregistersareaccessedbythesamesetofinstructionsasthebytesandbitsintheDATAsegment.AmemorymapoftheSFRSindicatingtheregisters.TheIDATASpaceCertain8051familymemberssuchasthe8052containanadditional128bytesofinternalRAMwhichresideatRAMlocations80hexandabove.ThissegmentofRAMistypicallyreferredtoastheIDATAsegment.BecausetheIDATAaddressesandtheSFRaddressesoverlap,addressconflictsbetweenIDATARAMandtheSFRsareresolvedbythetypeofmemoryaccessbeingperformed,sincetheIDATAsegmentcanonlybeaccessedviaindirectaddressingmodes.TheXDATASpace.Thefinal8051memoryspaceis64Kinlengthandisaddressedbythesame16addresslinesastheCODEsegment.Thisspaceistypicallyreferredtoastheexternaldatamemoryspace(ortheXDATAsegmentforshort).ThissegmentusuallyconsistsofsomesortofRAM(usuallyanSRAM)andtheI/Odevicesorexternalperipheralstowhichthe8051mustinterfaceviaitsbus.ReadorwriteoperationstothissegmenttakeaminimumoftwoprocessorcyclesandareperformedusingeitherDPTR,R0,orR1.InthecaseofDPTR,itusuallytakestwoprocessorcyclesormoretoloadthedesiredaddressinadditiontothetwocyclesrequiredtoperformthereadorwriteoperation.Similarly,loadingR0orR1willtakeminimumofonecycleinadditiontothetwocyclesimposedbythememoryaccessitself.Therefore,itiseasytoseethatatypicaloperationwiththeXDATAsegmentwill,ingeneral,takeaminimumofthreeprocessorcycles.Becauseofthis,theDATAsegmentisaveryattractiveplacetostoreanyfrequently.Itispossibletofillthissegmententirelywith64KofRAMifthe8051doesnotneedtoperformanyI/OwithdevicesinitsbusorifthedesignerwishestocycletheRAMonandoffwhenI/Odevicesarebeingaccessedviathebus.Methodsforperformingthistechniquewillbediscussedinchapterslaterinthisbook.On-BoardTimer/CountersThestandard8051hastwotimer/counters(other8051familymembershavevaryingamounts),eachofwhichisafull16bits.Eachtimer/countercanbefunctionasafreerunningtimer(inwhichcasetheycountprocessorcycles)orcanbeusedtocountfallingedgesonthesignalappliedtotheirrespectiveI/Opin(eitherT0orT1).Whenusedasacounter,theinputsignalmusthaveafrequencyequaltoorlowerthantheinstructioncyclefrequencydividedby2(ie:theoscillatorfrequency/24)sincetheincomingsignalissampledeveryinstructioncycle,andthecounterisincrementedonlywhena1to0transitionisdetected(whichwillrequiretwosamples).Ifdesired,thetimer/counterscanforceasoftwareinterruptwhentheyoverflow.TheTCON(TimerControl)SFRisusedtostartorstopthetimersaswellasholdtheoverflowflagsofthetimers.TheTCONSFRisdetailedbelowinTableA-7.Thetimer/countersarestartedorstoppedbychangingthetimerrunbits(TR0andTR1)inTCON.ThesoftwarecanfreezetheoperationofeithertimeraswellasrestartthetimerssimplybychangingtheTrxbitintheTCONregister.TheTCONregisteralsocontainstheoverflowflagsforthetimers.Whenthetimersoverflow,theysettheirrespectiveflag(TF0orTF1)inthisregister.Whentheprocessordetectsa0to1transitionintheflag,aninterruptoccursifitisenabled.Itshouldbenotedthatthesoftwarecansetorclearthisflagatanytime.Therefore,aninterruptcanbepreventedaswellasforcedbythesoftware.MicrocomputerinterfaceAmicrocomputerinterfaceconvertsinformationbetweentwoforms.Outsidethemicrocomputertheinformationhandledbyanelectronicsystemexistsasaphysicalsignals,butwithintheprogram,itisrepresentednumerically.Thefunctionofanyinterfacecanbebrokendownintoanumberofoperationswhichmodifythedatainsomeway,sothantheprocessofconversionbetweentheexternalandinternalformsiscarriedoutinanumberorsteps.ThiscanbeillustratedbymeansofanexamplesuchasthanorFig10-1,whichshowsaninterfacebetweenamicrocomputerandatransducerproducingacontinuouslyvariableanalogsignal.transducersoftenproduceverysmalloutrequiringamplyfrication,ortheymaygeneratesignals.inaformthatneedstobeconvertedagainbeforebeinghandledbytherestofthesystem.Forexample,manytransducersthesevariableresistancewhichmustbeconvertedtoavoltagebyaspecialcircuit.Thisprocessofconvertingthetransduceroutputintoavoltage4signalwhichcanbeconnectedtotherestofthesystemiscalledsignalconditioning.IntheexampleofFigure10-1,thesigmaconditioningsectiontranslatestherangelfvoltageorcurrentsignalsfromthetransducertoonewhichcanbeconvertedtodigitalforumbyananalog-to-digitalconverter.TransducerADCSignalconditioningTransducerADCSignalconditioningI/OSectionI/OSectionFig10-1outputInterfaceAnalog-to-digital–digitalconverter(ADC)isusedtoconvertacontinuouslyvariablesignaltoacorrespondingdigitalforumwhichcantakeanyoneofafixednumberofpossiblebinaryvalues.Iftheoutputlfthetransducerdoesnotvarycontinuously,noADCisnecessary.Inthiscasethesignalconditioningsectionmustconverttheincomingsignaltoaformwhichcanbeconnecteddirectlytothenextpartoftheinterface,theinput/outputsectionlfthemicrocomputeritself.TheI/Osectionconvertsdigital“on/off”voltagesignalstoaformwhichcanbepresentedtotheprocessorviatheviathesystembuses.Herethestateofeachinputlinewhetheritis“on”or“off”,isindicatedbyacorresponding“1”or“0”.Inthelineinputswhichhavebeenconvertedtodigitalform,thepatternsofonesandzerosintheinternalrepresentationwillformbinarynumberscorrespondingtothequantitybeingconverted.The“raw”numbersfromtheinterfacearelimitedbythedesignoftheinterfacecircuitryandtheyoftenrequirelinearizationandscalingtoproducevaluessuitableforuseinthemainprogram.Forexample,theinterfacenightberisetoconverttemperaturesintherange–20to–+50dress,buythenumbersproducedbyan8-bitconverterwilllieintherange0to255.Obviouslyitiseasier,theprogrammer‘spointofviewtodealdirectlywithtemperatureratherthantoworkouttheequivalentofanygiventemperatureintermsofthenumbersproducedbytheADC.Everytimetheinterfaceisusedtoreadatransducer,thesameoperationsmustbecarriedouttoconverttheinputnumberintoamoreconvenientform.Addtionarly,theoperationofsomeinterfacesrequirescontrolsignalstobepassedbetweenthemicrocomputerandcomponentsoftheinterface,Forthesereasonsitisnormaltouseasubroutinetolootafterthedetailedoperationoftheinterfaceandcarryoutanyscalingand/orlinearizationwhichmightbeneeded.Outputinterfacestakeasimilarform(Fig.10-2),thebiopicdifferencebeingthatheretheflowofinformationisintheoppositedirection;itispassedfromtheprogramtotheoutsideworld.Inthiscasetheprogrammaycallanoutputsubroutinewhichsupervisestheoperationoftheinterfaceandperformsthescalingnumberswhichmaybeneededforadigital-to-analogconverter(DAC).ThissubroutinepassesinformationintermtoanoutanalogformusingaDAC.Finallythesignalisconditioned(usuallyamplified)toaformsuitableforoperatinganactuator.Fig10-2outputInterfaceThesignalsusedwithinmicrocomputercircuitsarealmostalwaystoosmalltobeconnecteddirectlytothe“outsideworld”andsomekingofinterfacemustbeusedtotranslatethemtoamoreappropriateform.Thedesignofsectionofinterfacecircuitsisoneofthemostimportanttasksfacingtheengineerwishingtoapplymicrocomputers.Wehaveseenthatinmicrocomputersinformationisrepresentedasdiscretepatternsofbits;thisdigitalformismostusefulwhenthemicrocomputeristobeconnectedtoequipmentwhichcanonlybeswitchedonoroff,whereeachbitmightrepresentthestateofaswitchoractuator.Caremustbetakenwhenconnectinglogiccircuitstoensurethattheirlogiclevelsandcurrentratingsarecompatible.Theoutputvoltagesproducedbyalogiccircuitarenormallyspecifiedintermsofworstcasevalueswhensourcingorsinkingthemaximumratedcurrents.ThusVOHistheguaranteedminimum“high”voltagewhensourcingthemaximumrate“high”outputcurrentIOH,whileVOListheguaranteed“l(fā)ow”outputvoltagewhensinkingthemaximumrated“l(fā)ow”outputcurrentIOL.Therearecorrespondingspecificationsforlogicinputswhichspecifytheminimuminputvoltagewhichwillberecognizedasalogic“high”stateVIH,andthemaximuminputvoltagewhichwillberegardedasalogic“l(fā)ow”stateVIL.Forinputinterface,perhapsthemainproblemfacingthedesigneristhatofelectricalnoise.Smallnoisesignalmaycausethesystemtomalfunction,whilelargeramountsofmoistcanpermanentlydamageit.Thedesignermustbeawareofthesedangersfromtheoutset.Therearemanymethodstoprotectinterfacecircuitsandmicrocomputerfromvariouskindsofnoise.Followingissomeexamples:1.Inputandoutputelectricalisolatingbetweenthemicrocomputersystemandexternaldevicesusinganopt-isolatororatransformer.2.Removinghighfrequencynoisepulsesbyalow-peafilterandSchmitt-trigger.3.Protectingagainstexcessiveinputvoltagesusingapairofdiodestopowersupplyreversiblybiasedinnormaldirection.Foroutputinterface,parametersVOH,VOL,IOHandIOLofalogicdeviceareusuallymuchtolowtoallowloadstobeconnecteddirectly,andinpracticeanexternalcircuitmustbeconnectedtoamplifythecurrentandvoltagetodriveaload.AlthoughseveraltypesofsemiconductordevicesarenowavailableforcontrollingDCandACpowersuptomanykilowatts,therearetwobasicwaysinwhichaswitchcanbeconnectedtoaloadtocontrolit:seriesconnectionandshuntconnectionasshowninFigure10-3.Fig10-3SeriesandShuntConnectionWithseriesconnection,theswitchallowscurrenttoflowthroughtheloadwhenclosed,whilewithshuntconnectionclosingtheswitchallowscurrenttobypasstheload.Bothconnectionsareusefulinlow-powercircuits,butonlytheseriesconnectioncanbeusedinhigh-powercircuitsbecauseofthepowerwastedintheseriesresistorR.THEINTRODUCTIONOFAT89C52FeaturesoftheAT89C52?CompatiblewithMCS-51?Products?8KBytesofIn-SystemReprogrammableFlashMemory?Endurance:1,000Write/EraseCycles?FullyStaticOperation:0Hzto24MHz?Three-levelProgramMemoryLock?256x8-BitInternalRAM?32ProgrammableI/OLines?Three16-bitTimer/Counters?EightInterruptSources?ProgrammableSerialChannel?LowPowerIdleandPowerDownModesDescriptionTheAT89C52isalow-power,high-performanceCMOS8-bitmicrocomputerwith8KbytesofFlashprogrammableanderasablereadonlymemory(PEROM).ThedeviceismanufacturedusingAtmel’shighdensitynonvolatilememorytechnologyandiscompatiblewiththeindustrystandard80C51and80C52instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8-bitCPUwithFlashonamonolithicchip,theAtmelAT89C52isapowerfulmicrocomputerwhichprovidesahighlyflexibleandcosteffectivesolutiontomanyembeddedcontrolapplications.TheAT89C52providesthefollowingstandardfeatures:8KbytesofFlash,256bytesofRAM,32I/Olines,three16-bittimer/counters,asix-vectortwo-levelinterruptarchitectureafullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89C52isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAMtimer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePowerDownModesavestheRAMcontentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenexthardwarereset.PinDescriptionVCCSupplyvoltage.GNDGround.Port0Port0isan8-bitopendrainbidirectionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashighimpedanceinputs.Port0canalsobeconfiguredtobethemultiplexedloworderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpullups.Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.Port1Port1isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighby.Theinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Inaddition,P1.0andP1.1canbeconfiguredtobethetimer/counter2externalcountinput(P1.0/T2)andthetimer/counter2triggerinput(P1.1/T2EX),respectively,asshowninthefollowingtable.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.TABLE1--PortPinfunctionPortpinAlternateFunctionsP1.0T2(externalcountinputtoTimer/Counter2),clock-outP1.1T2EX(Timer/Counter2capture/reloadtriggeranddirectioncontrol)Port2Port2isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR).Inthisapplication,Port2usesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.Port3Port3isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepullups.概述 8051系列微控制器是基于高度完善的嵌入式控制系統(tǒng)的體系結(jié)構(gòu)。從軍事設(shè)備到汽車，再到PC機的鍵盤，它都有很廣泛的應(yīng)用。另外，對于摩托羅拉公司生產(chǎn)的M68HC11（8位處理器）可以應(yīng)用于不同廠商生產(chǎn)的8051系列微控制器，如：Intel、Philips及Siemens等。這些廠商都對8051增加了許多功能部件和外圍設(shè)備，如：12C總線接口、模/數(shù)轉(zhuǎn)換器、監(jiān)視跟蹤定時器和脈沖寬度調(diào)制輸出。8051的允許范圍：時鐘頻率上至40MHz，電壓下至1.5V都是有效的。一個公司的生產(chǎn)線要完成許多功能，開發(fā)人員就不得不學習這個平臺，為此以8051系列作為基本體系結(jié)構(gòu)是最好的選擇，以它為核心得到了廣泛的應(yīng)用?；倔w系結(jié)構(gòu)由下列功能部件組成：1.8位ALU；2.32個I/O引腳（4組，每組8個），可分別存取；3.2個16位定時/計數(shù)器；4.全雙工通用異步收發(fā)器；5.6個中斷源，2個中斷優(yōu)先級；6.128字節(jié)隨機存儲器；7.64字節(jié)地址空間，存放數(shù)據(jù)和代碼。一個8051的處理器周期是由12個振蕩周期組成。12個振蕩周期中每一個都能完成一種特殊功能，8051的核心如：操作碼的取出、典型的菊花鏈待定中斷。任何8051指令所需的定時都是由時鐘脈沖頻率除以12，再將所得結(jié)果乘以處理機所需的循環(huán)數(shù)計算得到。因此，如果你有一個系統(tǒng)時鐘11.059MHz，你可以用這個值除以12計算出每秒所需指令數(shù)。這里我們給出一個指令頻率921583/秒。將它轉(zhuǎn)化成實際時間，每個指令周期（1.085微妙）。存儲器組織8051體系結(jié)構(gòu)為用戶提供了3個物理直接存儲空間。每個存儲空間占用連續(xù)地址空間，按字節(jié)從0到最大尺寸。地址重疊是通過利用引用特定地址空間指令來解決的。這三個存儲空間功能如下所述：代碼空間第一個存儲空間是代碼段，其中用來存放可執(zhí)行程序。這個段最大可達64K（因為它有16根地址線）。處理機將它視為只讀，能產(chǎn)生相應(yīng)的信號對一存儲器件進行存取，如可擦可編程只讀存儲器EPROM。然而，這不意味著代碼段必須作為EPROM的工具。目前，許多嵌入式系統(tǒng)都利用EPROM，通過8051或一個外部設(shè)備允許對它存儲或改寫。這可能輕而易舉的提高產(chǎn)品，因為新的軟件可以下載到EPROM，而不必將它分解后再安裝成一個新的EPROM。另外，電池后面的靜態(tài)存儲器SRAM也可用來代替EPROM。這種方法和加載軟件到電可擦可編程只讀存儲器EEPROM是一樣的，但是EEPROM沒有任何讀/寫周期限制。然而，當電池電源RAM沒電了，也可如此將軟件加載到里面。在開發(fā)系統(tǒng)中若用SRAM代替EPROM，則允許在目標系統(tǒng)中快速下載新代碼。如果可以那樣做，它將幫助我們避免對EPROM的循環(huán)執(zhí)行/測試/擦寫，同時也能幫助我們避免對通常很少使用的線路仿真器產(chǎn)生爭論。除可執(zhí)行程序代碼之外，8051通常在代碼段存放安裝查找表。為了簡化，8051提供了允許快速存取查找表指令的途徑——數(shù)據(jù)指針（DPTR）或帶偏移量的程序計數(shù)器通過累加器隨意的指向查找表。通常這意味著，一個查找表的基地址能用DPTR來定位，而表中的元素可以通過累加器存儲。用8051執(zhí)行加法，在指令執(zhí)行期間可以根據(jù)情況存放許多循環(huán)數(shù)。數(shù)據(jù)空間8051輔助存儲空間是128字節(jié)的內(nèi)部RAM，而8052的高128字節(jié)是輔助存儲空間。這個段被認為是典型的數(shù)據(jù)段。RAM定位在這個段，依靠指令循環(huán)存取一次或二次。這樣存取時間比存取在XDATA段要快很多，因為存儲器直接給出地址，勝于由存儲指針如DPTR必須先初始化。因此，通常將已用變量和臨時定義變量都放在數(shù)據(jù)段。然而，這樣的分配會占用段中少量的存儲單元。數(shù)據(jù)段中的可變存儲器還可以由R0或R1間接存儲。使用寄存器作存儲指針就必須包含已檢索或已改變字節(jié)的地址。這些指令可以依靠源/目的數(shù)據(jù)字節(jié)使一個或二個處理機循環(huán)。數(shù)據(jù)段又包含兩個重要的小段。第一個子段由四個寄存器組組成，它占用了RAM的低32字節(jié)。8051用這四組（每組8字節(jié)）作為缺省寄存器組。寄存器組選定區(qū)域在任何時候都通過處理機狀態(tài)字（PSW）中的RS1和RS0這兩位來改變。這兩位組合表示數(shù)0~3（RS1作最高有效位），用來指明哪個寄存器組在被使用。在8051中，寄存器組開關(guān)不但允許快速參數(shù)傳遞，而且能打開單任務(wù)開關(guān)。在數(shù)據(jù)空間的第二個子段是一個可尋址位段，每一位都能單獨存取。這個段稱為BDATA段?？蓪ぶ返奈欢斡蓛?nèi)存中四個寄存器組16字節(jié)（128位）組成。8051包含許多位指令，它通常用于控制某一位的應(yīng)用及在8051中用軟件替換外部組合邏輯給予幫助，這樣在目標系統(tǒng)中以減少部分依賴。人們注意到這個16字節(jié)還可以按“一位”寬在數(shù)據(jù)空間像其他字節(jié)一樣進行存取。特殊功能寄存器8051內(nèi)部RAM的80H以上的單元為控制寄存器，包含中斷系統(tǒng)和外部設(shè)備。這些寄存器稱為特殊功能寄存器（簡稱SFR）。它們大部分是可按位尋址的。在可按位尋址的SFR中的位可以是被訪問的名稱、索引或者是位地址。因此，你可以參看中斷允許SFR中的EA（EA、IE.7或0AFH）位。SFR可控制的東西有：定時/計數(shù)器和UART的功能。中斷源以及它們的優(yōu)先級。這些被訪問的寄存器在數(shù)據(jù)段中的字節(jié)和位是同一張指令表。表A所示SFR的存儲圖中指明了可尋址的位寄存器。IDATA空間某些8051家族成員，如8052在內(nèi)部RAM中包含一個輔助128字節(jié)，存放在80H以上的單元。這個典型的RAM段被稱為IDATA段。因為IDATA地址和SFR地址重疊，IDATARAM和SFR之間的地址沖突是通過分解被存取存儲器的類型來解決，因為IDATA段只能通過間接尋址方式存取。XDATA空間8051存儲空間為64K，代碼段可用16根地址線尋址。這個典型空間被稱為外部數(shù)據(jù)存儲空間（簡稱XDATA段）。這個段通常由各種RAM（通常為SRAM）、I/O設(shè)備或外圍設(shè)備組成，8051必須通過總線連接。這個段的讀或?qū)懖僮髦辽傩鑳纱窝h(huán)處理，并且它的執(zhí)行既要用到DPTR又要用到R0和R1。就DPTR來說，它通常要在執(zhí)行讀或?qū)懖僮魉蟮膬蓚€循環(huán)外再附加加載兩個或更多循環(huán)處理地址。同樣，在一個周期內(nèi)除了利用存儲器自身存取之外，至少要加載R0或R1。顯而易見，XDATA段的典型操作很簡單，通常最少需三個循環(huán)處理。因此，數(shù)據(jù)段常用來存儲常用變量。如果8051不需要用總線執(zhí)行任何I/O設(shè)備或者設(shè)計者希望當I/O設(shè)備通過總線存取時讓RAM循環(huán)開、關(guān)，那么它可使這個段全部占滿64KRAM。微機接口微機接口實現(xiàn)兩種信息形式的交換。在計算機之外，由電子系統(tǒng)所處理以一種物理形式存在，但在程序中，它是用數(shù)字表示的。任一接口的功能都可分為以某種形式進行數(shù)據(jù)變換的一些操作，所以外部和內(nèi)部形式的轉(zhuǎn)換由許多步驟完成的。所示的情況為例加以說明，圖中展示了微計算機和產(chǎn)生的信號和形式被系統(tǒng)的其他部分處理之前需要再次轉(zhuǎn)換.舉例來說，許多傳感器具有電阻變化，這必須由一專門電路轉(zhuǎn)換成電壓。這種將傳感器輸出轉(zhuǎn)換成電壓信號，并與系統(tǒng)的其他電路相連接的過程，稱為信號調(diào)理。信號調(diào)理部分將源自傳感器的電壓或電流信號范圍轉(zhuǎn)換用模擬－數(shù)字轉(zhuǎn)換器變成數(shù)字形式的信號范圍。一個模擬－數(shù)字轉(zhuǎn)換器（ADC）用來將連續(xù)變化信號變成相應(yīng)的數(shù)字量，這數(shù)字量可是可能的二進制數(shù)值中的一個固定值。如果傳感器輸出不是連續(xù)變化的，就不需要模擬－數(shù)字轉(zhuǎn)換。這種情況下，信號調(diào)理單元必須將輸入信號變換成為另一信號，也可直接與接口的下一部分，即微計算機本身的輸入輸出相連接。輸入／輸出單元將數(shù)字＂開／關(guān)＂電壓信號轉(zhuǎn)換成能通過系統(tǒng)總線傳送到系統(tǒng)總線傳送到計算機的信號。這里每一根線的狀態(tài)，無論是＂開＂或是＂關(guān)＂，用相應(yīng)的＂1＂或＂0＂表示。對于已經(jīng)轉(zhuǎn)換成數(shù)字形式的模擬輸入量，內(nèi)部表示中用1和0組成的排列形式形成與補轉(zhuǎn)換量相對應(yīng)的二進制數(shù)。從接口得到的原數(shù)值會受到接口電路設(shè)計的限制，而且常需要線性化和量程調(diào)整才能形成適合于在主程序中使用的數(shù)值。舉例來說，接口可用于轉(zhuǎn)換范圍為－20oC至50oC的溫度，而8位轉(zhuǎn)換器所產(chǎn)生的數(shù)值會在范圍0至255之間。顯然，從程序員的觀點，對溫度進行直接的處理要比使用由ADC所產(chǎn)生的與一個給定溫度相一致的值要容易。接口操作需要將控制信號在微機和接口之間進行傳送。根據(jù)這些理由，通常使用子程序來監(jiān)督接口的具體操作，并完成任何所需的量程調(diào)整和/或線性化。輸出接口采用相似的形式，明顯的差別在于信息流的方向相反;是從程序到外部世界。這種情況下，程序可稱為輸出程序，它監(jiān)督接口的操作并完成數(shù)字-模擬轉(zhuǎn)換器（DAC）所需數(shù)字的標定。該子程序依次送出信息給輸出器件，產(chǎn)生相應(yīng)的電信號，由DAC轉(zhuǎn)換成模擬形式。最后，信號經(jīng)調(diào)理（通常是放大）以形成適應(yīng)于執(zhí)行器操作的形式。數(shù)字接口電路在微機電路中使用的信號幾乎總是太小而不能被直接地連到“外部世界”，因而必須用某種形式將其轉(zhuǎn)換成更適宜的形式。接口電路部分的設(shè)計是使用微機的工程師所面臨最重要的任務(wù)之一。我們已經(jīng)了解到微機中，信息以離或散的位形式表示。當微機要與只有打開或關(guān)閉操作的設(shè)備相連時，這種數(shù)字形式是最有用的，這里每一位都可表示一個開關(guān)或執(zhí)行器的狀態(tài)。連接邏輯電路時，必須小心翼翼，以保證它們的邏輯電平和電流額定值是兼容的。由邏輯電路產(chǎn)生的輸出電壓通以拉出或灌入最大額定電流時，按最弱情況下數(shù)值所定義。這樣VOH是當拉出最大額定“高”輸出電流IOH時的允許最小“高”電壓，而VOL,則是當灌入最大額定“低”輸出電流IOL時允許最“低”電壓。對邏輯輸入也有相應(yīng)的參數(shù)，規(guī)定最小輸入電壓為邏輯“高”狀態(tài)VIH，以及最大輸入電壓為邏輯“低”狀態(tài)VIL。對于輸入接口，也許設(shè)計所面臨的主要問題是電噪聲，小噪聲信號會引起系統(tǒng)工作不良，而大量的噪聲會造成永久性損壞。設(shè)計者必須從一開始就清楚這些危險。有許多方法保護接口電路和微機不受各種各樣噪聲影響，下面是一些例子：1.使用光電隔離或變壓器實現(xiàn)微機系統(tǒng)和外部器件之間的輸入輸出電信號隔離。2.用一低通濾器和施密特觸發(fā)器排除高頻噪聲脈沖。3.用一對二極管以反向偏置于正常方向的形式連接至電源端，來保護過高的輸入電壓。對于輸出接口，一個邏輯器件的參數(shù)VOH，VOL，IOH，和IOL往往太小而不能直接與負載相連，實踐中必須在一個外部將電流和電壓進行放大以驅(qū)動一個負載。現(xiàn)在盡管有一些類型的半導(dǎo)體器件可用于DC和AC的功率控制至若干千瓦，有兩種基本方式將連至負載，并對其進行控制：串聯(lián)連接和并聯(lián)連接。對于串聯(lián)連接，開關(guān)閉合時使電流渡過負載，而當并聯(lián)連接時合上開關(guān)將使電流繞過負載。兩種方式都可用于低功率電路中，但只有串聯(lián)連接才能用于高功率電路，這是因為串聯(lián)電阻R上要消耗功率。AT89C52的使用簡介AT89C52帶8K字節(jié)閃速存儲器的8位單片機特性于80C51和80C52產(chǎn)品兼容8K字節(jié)編程閃速存儲器壽命：1000次寫/擦循環(huán)，數(shù)據(jù)保留時間：10年全靜態(tài)工作：0H——24MHZ三級程序存儲器鎖定256×8位內(nèi)部RAM三個16位定時器/計數(shù)器8個中斷源可編程串行通道低功耗的閑置和掉電模式說明：AT89C52是一種帶8K字節(jié)閃速可編程可擦除只讀存儲器（PEROM）的低電壓、高性能CMOS8位為控制器。該器件采用ATMEL非易失存儲器制造技術(shù)制造，與工業(yè)標準的80C51和80C52指令集和輸出管腳相兼容。由于將多功能8位CPU和閃速存儲器組合在單個芯片中，ATMEL的AT89C52是一種高效微控制器，為很多嵌入式控制系統(tǒng)提供