關(guān)于單片機(jī)at89c51的外文翻譯5000字英文

關(guān)于單片機(jī)at89c51的外文翻譯5000字英文篇一：畢業(yè)設(shè)計外文翻譯單片機(jī)AT89C51

附件1：外文資料翻譯譯文

AT89C51

主要性能參數(shù)：

與MCS-51產(chǎn)品指令系統(tǒng)完全兼容

4K字節(jié)可重檫寫Flash閃速存儲器

1000次檫寫周期

全靜態(tài)操作：0HZ-24MHZ

三級加密程序存儲器

128*8字節(jié)內(nèi)部RAM

32個可編程I/O口線

2個16位定時/記數(shù)器

6個中斷源

可編程串行UART通道

低功耗空閑和掉電形式

功能特性概述：

AT89C51提供以下標(biāo)準(zhǔn)功能：4K字節(jié)Flash閃速存儲器，128字節(jié)內(nèi)部RAM，32個I/O口線，兩個16位定時/記數(shù)器，一個5向量兩級中斷構(gòu)造，一個全雙工串行通信口，片內(nèi)振蕩器及時鐘電路。同時，AT89C51可降至0HZ的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作形式?？臻e方式停頓CPU的工作，但允許RAM，定時/記數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內(nèi)容，但振蕩器停頓工作直到下一個硬件復(fù)位。

AT89C51是美國ATMEL公司消費的低電壓，高性能CMOS8位單片機(jī)，片內(nèi)含4kbytes的可反復(fù)擦寫的只讀程序存儲器〔PEROM〕和128bytes的隨機(jī)存取數(shù)據(jù)存儲器〔RAM〕，器件采用ATMEL公司的高密度、非易失性存儲技術(shù)消費，兼容標(biāo)準(zhǔn)MCS-51指令系統(tǒng)，片內(nèi)置通用8位中央處理器〔CPU〕和Flash存儲單元，功能強大AT89C51單片機(jī)可為您提供許多高性價比的應(yīng)用場合，可靈敏應(yīng)用于各種控制領(lǐng)域。

AT89C51方框圖

引腳功能說明

·Vcc：電源電壓

·GND：地

·P0口：P0口是一組8位漏極開路型雙向I／O口，也即地址／數(shù)據(jù)總線復(fù)用口。作為輸出口用時，每位能吸收電流的方式驅(qū)動8個TTL邏輯門電路，對端口寫“1〞可作為高阻抗輸入端用。在訪問外部數(shù)據(jù)存儲器或程序存儲器時，這組口線分時轉(zhuǎn)換地址〔低8位〕和數(shù)據(jù)總線復(fù)用，在訪問期間激活內(nèi)部上拉電阻。在FIash編程時，P0口接收指令字節(jié)，而在程序校驗時，輸出指令字節(jié)，校驗時，要求外接上拉電阻。

·P1口：P1是一個帶內(nèi)部上拉電阻的8位雙向I／O口，P1的輸出緩沖級可驅(qū)動〔吸收或輸出電流〕4個TTL邏輯門電路。對端口寫“1〞，通過內(nèi)部的上拉電阻把端口拉到高電平，此時可作輸入口。作輸入口使用時，因為內(nèi)部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流〔IIL〕。FIash編程和程序校驗期間，P1接收低8位地址。

·P2口：P2是一個帶有內(nèi)部上拉電阻的8位雙向I／O口，P2的輸出緩沖級可驅(qū)動〔吸收或輸出電流〕4個TTL邏輯門電路。對端口寫“1〞，通過內(nèi)部的上拉電阻把端口拉到高電平，此時可作輸入口，作輸入口使用時，因為內(nèi)部存在上拉電阻，某個引腳被外部信號拉低時會輸出一個電流〔IIL〕。在訪問外部程序存儲器或16位地址的外部數(shù)據(jù)存儲器〔例如執(zhí)行MOVX@DPTR指令〕時，P2口送出高8位地址數(shù)據(jù)。在訪問8位地址的外部數(shù)據(jù)存儲器〔如執(zhí)行MOVX@RI指令〕時，P2口線上的內(nèi)容〔也即特殊功能存放器〔SFR〕區(qū)中R2存放器的內(nèi)容〕，在整個訪問期間不改變。Flash編程或校驗時，P2亦接收高位地址和其它控制信號

·P3口：P3口是一組帶有內(nèi)部上拉電阻的8位雙向I／O口。P3口輸出緩沖級可驅(qū)動〔吸收或輸出電流〕4個TTL邏輯門電路。對P3口寫入“1〞時，它們被內(nèi)部上拉電阻拉高并可作為輸入端口。作輸入端時，被外部拉低的P3口將用上拉電阻輸出電流〔IIL〕。

P3口除了作為一般的I／O口線外，更重要的用途是它的第二功能，如下表所示：

P3口還接收一些用于Flash閃速存儲器編程和程序校驗的控制信號。

·RST：復(fù)位輸入。當(dāng)振蕩器工作時，RST引腳出現(xiàn)兩個機(jī)器周期以上高電平將使單片機(jī)復(fù)位。

·ALE／PROG：當(dāng)訪問外部程序存儲器或數(shù)據(jù)存儲器時，ALE〔地址鎖存允許〕輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問外部存儲器，ALE仍以時鐘振蕩頻率的l／6輸出固定的正脈沖信號，因此它可對外輸出時鐘或用于定時目的。要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲器時將跳過一個ALE脈沖。對Flash存儲器編程期間，該引腳還用于輸入編程脈沖〔PROG〕。如有必要，可通過對特殊功能存放器〔SFR〕區(qū)中的8EH單元的DO位置位，可制止ALE操作。該位置位后，只有一條MOVX和MOVC指令A(yù)LE才會被激活。此外，該引腳會被微弱拉高，單片機(jī)執(zhí)行外部程序時，應(yīng)設(shè)置ALE無效。

·PSEN：程序儲存允許〔PSEN〕輸出是外部程序存儲器的讀選通信號，當(dāng)AT89C51由外部程序存儲器取指令〔或數(shù)據(jù)〕時，每個機(jī)器周期兩次PSEN有效，即輸出兩個脈沖。在此期間，當(dāng)訪問外部數(shù)據(jù)存儲器，這兩次有效的PSEN信號出現(xiàn)。

·EA／VPP：外部訪問允許。欲使CPU僅訪問外部程序存儲器〔地址為0000H—FFFFH〕，EA端必須保持低電平〔接地〕。需注意的是：假設(shè)加密位LB1被編程，復(fù)位時內(nèi)部會鎖存EA端狀態(tài)。如EA端為高電平〔接VCC端〕，CPU那么執(zhí)行內(nèi)部程序存儲器中的指令。Flash存儲器編程時，該引腳加上+12V的編程允許電源Vpp，當(dāng)然這必須是該器件是使用12V編程電壓Vpp。

篇二：AT89C51單片機(jī)中英文對照外文翻譯文獻(xiàn)

(文檔含英文原文和中文翻譯)

中英文資料對照外文翻譯

原文：

Description

TheAT89C51isalow-power,high-performanceCMOS8-bitmicroputerwith4KbytesofFlashProgrammableandErasableReadOnlyMemory(PEROM)and128bytesRAM.ThedeviceismanufacturedusingAtmel’shighdensitynonvolatilememorytechnologyandispatiblewiththeindustrystandard

MCS-51Features:

TheAT89C51providesthefollowingstandardfeatures:4KbytesofFlash,128bytesofRAM,32I/Olines,two16-bittimer/counters,afivevectortwo-level

interruptarchitecture,afullduplexserialport,on-chiposcillatorandclockcircuitry.Inaddition,theAT89C51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialportandinterruptsystemtocontinuefunctioning.ThePowerDownModesavestheRAMcontentsbutfreezestheoscillatordisablingallotherchipfunctionsuntilthenexthardwarereset.

BlockDiagramPinDescription:

VCCSupplyvoltage.

GNDGround.

Port0

Port0isan8-bitopendrainbidirectionalI/Oport.AsanoutputporteachpincansinkeightTTLinputs.Whenisarewrittentoport0pins,thepinscanbeusedashigh

impedanceinputs.

Port0mayalsobeconfiguredtobethemultiplexedloworderaddress/databusduringaccessestoexternalprogramanddatamemory.InthismodeP0hasinternalpullups.

Port0alsoreceivesthecodebytesduringFlashprogramming,andoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.

Port1

Port1isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledloillsourcecurrent(IIL)becauseoftheinternalpullups.

Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.

Port2

Port2isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledloillsourcecurrent(IIL)becauseoftheinternalpullups.

Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses

(MOVX@DPTR).Inthisapplicationitusesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.

Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.

Port3

Port3isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledloillsourcecurrent(IIL)becauseofthepullups.

Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89C51aslistedbelow:

Port3alsoreceivessomecontrolsignalsforFlashprogrammingandverification.RST

Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.

ALE/PROG

AddressLatchEnableoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput(PROG)duringFlashprogramming.

InnormaloperationALEisemittedataconstantrateof1/6theoscillator

frequency,andmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippedduringeachaccesstoexternalDataMemory.

Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.

PSEN

ProgramStoreEnableisthereadstrobetoexternalprogrammemory.

WhentheAT89C51isexecutingcodefromexternalprogrammemory,PSENisactivatedtwiceeachmachinecycle,exceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemory.

EA/VPP

ExternalAccessEnable.EAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,EAwillbeinternallylatchedonreset.

EAshouldbestrappedtoVCCforinternalprogramexecutions.

Thispinalsoreceivesthe12-voltprogrammingenablevoltage(VPP)duringFlashprogramming,forpartsthatrequire12-voltVPP.

XTAL1

Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.

XTAL2

Outputfromtheinvertingoscillatoramplifier.

OscillatorCharacteristics

XTAL1andXTAL2aretheinputandoutput,respectively,ofaninverting

篇三：at89c51單片機(jī)外文翻譯

THEINTRODUCTIONOFAT89C51

Description

TheAT89C51isalow-power,high-performanceCMOS8-bitmicroputerwith4KbytesofFlashprogrammableanderasablereadonlymemory(PEROM).ThedeviceismanufacturedusingATMEL’shigh-densitynonvolatilememorytechnologyandispatiblewiththeindustry-standardMCS-51instructionsetandpin-out.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bybiningaversatile8-bitCPUwithFlashonamonolithicchip,theATMELAT89C51isapowerfulmicroputerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.Functioncharacteristic

TheAT89C51providesthefollowingstandardfeatures:4KbytesofFlash,128bytesofRAM,32I/Olines,two16-bittimer/counters,afivevectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillatorandclockcircuitry.Inaddition,theAT89C51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialportandinterruptsystemtocontinuefunctioning.ThePower-downModesavestheRAMcontentsbutfreezestheoscillatordisablingallotherchipfunctionsuntilthenexthardwarereset.

PinDescription

VCC：Supplyvoltage.

GND：Ground.

Port0：

Port0isan8-bitopen-drainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedasthehighimpedanceinputs.Port0mayalsobeconfiguredtobethemultiplexedreference

address/databusduringaccessestoexternalprogramanddatamemory.InthismodeP0hasinternalpull-ups.Port0alsoreceivesthecodebytesduringFlashprogramming,andoutputsthecodebytesduringprogramverification.Externalpull-upsarerequiredduring-1-

programverification.

Port1

Port1isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pinstheyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledloillsourcecurrent(IIL)becauseoftheinternalpull-ups.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.Port2

Port2isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pinstheyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledloillsourcecurrent,becauseoftheinternalpull-ups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses.Inthisapplication,itusesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses,Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.

Port3

Port3isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pinstheyarepulledhighbytheinternalpull-upsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledloillsourcecurrent(IIL)becauseofthepull-ups.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89C51aslistedbelow:

-2-

Port3alsoreceivessomecontrolsignalsforFlashprogrammingandverification.

RST

Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.

ALE/PROG

AddressLatchEnableoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput(PROG)duringFlashprogramming.InnormaloperationALEisemittedataconstantrateof1/6theoscillatorfrequency,andmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippedduringeachaccesstoexternalDataMemory.

Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicro-controllerisinexternalexecutionmode.

PSEN

ProgramStoreEnableisthereadstrobetoexternalprogrammemory.WhentheAT89C51isexecutingcodefromexternalprogrammemory,PSENisactivatedtwiceeachmachinecycle,exceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemory.

EA/VPP

ExternalAccessEnable.EAmustbestrappedtoGNDinordertoenablethedeviceto

-3-

fetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,EAwillbeinternallylatchedonreset.EAshouldbestrappedtoVCCforinternalprogramexecutions.Thispinalsoreceivesthe12-voltprogrammingenablevoltage(VPP)duringFlashprogramming,forpartsthatrequire12-voltVPP.

XTAL1

Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.

XTAL2

Outputfromtheinvertingoscillatoramplifier.

OscillatorCharacteristics

XTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierwhichcanbeconfiguredforuseasanon-chiposcillator,asshowninFigure1.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdrivenasshowninFigure2.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclockingcircuitryisthroughadivide-by-twoflip-flop,butminimum

andmaximumvoltagehighandlowtimespecificationsmustbeobserved.

Figure1.OscillatorConnectionsFigure2.ExternalClockDriveConfiguration

-4-

IdleMode

Inidlemode,theCPUputsitse