論出口對中國經(jīng)濟(jì)增長的貢獻(xiàn)及TMS320C5402外文文獻(xiàn)及譯文

PAGE論出口對中國經(jīng)濟(jì)增長的貢獻(xiàn)內(nèi)容提要：本文使用一種叫做自回歸分布滯后—非約束誤差糾正模型(ARDL-UECM)的方法來檢驗(yàn)Thirlwall定律在中國的適用性，并測度長期中出口對經(jīng)濟(jì)增長的貢獻(xiàn)程度。結(jié)果表明，長期中，Thirlwall定律在中國成立。1980—2010年間，出口每增長10%，將推動(dòng)GDP增長約1.8%。這個(gè)值大于林毅夫和李XX2003年估計(jì)的1%，這表明他們的估計(jì)方法存在的缺陷可能確實(shí)對結(jié)果產(chǎn)生了較大的影響。出口對經(jīng)濟(jì)增長的影響如此之大，所以我國有必要保持外貿(mào)的穩(wěn)定增長。關(guān)鍵詞：出口，中國經(jīng)濟(jì)增長，Thirlwall定律，ARDLUECM方法作者簡介：王俊杰，華中科技大學(xué)經(jīng)濟(jì)學(xué)院一、引言1978—2010年，我國對外貿(mào)易取得了飛速發(fā)展，進(jìn)出口總額從1978年的206.4億美元增加到2010年的29727.6億美元，其中進(jìn)口從108.9億美元增加到13948.3億美元，出口從97.5億美元增加到15779.3億美元。折算成增長率，進(jìn)口年均增長16.37%，出口年均增長17.23%，而同期中國GDP年均增長9.9%。出口對于經(jīng)濟(jì)增長的巨大作用得到了許多文獻(xiàn)的證實(shí)(Thirlwall，1979，1983，2003；Feder，1983；徐長生和莊佳強(qiáng)，2008；Jeon，2008)。林毅夫和李XX(2003)還實(shí)證研究了出口對中國經(jīng)濟(jì)的貢獻(xiàn)程度，結(jié)果表明，20世紀(jì)90年代，外貿(mào)出口每增長10%，基本上能夠推動(dòng)GDP增長1%。但是林毅夫和李XX的模型設(shè)定和估計(jì)方法存在問題。由于他們的基本模型受到多重共線性的困擾，他們不得不去掉多個(gè)變量，這可能對結(jié)果產(chǎn)生了重大影響。本文根據(jù)Thirlwall的理論，并使用一種叫做自回歸分布滯后—非約束誤差糾正模型(ARDL-UECM)的方法來測度出口對經(jīng)濟(jì)增長的貢獻(xiàn)程度。這種方法在測度變量之間的長期關(guān)系時(shí)非常有效，且它的一個(gè)突出的優(yōu)點(diǎn)是它允許解釋變量都是I(0)或者I(1)，或者是二者的混合，只要被解釋變量是I(1)。此外，它對于小樣本而言，也相當(dāng)有效。二、文獻(xiàn)綜述Kaldor(1957)認(rèn)為，出口是需求的一部分，出口需求的增加傾向于導(dǎo)致更好的供給條件，如更多的產(chǎn)出將導(dǎo)致更高的勞動(dòng)生產(chǎn)率，而這將反過來導(dǎo)致更多的出口需求，因?yàn)楦叩纳a(chǎn)率意味著更多的供給和更好的貿(mào)易條件。Thirlwall(1979)沿著Kaldor的思路，提出國際收支平衡約束下的經(jīng)濟(jì)增長。在開放經(jīng)濟(jì)條件下，一國經(jīng)濟(jì)要想持續(xù)增長，伴隨著經(jīng)濟(jì)增長的進(jìn)口需求增長必須由出口增長帶來的外匯收入來支持。因此，一國經(jīng)濟(jì)增長受到國際收支平衡的約束，長期中，一國經(jīng)濟(jì)增長率與出口增長率正相關(guān)，且一國經(jīng)濟(jì)要想持續(xù)增長，出口的增長速度必須快于進(jìn)口的增長速度。在Thirlwall的理論體系中，模型來自最基本的收支平衡方程：PX+EF=EPfM(1)其中，P是以本國貨幣表示的價(jià)格水平，X是對本國產(chǎn)品的出口需求，E是用一單位外國貨幣的本幣價(jià)格表示的名義匯率，F(xiàn)是以外幣表示的凈資本流入，Pf是以外幣表示的外國價(jià)格水平，M是本國的進(jìn)口需求數(shù)量。方程中，F(xiàn)＞0表示資本流入，F(xiàn)＜0則意味著資本流出。最后定義出口收入占從國外取得的總收入的比例如下：θ=PX/(PX+EF)(2)出口需求函數(shù)用常用形式：X=(P/EPf)ηZε(3)其中，Z表示貿(mào)易伙伴的實(shí)際收入，η和ε表示外國對本國出口需求的價(jià)格彈性和收入彈性。因此，如根據(jù)標(biāo)準(zhǔn)需求理論，η＜0，ε＞0。類似地，進(jìn)口需求函數(shù)表示如下：M=(EPf/P)ψYπ(4)其中，Y是國內(nèi)實(shí)際收入，ψ和π分別表示國內(nèi)對進(jìn)口產(chǎn)品需求的價(jià)格彈性和收入彈性，ψ＜0，π＞0。對(1)、(3)、(4)式兩邊取對數(shù)并微分，并利用方程(2)得：θ(p+x)+(1-θ)(e+f)=e+pf+m(5)x=η(p-e-pf)+εz(6)m=ψ(pf+e-p)+πy(7)其中小寫字母表示以上所定義變量的增長率。將(6)、(7)式代入方程(5)，并解出y，可以得到以下等式：(8)上式中，y加有下標(biāo)b表示本國收入的增長率受到國際收支平衡的約束。上式中，等式右邊第一項(xiàng)表示外生的國外收入變化通過出口需求的收入彈性對本國產(chǎn)出增長的影響；第二項(xiàng)表示貿(mào)易條件變化產(chǎn)生的影響；第三項(xiàng)則表示資本流入變化對國內(nèi)收入的影響。為了簡化模型，需要對方程(8)做出一些假設(shè)。一種假設(shè)是假設(shè)長期中貿(mào)易條件(或者說國內(nèi)外的相對物價(jià)水平)保持不變，那么就有(p-e-pf)=0和x=εz。于是可得：(9)(9)式意味著收支平衡約束下的產(chǎn)出增長率是出口增長率和資本流入增長率的加權(quán)平均。此外，還可以假設(shè)沒有資本流入或者資本流入僅占從國外取得的收入的極小一部分，因而可以忽略不計(jì)。此時(shí)，θ=1，(8)式可簡化如下：

表1中國GDP及出口增長率：1980—2010單位：%年份GDP增長率出口增長率年份GDP增長率出口增長率年份GDP增長率出口增長率19807.828.419919.223.9620029.123.3419815.218.27199214.214.8420031033.0619829.113.82199314-1.47200410.130.24198310.92.86199413.158.91200511.325.33198415.231.25199510.92.03200612.722.03198513.520.11199610-6.74200714.214.9219868.825.6119979.317.2720089.61.44198711.626.619987.81.2220099.2-17.59198811.31.1619997.67.6620101019.8619894.1-6.1720008.421.8719903.848.0620018.35.99(注：數(shù)據(jù)來源：《中國統(tǒng)計(jì)摘要2011》。出口增長率的數(shù)據(jù)是根據(jù)其中的歷年出口額計(jì)算得來；增長率都是按不變價(jià)格計(jì)算的。)(10)(10)式表明，國內(nèi)收入水平增長率由三個(gè)因素決定：進(jìn)口和出口需求的價(jià)格彈性；長期貿(mào)易條件；進(jìn)口和出口需求的收入彈性。在方程(10)加入長期貿(mào)易條件不變的假設(shè)，就可以得到：(11)根據(jù)(6)，又可得到：(12)方程(12)就是Thirlwall定律最簡單的表達(dá)式，它是在沒有資本凈流入和長期中貿(mào)易條件不變兩個(gè)假設(shè)前提下推導(dǎo)出來的。它表明有收支平衡約束下的長期產(chǎn)出增長率是由出口增長率和進(jìn)口需求的收入彈性之比決定的，且如果π為常數(shù)，那么產(chǎn)出增長率就與出口增長率存在一一對應(yīng)的關(guān)系。不過Thirlwall定律也受到較多的批評，比如，對長期中貿(mào)易條件穩(wěn)定的假設(shè)，許多經(jīng)濟(jì)學(xué)家提出了質(zhì)疑。還有，對于方程(12)中因果關(guān)系的方向，也有人提出了質(zhì)疑。不過Thirlwall認(rèn)為，長期中相對價(jià)格水平不變可能來自以下三個(gè)原因：一是一價(jià)定律；二是浮動(dòng)匯率制度；三是寡頭壟斷的市場結(jié)構(gòu)。而對于因果關(guān)系，Thirlwall遵循Kaldor的思想，認(rèn)為需求是經(jīng)濟(jì)增長的最終決定力量，因此是來自國外的需求拉動(dòng)本國經(jīng)濟(jì)增長，而不是經(jīng)濟(jì)增長促進(jìn)出口。盡管如此，對于出口與經(jīng)濟(jì)增長之間的因果關(guān)系的方向的爭論從未停休。理論上各執(zhí)一詞，實(shí)證結(jié)果也大相徑庭。所以，對于出口與經(jīng)濟(jì)增長之間的因果關(guān)系的方向，本文沒有必要深入討論。許多文獻(xiàn)證實(shí)了Thirlwall的理論，其中包括Atesoglu(1993)用美國數(shù)據(jù)的實(shí)證檢驗(yàn)，Bairam(2001)對歐洲及北美19個(gè)國家數(shù)據(jù)的檢驗(yàn)。三、模型設(shè)定與計(jì)量分析1、模型設(shè)定有必要陳述Thirlwall定律的假設(shè)在中國的符合性。第一，關(guān)于貿(mào)易條件穩(wěn)定的假設(shè)。這個(gè)假設(shè)在中國1979—2010年間并不是成立的，但是這個(gè)條件實(shí)際上在各國都很難成立，且文獻(xiàn)中也常常忽略這個(gè)假定，本文也采取相同的做法，不對這一假定做深入追究。第二，關(guān)于沒有資本凈流入的假定。這一假定在中國基本符合，因?yàn)樵谥袊磕甑馁Y本凈流入相對出口而言幾乎可以忽略不計(jì)。第三，關(guān)于出口必須快于進(jìn)口的假定。這一假定在中國也符合。上文已經(jīng)陳述，改革開放以來，中國出口年均增長17.23%，而進(jìn)口年均增長16.37%。本文選取全國1980—2010年的時(shí)間序列數(shù)據(jù)，如表1所示。為了簡化模型，本文假定進(jìn)口需求的收入彈性π是一個(gè)常數(shù)，在樣本期內(nèi)保持不變。在這里還需強(qiáng)調(diào)的是，Thirlwall定律中所說的收入增長率與出口增長率之間的關(guān)系是長期中的關(guān)系，因此，如果直接用GDP增長率對出口增長率做二元線性回歸，我們可能無法確定它們二者之間的關(guān)系。即使能得到它們之間的回歸關(guān)系，結(jié)果也極有可能是錯(cuò)誤的，因?yàn)槲覀儽仨毜每紤]時(shí)間序列相關(guān)的一系列問題。此外，由于出口增長率的波動(dòng)性相對GDP增長率的波動(dòng)性更大，直覺上我們就可以判斷一年的GDP增長率與當(dāng)年的出口增長率之間并不會有明顯的聯(lián)系。而且，我們的樣本只有31年的數(shù)據(jù)，很可能不能解釋長期中產(chǎn)出與出口之間的關(guān)系。在檢驗(yàn)變量之間長期的關(guān)系時(shí)，Pesaran等(2001)提出一種叫做自回歸分布滯后—非約束誤差糾正模型(ARDL—UECM)的方法。這種方法在檢驗(yàn)變量之間的長期關(guān)系時(shí)非常有效，且它的一個(gè)突出的優(yōu)點(diǎn)是它允許解釋變量都是I(0)或者I(1)，或者是二者的混合，只要被解釋變量是I(1)。此外，它對于小樣本而言，也相當(dāng)有效。模型形式如下：(13)其中，y是因變量，△yt是y的一階差分，xj是各個(gè)解釋變量，△xj,t-i是各解釋變量i期滯后的一階差分。l和q是滯后期數(shù)，它們并不一定相等。用普通最小二乘法估計(jì)方程(13)。為了檢驗(yàn)這些變量之間的長期關(guān)系，需要對方程(13)中所有x的滯后項(xiàng)系數(shù)都為0這個(gè)虛擬假設(shè)做檢驗(yàn)。即：H0：βj=0，j=1，…，kH1：βj≠0，j=1，…，k(14)用F-檢驗(yàn)對參數(shù)的總體顯著性進(jìn)行檢驗(yàn)。但是這個(gè)檢驗(yàn)的統(tǒng)計(jì)量并不是服從標(biāo)準(zhǔn)的F-分布，其臨界值取決于變量是I(0)還是I(1)。不過Pesaran等計(jì)算并給出了這個(gè)統(tǒng)計(jì)量的臨界值表。因此，我們可以方便地查詢臨界值。如果虛擬假設(shè)被拒絕，就說明變量之間存在協(xié)整關(guān)系，那么變量之間的協(xié)整系數(shù)就可以通過如下方式計(jì)算：pyxj=βj/(-β1)(15)即長期中，xj對y的影響系數(shù)為βj/(-β1)。對于本文所研究的收入增長率與出口增長率之間的長期關(guān)系，使用ARDL-UECM方法，我們建立如下模型：(16)其中，y表示GDP增長率，x表示出口增長率。如上文所述，還是用OLS估計(jì)這個(gè)模型，并檢驗(yàn)一下虛擬假設(shè)：H0：β1=β2=0Hi：β1≠0，β2≠0(17)如果拒絕虛擬假設(shè)，則表明GDP增長率與出口增長率之間存在協(xié)整關(guān)系，則證明GDP增長率與出口增長率之間存在長期的相關(guān)關(guān)系。2、對Thirlwall定律的計(jì)量檢驗(yàn)上文中已經(jīng)指出，使用ARDL-UECM方法，要求被解釋變量是I(1)，因此，我們需要首先對GDP增長率做一個(gè)簡單的單位根檢驗(yàn)。檢驗(yàn)顯示，GDP增長率確實(shí)存在單位根，也就是說是I(1)。此外，我們需要選擇合理的滯后項(xiàng)數(shù)，即l和q的值。根據(jù)AIC和SIC信息準(zhǔn)則，本文選擇1=1和q=2，即選擇如下模型：△yt=β0+β1yt-1+β2xt-1+b11△yt-1+b20△x+b21△xt-1+b22△xt-2+ut(18)回歸結(jié)果如表2所示。注意到，表2顯示F=4.41。查Pesaran給出的臨界值表可知，在1%的顯著性水平上，兩個(gè)臨界值分別是6.84和7.84(臨界值表見Pesaranetal.Boundstestapproachestotheanalysisoflevelrelationships.JournalofAppliedEconometrics，May/Jun，2001，p300.TableCI(iii)。本模型中，k=1。)，F(xiàn)=4.41落在臨界值之外，因此，我們可以拒絕虛擬假設(shè)，即拒絕變量之間不存在協(xié)整關(guān)系。也就是說，結(jié)果表明，GDP增長率與出口增長率之間存在很強(qiáng)的相關(guān)關(guān)系。此外，根據(jù)上文等式(15)，可以計(jì)算出產(chǎn)出增長率與出口增長率之間的相關(guān)系數(shù)為0.133/0.756≈0.18。因此，相關(guān)方程可以表示如下：y=0.18x(19)(2.12)上式中，括號中的數(shù)字是系數(shù)的t值，這個(gè)t值就是表1中變量x(-1)的系數(shù)的t值。t值顯示系數(shù)0.18在5%的顯著性水平下是顯著的。

表2GDP與出口之間的長期關(guān)系的檢驗(yàn)解釋變量被解釋變量：產(chǎn)出增長率的一階差分(D(y))常數(shù)項(xiàng)5.51(3.01)***y(-1)-0.756(--4.29)***x(-1)0.133(2.12)**D(y(-1))0.452(2.75)**D(x)0.046(1.89)*D(x(-1))-0.058(-1.31)D(x(-2))-0.024(-0.86)樣本量31調(diào)整后的R20.43F統(tǒng)計(jì)量4.41(注：括號中的數(shù)字表示t值；**和***分別表示在5%和1%的顯著性水平顯著。)以上結(jié)果表明，中國GDP增長率和出口增長率之間確實(shí)存在很強(qiáng)的正相關(guān)關(guān)系。因此，可以說明，Thirlwall定律在中國適用，即長期中，收入增長率與出口增長率正相關(guān)，出口增長10%，將推動(dòng)總產(chǎn)出增長1.8%。這個(gè)值明顯大于林毅夫和李XX2003年估計(jì)的1%，這可能表明他們的估計(jì)方法存在的缺陷確實(shí)對結(jié)果產(chǎn)生了較大的影響。林XX和李XX的方法所關(guān)心的是出口增加通過刺激消費(fèi)、投資、政府支出來間接地影響我國的GDP的增長，而沒有考慮出口增長—因而產(chǎn)出增長—對生產(chǎn)率的促進(jìn)作用。這可能就是導(dǎo)致林和李XX估計(jì)的結(jié)果偏低的原因。四、結(jié)論本文通過ARDL-UECM方法分析，證實(shí)了中國經(jīng)濟(jì)增長與出口增長之間的相關(guān)關(guān)系，驗(yàn)證了Thirlwall定律在中國的適用性，且表明1978—2010年間，出口增長10%，收入將增長1.8%，不止是林毅夫和李XX2003年估計(jì)的1%。這意味著，為了維持我國經(jīng)濟(jì)的快速增長，繼續(xù)發(fā)揮比較優(yōu)勢，保持出口的穩(wěn)定增長意義重大。

【參考文獻(xiàn)】[1]Thirlwall,A.P..Theinteractionbetweenincomeandexpenditureintheabsorptionapproachtothebalanceofpayments[J].JournalofMacroeconomics,1979,vol.1(2).[2]Thilwall,A.P..APlainMan'sGuidetoKaldor'sGrowthLaws[J].JournalofPost-KeynesianEconomics,1983,5(3).[3]Thilwall,A.P..GrowthandDevelopment:WithSpecialReferencetoDevelopingEconomies[M].7thedition.NewYork:PalgraveMacmillan,2003.[4]Feder,G.,.OnExportandEconomicGrowth[J].JournalofDevelopmentEconomics,1983(12).[5]莊佳強(qiáng)、徐長生：論出口、消費(fèi)與經(jīng)濟(jì)增長[J].國際貿(mào)易問題，2008(10).[6]Jeon,Yongbok..EconomicGrowthinChina,1978-2004:AKaldorianApproach[D].TheUniversityof[7]林毅夫、李XX：出口與中國的經(jīng)濟(jì)增長：需求導(dǎo)向的分析[J].經(jīng)濟(jì)學(xué)(季刊)，2003(7).[8]Kaldor,N..AModelofEconomicGrowth[J].EconomicJournal,1957,57(268).[9]Atesoglu,L..ManufacturingandEconomicGrowthintheUnitedStates[J].ApliedEconomics,1993(6).[10]Bairam,Erkin.Thirlwall'slawandthestabilityofexportandimportincomeelasticity[J].InternationalReviewofAppliedEconomics,2001,vol.15,No.3.[11]Pesaran,Hashem,etal..Boundstestapproachestotheanalysisoflevelrelationships[J].JournalofAppliedEconometrics,2001(May/June).本科畢業(yè)設(shè)計(jì)外文文獻(xiàn)及譯文文獻(xiàn)、資料題目：TMS320C5402文獻(xiàn)、資料來源：文獻(xiàn)、資料發(fā)表（出版）日期：院（部）：信息與電氣工程學(xué)院專業(yè)：班級：姓名：學(xué)號：指導(dǎo)教師：翻譯日期：9---外文文獻(xiàn)TMS320C5402AdvancedMultibusArchitectureWithThreeSeparate16-BitDataMemoryBusesandOneProgramMemoryBus.40-BitArithmeticLogicUnit(ALU),Includinga40-BitBarrelShifterandTwoIndependent40-BitAccumulators1717-BitParallelMultiplierCoupledtoa40-BitDedicatedAdderforNon-PipelinedSingle-CycleMultiply/Accumulate(MAC)Operation.Compare,Select,andStoreUnit(CSSU)fortheAdd/CompareSelectionoftheViterbiOperator.ExponentEncodertoComputeanExponentValueofa40-BitAccumulatorValueinaSingleCycle.TwoAddressGeneratorsWithEightAuxiliaryRegistersandTwoAuxiliaryRegisterArithmeticUnits(ARAUDataBusWithaBus-HolderFeature.ExtendedAddressingModefor1M16-BitMaximumAddressableExternalProgramSpace.4Kx16-BitOn-ChipROM.16Kx16-BitDual-AccessOn-ChipRAM.Single-Instruction-RepeatandBlock-RepeatOperationsforProgramCode.Block-Memory-MoveInstructionsforEfficientProgramandDataManagement.InstructionsWitha32-BitLongWordOperand.InstructionsWithTwo-orThree-OperandReads.ArithmeticInstructionsWithParallelStoreandParallelLoad.ConditionalStoreInstructionsFastReturnFromInterruptOn-ChipPeripheralsSoftware-ProgrammableWait-StateGeneratorandProgrammableBankSwitchingOn-ChipPhase-LockedLoop(PLL)ClockGeneratorWithInternalOscillatororExternalClockSource.TwoMultichannelBufferedSerialPorts(McBSPs).Enhanced8-BitParallelHost-PortInterface(HPI8).Two16-BitTimers,Six-ChannelDirectMemoryAccess(DMA)Controller.PowerConsumptionControlWithIDLE1,IDLE2,andIDLE3InstructionsWithPower-DownModes.CLKOUTOffControltoDisableCLKOUTOn-ChipScan-BasedEmulationLogic,IEEEStd1149.1?(JTAG)BoundaryScanLogic10-nsSingle-CycleFixed-PointInstructionExecutionTime(100MIPS)for3.3-VPowerSupply(1.8-VCore).Availableina144-PinPlasticLow-ProfileQuadFlatpack(LQFP)(PGESuffix)anda144-PinBallGridArray(BGA)(GGUSuffix).1.descriptionTheTMS320VC5402fixed-point,digitalsignalprocessor(DSP)(hereafterreferredtoasthe’5402unlessotherwisespecified)isbasedonanadvancedmodifiedHarvardarchitecturethathasoneprogrammemorybusandthreedatamemorybuses.Thisprocessorprovidesanarithmeticlogicunit(ALU)withahighdegreeofparallelism,application-specifichardwarelogic,on-chipmemory,andadditionalon-chipperipherals.ThebasisoftheoperationalflexibilityandspeedofthisDSPisahighlyspecializedinstructionset.Separateprogramanddataspacesallowsimultaneousaccesstoprograminstructionsanddata,providingthehighdegreeofparallelism.Tworeadoperationsandonewriteoperationcanbeperformedinasinglecycle.Instructionswithparallelstoreandapplication-specificinstructionscanfullyutilizethisarchitecture.Inaddition,datacanbetransferredbetweendataandprogramspaces.Suchparallelismsupportsapowerfulsetofarithmetic,logic,andbit-manipulationoperationsthatcanbeperformedinasinglemachinecycle.Inaddition,the’5402includesthecontrolmechanismstomanageinterrupts,repeatedoperations,andfunctioncalls.2.memoryThe’5402deviceprovidesbothon-chipROMandRAMmemoriestoaidinsystemperformanceandintegration.3.on-chipROMwithbootloaderThe’5402featuresa4K-word16-biton-chipmaskableROM.CustomerscanarrangetohavetheROMofthe’5402programmedwithcontentsuniquetoanyparticularapplication.AsecurityoptionisavailabletoprotectacustomROM.ThissecurityoptionisdescribedintheTMS320C54xDSPCPUandPeripheralsReferenceSet,Volume1(literaturenumberSPRU131).NotethatonlytheROMsecurityoption,andnottheROM/RAMoption,isavailableonthe’5402.Abootloaderisavailableinthestandard’5402on-chipROM.Thisbootloadercanbeusedtoautomaticallytransferusercodefromanexternalsourcetoanywhereintheprogrammemoryatpowerup.IftheMP/MCpinissampledlowduringahardwarereset,executionbeginsatlocationFF80hoftheon-chipROM.Thislocationcontainsabranchinstructiontothestartofthebootloaderprogram.Thestandard’5402bootloaderprovidesdifferentwaystodownloadthecodetoaccomodatevarioussystemrequirements:（1）Parallelfrom8-bitor16-bit-wideEPROM（2）ParallelfromI/Ospace8-bitor16-bitmode（3）Serialbootfromserialports8-bitor16-bitmode（4）Host-portinterfacebootThestandardon-chipROMlayoutisshown4.on-chipRAMThe’5402devicecontains16K16-bitofon-chipdual-accessRAM(DARAM).TheDARAMiscomposedoftwoblocksof8Kwordseach.EachblockintheDARAMcansupporttworeadsinonecycle,orareadandawriteinonecycle.TheDARAMislocatedintheaddressrange0060h–3FFFhindataspace,andcanbemappedintoprogram/dataspacebysettingtheOVLYbittoone.5.relocatableinterruptvectortableThereset,interrupt,andtrapvectorsareaddressedinprogramspace.Thesevectorsaresoft—meaningthattheprocessor,whentakingthetrap,loadstheprogramcounter(PC)withthetrapaddressandexecutesthecodeatthevectorlocation.Fourwordsarereservedateachvectorlocationtoaccommodateadelayedbranchinstruction,eithertwo1-wordinstructionsorone2-wordinstruction,whichallowsbranchingtotheappropriateinterruptserviceroutinewithminimaloverhead.Atdevicereset,thereset,interrupt,andtrapvectorsaremappedtoaddressFF80hinprogramspace.However,thesevectorscanberemappedtothebeginningofany128-wordpageinprogramspaceafterdevicereset.Thisisdonebyloadingtheinterruptvectorpointer(IPTR)bitsinthePMSTregister(seeFigure2)withtheappropriate128-wordpageboundaryaddress.AfterloadingIPTR,anyuserinterruptortrapvectorismappedtothenew128-wordpage.NOTE:Thehardwarereset(RS)vectorcannotberemappedbecauseahardwareresetloadstheIPTRwith1s.Therefore,theresetvectorisalwaysfetchedatlocationFF80hinprogramspace.6.ProcessorModeStatus(PMST)RegistersextendedprogrammemoryThe’5402usesapagedextendedmemoryschemeinprogramspacetoallowaccessofupto1024Kprogrammemorylocations.Inordertoimplementthisscheme,the’5402includesseveralfeaturesthatarealsopresentonthe’548/’549devices:Twentyaddresslines,insteadofsixteenAnextramemory-mappedregister,theXPCregister,definesthepageselection.Thisregisterismemory-mappedintodataspacetoaddress001Eh.Atahardwarereset,theXPCisinitializedto0.Sixextrainstructionsforaddressingextendedprogramspace.ThesesixinstructionsaffecttheXPC.FB[D]pmad(20bits)–FarbranchFBACC[D]Accu[19:0]–FarbranchtothelocationspecifiedbythevalueinaccumulatorAoraccumulatorBFCALL[D]pmad(20bits)–FarcallFCALA[D]Accu[19:0]–FarcalltothelocationspecifiedbythevalueinaccumulatorAoraccumulatorBFRET[D]–FarreturnFRETE[D]–FarreturnwithinterruptsenabledInadditiontothesenewinstructions,two’54xinstructionsareextendedtouse20bitsinthe’5402:READAdata_memory(using20-bitaccumulatoraddress).WRITAdata_memory(using20-bitaccumulatoraddress)Allotherinstructions,softwareinterruptsandhardwareinterruptsdonotmodifytheXPCregisterandaccessonlymemorywithinthecurrentpage.Programmemoryinthe’5402isorganizedinto16pagesthatareeach64Kinlength,asshowninFigure3.7.on-chipperipheralsThe’5402devicehasthefollowingperipherals:Software-programmablewait-stategeneratorwithprogrammablebank-switchingwaitstates.（1）Anenhanced8-bithost-portinterface(HPI8).（2）Twomultichannelbufferedserialports(McBSPs).（3）Twohardwaretimers.（4）Aclockgeneratorwithaphase-lockedloop(PLL).（5）Adirectmemoryaccess(DMA)controller.8.software-programmablewait-stategeneratorThesoftwarewait-stategeneratorofthe’5402canextendexternalbuscyclesbyuptofourteenmachinecycles.DevicesthatrequiremorethanfourteenwaitstatescanbeinterfacedusingthehardwareREADYline.Whenallexternalaccessesareconfiguredforzerowaitstates,theinternalclockstothewait-stategeneratorareautomaticallydisabled.Disablingthewait-stategeneratorclocksreducesthepowercomsumptionofthe’5402.Thesoftwarewait-stateregister(SWWSR)controlstheoperationofthewait-stategenerator.The14LSBsoftheSWWSRspecifythenumberofwaitstates(0to7)tobeinsertedforexternalmemoryaccessestofiveseparateaddressranges.Thisallowsadifferentnumberofwaitstatesforeachofthefiveaddressranges.Additionally,thesoftwarewait-statemultiplier(SWSM)bitofthesoftwarewait-statecontrolregister(SWCR)definesamultiplicationfactorof1or2forthenumberofwaitstates.Atreset,thewait-stategeneratorisinitializedtoprovidesevenwaitstatesonallexternalmemoryaccesses.9.parallelI/OportsThe’5402hasatotalof64KI/Oports.TheseportscanbeaddressedbythePORTRinstructionorthePORTWinstruction.TheISsignalindicatesaread/writeoperationthroughanI/Oport.The’5402caninterfaceeasilywithexternaldevicesthroughtheI/Oportswhilerequiringminimaloff-chipaddress-decodingcircuits.10.enhanced8-bithost-portinterfaceThe’5402host-portinterface,alsoreferredtoastheHPI8,isanenhancedversionofthestandard8-bitHPIfoundonearlier’54xDSPs(’542,’545,’548,and’549).TheHPI8isan8-bitparallelportforinterprocessorcommunication.ThefeaturesoftheHPI8include:Standardfeatures:Sequentialtransfers(withautoincrement)orrandom-accesstransfers，Hostinterruptand’54xinterruptcapability，MultipledatastrobesandcontrolpinsforinterfaceflexibilityEnhancedfeaturesofthe’5402HPI8:Accesstoentireon-chipRAMthroughDMAbus；Capabilitytocontinuetransferringduringemulationstop；TheHPI8functionsasaslaveandenablesthehostprocessortoaccesstheon-chipmemoryofthe’5402.Amajorenhancementtothe’5402HPIoverpreviousversionsisthatitallowshostaccesstotheentireon-chipmemoryrangeoftheDSP.TheHPI8memorymapisidenticaltothatoftheDMAcontrollershowninFigure7.ThehostandtheDSPbothhaveaccesstotheon-chipRAMatalltimesandhostaccessesarealwayssynchronizedtotheDSPclock.IfthehostandtheDSPcontendforaccesstothesamelocation,thehosthaspriority,andtheDSPwaitsforoneHPI8cycle.Notethatsincehostaccessesarealwayssynchronizedtothe’5402clock,anactiveinputclock(CLKIN)isrequiredforHPI8accessesduringIDLEstates,andhostaccessesarenotallowedwhilethe’5402resetpinisasserted.TheHPI8interfaceconsistsofan8-bitbidirectionaldatabusandvariouscontrolsignals.Sixteen-bittransfersareaccomplishedintwopartswiththeHBILinputdesignatinghighorlowbyte.ThehostcommunicateswiththeHPI8throughthreededicatedregisters—HPIaddressregister(HPIA),HPIdataregister(HPID),andanHPIcontrolregister(HPIC).TheHPIAandHPIDregistersareonlyaccessiblebythehost,andtheHPICregisterisaccessiblebyboththehostandthe’5402.11.multichannelbufferedserialportsThe’5402deviceincludestwohigh-speed,full-duplexmultichannelbufferedserialports(McBSPs)thatallowdirectinterfacetoother’C54x/’LC54xdevices,codecs,andotherdevicesinasystem.TheMcBSPsarebasedonthestandardserialportinterfacefoundonother’54xdevices.Likeitspredecessors,theMcBSPprovides:Full-duplexcommunication；Double-buffereddataregisters,whichallowacontinuousdatastream；Independentframingandclockingforreceiveandtransmit。Inaddition,theMcBSPhasthefollowingcapabilities:Directinterfaceto:T1/E1framers；MVIPswitchingcompatibleandST-BUScompliantdevices；IOM-2compliantdevices；Serialperipheralinterfacedevices；Multichanneltransmitandreceiveofupto128channels；Awideselectionofdatasizesincluding8,12,16,20,24,or32bits；-lawandA-lawcompanding；Programmablepolarityforbothframesynchronizationanddataclocks；Programmableinternalclockandframegeneration。TheMcBSPsconsistofseparatetransmitandreceivechannelsthatoperateindependently.TheexternalinterfaceofeachMcBSPconsistsofthefollowingpins:BCLKXTransmitreferenceclock；BDXTransmitdata；BFSXTransmitframesynchronization；BCLKRReceivereferenceclock；BDRReceivedata；BFSRReceiveframesynchronization。Thesixpinslistedarefunctionallyequivalenttopreviousserialportinterfacepinsinthe’C5000familyofDSPs.Onthetransmitter,transmitframesynchronizationandclockingareindicatedbytheBFSXandBCLKXpins,respectively.TheCPUorDMAcaninitiatetransmissionofdatabywritingtothedatatransmitregister(DXR).DatawrittentoDXRisshiftedoutontheBDXpinthroughatransmitshiftregister(XSR).ThisstructureallowsDXRtobeloadedwiththenextwordtobesentwhilethetransmissionofthecurrentwordisinprogress.12.multichannelbufferedserialports(continued)Onthereceiver,receiveframesynchronizationandclockingareindicatedbytheBFSRandBCLKRpins,respectively.TheCPUorDMAcanreadreceiveddatafromthedatareceiveregister(DRR).DatareceivedontheBDRpinisshiftedintoareceiveshiftregister(RSR)andthenbufferedinthereceivebufferregister(RBR).IftheDRRisempty,theRBRcontentsarecopiedintotheDRR.Ifnot,theRBRholdsthedatauntiltheDRRisavailable.Thisstructureallowsstorageofthetwopreviouswordswhilethereceptionofthecurrentwordisinprogress.TheCPUandDMAcanmovedatatoandfromtheMcBSPsandcansynchronizetransfersbasedonMcBSPinterrupts,eventsignals,andstatusflags.TheDMAiscapableofhandlingdatamovementbetweentheMcBSPsandmemorywithnointerventionfromtheCPU.Inadditiontothestandardserialportfunctions,theMcBSPprovidesprogrammableclockandframesynchronizationsignals.Theprogrammablefunctionsinclude:Framesynchronizationpulsewidth；Frameperiod；Framesynchronizationdelay；Clockreference(internalvs.external)；Clockdivision；Clockandframesynchronizationpolarity；Theon-chipcompandinghardwareallowscompressionandexpansionofdataineitherlaworA-lawformat.Whencompandingisused,transmitdataisencodedaccordingtospecifiedcompandinglawandreceiveddataisdecodedto2scomplementformat.TheMcBSPallowsthemultiplechannelstobeindependentlyselectedforthetransmitterandreceiver.Whenmultiplechannelsareselected,eachframerepresentsatime-divisionmultiplexed(TDM)datastream.InusingTDMdatastreams,theCPUmayonlyneedtoprocessafewofthem.Thus,tosavememoryandbusbandwidth,multichannelselectionallowsindependentenablingofparticularchannelsfortransmissionandreception.Upto32channelsinastreamofupto128channelscanbeenabled.Theclock-stopmode(CLKSTP)intheMcBSPprovidescompatibilitywiththeserialperipheralinterface(SPI)protocol.ThewordsizessupportedbytheMcBSPareprogrammablefor8-,12-,16-,20-,24-,or32-bitoperation.WhentheMcBSPisconfiguredtooperateinSPImode,boththetransmitterandthereceiveroperatetogetherasamasterorasaslave.TheMcBSPisfullystaticandoperatesatarbitrarilylowclockfrequencies.ThemaximumfrequencyisCPUclockfrequencydividedby2.13.hardwaretimerThe’5402devicefeaturestwo16-bittimingcircuitswith4-bitprescalers.ThemaincounterofeachtimerisdecrementedbyoneeveryCLKOUTcycle.Eachtimethecounterdecrementsto0,atimerinterruptisgenerated.Thetimerscanbestopped,restarted,reset,ordisabledbyspecificcontrolbits.14.clockgeneratorTheclockgeneratorprovidesclockstothe’5402device,andconsistsofaninternaloscillatorandaphase-lockedloop(PLL)circuit.Theclockgeneratorrequiresareferenceclockinput,whichcanbeprovidedbyusingacrystalresonatorwiththeinternaloscillator,orfromanexternalclocksource。15.clockgenerator(continued)Thereferenceclockinputisthendividedbytwo(DIVmode)togenerateclocksforthe’5402device,orthePLLcircuitcanbeused(PLLmode)togeneratethedeviceclockbymultiplyingthereferenceclockfrequencybyascalefactor,allowinguseofaclocksourcewithalowerfrequencythanthatoftheCPU.ThePLLisanadaptivecircuitthat,oncesynchronized,locksontoandtracksaninputclocksignal.WhenthePLLisinitiallystarted,itentersatransitionalmodeduringwhichthePLLacquireslockwiththeinputsignal.OncethePLLislocked,itcontinuestotrackandmaintainsynchronizationwiththeinputsignal.Then,otherinternalclockcircuitryallowsthesynthesisofnewclockfrequenciesforuseasmasterclockforthe’5402device.Thisclockgeneratorallowssystemdesignerstoselecttheclocksource.Thesourcesthatdrivetheclockgeneratorare:Acrystalresonatorcircuit.ThecrystalresonatorcircuitisconnectedacrosstheX1andX2/CLKINpinsofthe’5402toenabletheinternaloscillator.Anexternalclock.TheexternalclocksourceisdirectlyconnectedtotheX2/CLKINpin,andX1isleftunconnected.NOTE:Allrevisionsofthe’5402canbeoperatedwithanexternalclocksource,providedthatthepropervoltagelevelsbedrivenontheX2/CLKINpin.ItshouldbenotedthattheX2/CLKINpinisreferencedtothedevice1.8Vpowersupply(CVdd),ratherthanthe3VI/Osupply(DVdd).RefertotherecommendedoperatingconditionssectionofthisdocumentfortheallowablevoltagelevelsoftheX2/CLKINpin.Thesoftware-programmablePLLfeaturesahighlevelofflexibility,andincludesaclockscalerthatprovidesvariousclockmultiplierratios,capabilitytodirectlyenableanddisablethePLL,andaPLLlocktimerthatcanbeusedtodelayswitchingtoPLLclockingmodeofthedeviceuntillockisachieved.Devicesthathaveabuilt-insoftware-programmablePLLcanbeconfiguredinoneoftwoclockmodes:PLLmode.Theinputclock(X2/CLKIN)ismultipliedby1of31possibleratios.TheseratiosareachievedusingthePLLcircuitry.DIV(divider)mode.Theinputclockisdividedby2or4.NotethatwhenDIVmodeisused,thePLLcanbecompletelydisabledinordertominimizepowerdissipation.Thesoftware-programmablePLLiscontrolledusingthe16-bitmemory-mapped(address0058h)clockmoderegister(CLKMD).TheCLKMDregisterisusedtodefinetheconfigurationofthePLLclockmodule.Uponreset,theCLKMDregisterisinitializedwithapredeterminedvaluedependentonlyuponthestateoftheCLKMD1,CLKMD3pinsasshowninTable5.16.DMAcontrollerThe’5402directmemoryaccess(DMA)controllertransfersdatabetweenpointsinthememorymapwithoutinterventionbytheCPU.TheDMAcontrollerallowsmovementsofdatatoandfrominternalprogram/datamemoryorinternalperipherals(suchastheMcBSPs)tooccurinthebackgroundofCPUoperation.TheDMAhassixindependentprogrammablechannelsallowingsixdifferentcontextsforDMAoperation.17.featuresTheDMAhasthefollowingfeatures:TheDMAoperatesindependentlyoftheCPU._TheDMAhassixchannels.TheDMAcankeeptrackofthecontextsofsixindependentblocktransfers.TheDMAhashigherprioritythantheCPUforinternalaccesses.Eachchannelhasindependentlyprogrammablepriorities.Eachchannel’ssourceanddestinationaddressregisterscanhaveconfigurableindexesthroughmemoryoneachreadandwritetransfer,respectively.Theaddressmayremainconstant,bepost-incremented,post-decremented,orbeadjustedbyaprogrammablevalue.Eachreadorwritetransfermaybeinitializedbyselectedevents.Uponcompletionofahalf-blockoranentire-blocktransfer,eachDMAchannelmaysendaninterrupttotheCPU.TheDMA