加法計數(shù)器的設(shè)計實驗報告

EDA實驗報告書姓名xxx學(xué)號xxxxxxx實驗時間課題名稱含異步清零和同步時鐘使能的加法計數(shù)器設(shè)計實驗?zāi)康?.學(xué)習(xí)計數(shù)器的設(shè)計、仿真和硬件測試方法；2.進一步熟悉VHDL設(shè)計技術(shù)及QuatusⅡ軟件的使用方法；設(shè)計要求設(shè)計一個24進制含異步清零和同步時鐘使能的加法計數(shù)器，具體要求如下：1.清零端高電平時，信號輸出為0；使能端高電平時可以計數(shù)；2.本計數(shù)器為上升沿觸發(fā)；3.計數(shù)器的輸出為兩路信號，分別代表計數(shù)值的個位和十位；兩路信號以BCD碼輸出。設(shè)計思路根據(jù)十進制使能端加法計數(shù)器設(shè)計24進制計數(shù)器，設(shè)計異步清零；清零端高電平時，信號輸出為0；使能端高電平時可以計數(shù)?，F(xiàn)根據(jù)書上設(shè)計出24進制計數(shù)器，再通過改進，變?yōu)閮陕份敵鯞CD碼設(shè)計原理圖及源程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYssISPORT(CLK,RD,EN:INSTD_LOGIC;CQ,CP:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUT:OUTSTD_LOGIC);ENDss;ARCHITECTUREBBQOFssISSIGNALCG:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALCS:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK,RD,EN)BEGINIFRD='1'THENCG<="0000";CS<="0000";ELSIFCLK'EVENTANDCLK='1'THENIFEN='1'THENIF(CS="0010"ANDCG="0011")THENCG<="0000";CS<="0000";ELSIFCG="1001"THENCG<="0000";CS<=CS+1;ELSECG<=CG+1;ENDIF;ENDIF;ENDIF;IF(CS="0010"ANDCG="0011")THENCOUT<='1';ELSECOUT<='0';ENDIF;CQ<=CG;CP<=CS;ENDPROCESS;ENDBBQ;仿真波形圖問題討論設(shè)計一個60進制的加法計數(shù)器，具體要求與本實驗中的24進制計數(shù)器相同。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYJINZHI60ISPORT(CLK,RD,EN:INSTD_LOGIC;CQ,CP:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUT:OUTSTD_LOGIC);ENDJINZHI60;ARCHITECTUREBBQOFJINZHI60ISSIGNALCS,CG:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK,RD,EN)BEGINIFRD='1'THENCG<="0000";CS<="0000";ELSIFCLK'EVENTANDCLK='1'THENIFEN='1'THENIF(CS="0101"ANDCG="1001")THENCG<="0000";CS<="0000";ELSIFCG="1001"THENCG<="0000";CS<=CS+1;ELSECG<=CG+1;ENDIF;ENDIF;ENDIF;IF(CS="0101"ANDCG="1001")THENCOUT<='1';ELSECOUT<='0';ENDIF;CQ<=CG;CP<=CS;ENDPROCESS;ENDBBQ;利用60進制及24進制計數(shù)器設(shè)計簡易數(shù)字鐘。LIBRARY

IEEE;

USE

IEEE.STD_LOGIC_1164.ALL;

USE

IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY

JY

IS

PORT(CLK,RD,EN:IN

STD_LOGIC;

A,B,C,D:OUT

STD_LOGIC_VECTOR(3

DOWNTO

0));

END

JY;

ARCHITECTURE

WRR

OF

JY

IS

SIGNAL

H,I,J,K:STD_LOGIC_VECTOR(3

DOWNTO

0);

BEGIN

PROCESS

(CLK,RD,EN)

BEGIN

IF

RD='1'

THEN

H<="0000";

I<="0000";

J<="0000";

K<="0000";

ELSIF

CLK'EVENT

AND

CLK='1'THEN

IF

EN='1'THEN

IF(J="0110"

AND

K="0000")THEN

J<="0000";

K<="0000";

I<=I+1;

ELSIF

K="1001"THEN

K<="0000";

J<=J+1;

ELSE

K<=K+1;

IF

I="1010"THEN

I<="0000";

H<=H+1;

ELSIF

(J="0110"

AND

K="0000")THEN

J<="0000";

K<="0000";

END

IF;

IF

(H="0010"AND

I="0100")THEN

H<="0000";

I<="0000";

END

IF;

END

IF;

END

IF;

END

IF;

A<=H;B<=I;

C<=J;

D<=K;

END

PROCESS;

END

WRR;3.體會分層設(shè)計的思想。(1)實現(xiàn)了軟件之間的解耦；

(2)便于進行分工

(3)便于維護

(4)提高軟件組件的重用

(5)便于替換某種產(chǎn)品，比如持久層用的是hibernate,需要更換產(chǎn)品用toplink，就不用該其他業(yè)務(wù)代碼，直接把配置一改。

(6)便于產(chǎn)品