狀態(tài)機(jī)實(shí)驗(yàn)報(bào)告

01110100110110102、序列信號檢測器001100110000(1)建立工作庫文獻(xiàn)夾，輸入設(shè)計(jì)項(xiàng)目VHDL代碼，如下：BRARYIEEELLENTITYsmachineISPORTclkresetstateinput:INSTD_LOGIC;mboutputOUTSTDLOGICDsmachineARCHITECTUREbehavOFs_machineISTYPEFSMSTISs,s1,s2,s3);NALcurrentstatenextstateFSMSTINREGPROCESSresetclkINIFresetTHENcurrent_state<=s0;ELSIFCLK'EVENTANDCLK='1'THENrentstatenextstatEDIFPROCESSMPROCESScurrentstatenextstateINSEcurrentstateISWHENs>comb_output<='0';IFstateinputTHENnext_state<=s0;ELSEnextstates;DIFWHENs>comb_output<='0';IFstateinputTHENnext_state<=s0;ELSEnextstates;DIFWHENs>comb_output<='0';IFstateinputTHENnext_state<=s0;ELSEnextstates;DIFWHENs>comb_output<='1';IFstateinputTHENnext_state<=s0;ELSEnextstates;DIFDcasePROCESSbehav(2)對其進(jìn)行波形仿真，如下圖：3)將其轉(zhuǎn)換成可調(diào)用元件如圖：、信號檢測器入設(shè)計(jì)項(xiàng)目VHDL代碼，如下：LIBRARYIEEE;USEIEEESTDLOGIC1164.ALL;ENTITYSCHKISPORTDINCLKCLR:INSTD_LOGIC;CVECTORDSCHKARCHITECTUREbehavOFSCHKISSIGNALQ:INTEGERRANGE0TO5;SIGNALDSTDLOGICVECTOR(5DOWNTO0);IND<="11010";PROCESS(CLK,CLR)INIFCLR='1'THENQ<=0;ELSIFCLKEVENTANDCLK='1'THENCASEQISWHEN0=>IFDIN=D(4)THENQ<=1;ELSEQ<=0;ENDIF;WHEN1=>IFDIN=D(3)THENQ<=2;ELSEQ<=0;ENDIF;WHEN2=>IFDIN=D(2)THENQ<=3;ELSEQ<=2;ENDIF;WHEN3=>IFDIN=D(1)THENQ<=4;ELSEQ<=0;ENDIF;WHEN4=>IFDIN=D(0)THENQ<=5;ELSEQ<=2;ENDIF;WHENOTHERS=>Q<=0;ENDCASE;ENDIF;ENDPROCESS;PROCESS(Q)INIFQ=5THENss<="1";ELSEss<="0";ENDIF;ENDPROCESS;EN