集成電路設(shè)計-10-系統(tǒng)設(shè)計-3

集成電路設(shè)計第10章 系統(tǒng)設(shè)計（3）-設(shè)計方法學(xué)

DesignMethodologies1EIS-WuhanUniversity綱要概述實(shí)現(xiàn)方法基于單元的設(shè)計基于陣列的設(shè)計2EIS-WuhanUniversity1.概述

——TheDesignProductivityChallengeSource:sematech97Agrowinggapbetweendesigncomplexityanddesignproductivity1981LogicTransistorsperChip(K)Productivity(Trans./Staff-Month)19831985198719891991199319951997199920012003200520072009ASimpleProcessorMEMORY數(shù)據(jù)通路DATAPATHCONTROLINPUT-OUTPUTINPUT/OUTPUT互連網(wǎng)絡(luò)4EIS-WuhanUniversityASystem-on-a-Chip:ExampleCourtesy:Philips5EIS-WuhanUniversitycanbeimplementedwith：

Hardwareprocessor+suitablesoftwareprograms(flexibility)a.PentiumIV+suitablesoftwareprograms(high-levellanguage)b.TI-DSP+suitablesoftwareprogramsc.MCU(8051)+suitablesoftwareprograms(low-levellanguage)Dedicatedhardwarecircuits(faster)a.old_PCBs(TTLSSI,MSIchipsandwires)b.new_PCBs(somedevices,applicationspecificintegratedcircuit-ASIC,wires)Somehardwarecircuits+softwareprograms(tosolvemorecomplexproblems)a.Systemonaboard(memory,processor,ASIC,I/O,otherdevices)b.Systemonachip(SoC)currentandfutureworkHardwareImplementationMethodsandAlgorithmsareusedtosolvesomespecificproblems.memoryCPUASICI/ORISC-ARMPCIUSBUARTIEEE1394ASIC6EIS-WuhanUniversityHierarchicalComponentsinPCBDescribethecircuitswithHardwareDescriptionLanguage(HDL)2.Synthesisthecircuits….

applicationspecificintegratedcircuit(ASIC,ICorchip)7EIS-WuhanUniversity

Choosethedesignentrymethod:SchematicGateleveldesignIntuitive&easytodebugHDL(HardwareDescriptionLanguage)Descriptive&portableEasytomodifyMixedHDL&Schematic…DesignEntryforVLSISystemalways@(IN)beginOUT=(IN[0]|IN[1])&(IN[2]|IN[3]);end8EIS-WuhanUniversity2.實(shí)現(xiàn)方法ImplementationChoicesCustomStandardCellsCompiledCellsMacroCellsCell-based預(yù)擴(kuò)散Pre-diffused(GateArrays)預(yù)布線Pre-wired(FPGA's)Array-based半定制SemicustomDigitalCircuitImplementationApproaches9EIS-WuhanUniversityTheCustomApproachIntel4004CourtesyIntel可重復(fù)使用；周期長；適用于大批量生產(chǎn),成本分擔(dān)；NoCPLDorFPGAsolutions;Analogcircuits;Tomakesystem

smaller;成本不是主要設(shè)計準(zhǔn)則。10EIS-WuhanUniversityFullCustomDesignCMOSInverterinoutdonebychipdesignerdonebyFabPacking,Testingmasking11EIS-WuhanUniversityTransitiontoAutomationandRegularStructuresIntel4004(‘71)Intel8080Intel8085Intel8286Intel848612EIS-WuhanUniversitySemiCustomDesignProductspecificationModelingwithHDLSynthesis(byusingsuitablestandardcell)SimulationandverificationPhysicalplacementandlayoutTape-out(realchip)Testing--implementedwithsuitabletools--implementedbysuitabletoolsandmechanisms--implementedbysuitableFabcompaniesFPGAorCPLDRealASICchiplessflexible,longdesigncycle,larger-scaleproductiontoreducepricemoreflexible,shorterdesigncycle,suitableforsmallerproductionStandardcellPLDFab(TSMC,UMC,..)Twodifferentsolutions:Xilinx,Altera13EIS-WuhanUniversity3.基于單元的設(shè)計

Cell-basedDesign(orstandardcells)Routingchannel

requirementsarereducedbypresenceofmoreinterconnectlayers14EIS-WuhanUniversityCellsarecharacterizedandstoredinlibraryNeedupdatewhentechnologyadvanceNeedtechnologymappingbeforelayoutforeachdesignStandardCells15EIS-WuhanUniversityStandardCell—Example[Brodersen92]16EIS-WuhanUniversityStandardCell–TheNewGenerationCell-structurehiddenunder

interconnectlayers17EIS-WuhanUniversityStandardCell-Example3-inputNANDcell(fromSTMicroelectronics):C=LoadcapacitanceT=inputrise/falltime18EIS-WuhanUniversityPLA-ProgrambleLogicArrayx0x1x2ANDplanex0x1x2ProducttermsORplanef0f1早期的設(shè)計自動化—結(jié)構(gòu)化設(shè)計19EIS-WuhanUniversityTwo-LevelLogicInvertingformat(NOR-NOR)moreeffectiveEverylogicfunctioncanbe

expressedinsum-of-products

format(AND-OR)minterm20EIS-WuhanUniversityPLALayout–ExploitingRegularityVDDGNDfAnd-PlaneOr-Plane21EIS-WuhanUniversity復(fù)雜性超過單元庫中單元的程度Megacell（巨單元）Hard—具有指定功能，及預(yù)先確定的物理設(shè)計。Soft—具有指定功能，但無預(yù)先確定的物理設(shè)計。MacroModules22EIS-WuhanUniversityhard-macro

Modules256

32(or8192bit)SRAMGeneratedbyhard-macromodulegenerator23EIS-WuhanUniversity“Soft”MacroModulesSynopsysDesignCompiler24EIS-WuhanUniversityInsidethe22v10“Macrocell”Block

Outputsmayberegisteredorcombinational,positiveorinverted

RegisteredoutputmaybefedbacktoANDarrayforFSMs,etc.25EIS-WuhanUniversityInput/OutputEquivalentSchematics26EIS-WuhanUniversity“IntellectualProperty”AProtocolProcessorforWireless27EIS-WuhanUniversity4.Semicustom（半定制）DesignFlowHDLLogicSynthesisFloorplanningPlacementRoutingTape-outCircuitExtractionPre-LayoutSimulationPost-LayoutSimulationStructuralPhysicalBehavioralDesignCaptureDesignIteration28EIS-WuhanUniversity時序最終確定

The“DesignClosure(設(shè)計收斂)”ProblemCourtesySynopsysIterativeRemovalofTimingViolations(whitelines)DesignclosureistheprocessbywhichaVLSIdesignismodifiedfromitsinitialdescriptiontomeetagrowinglistofdesignconstraintsandobjectives.29EIS-WuhanUniversityIntegratingSynthesiswithPhysicalDesignArtworkPhysicalSynthesisRTL(Timing)ConstraintsPlace-and-Route

OptimizationNetlistwithPlace-and-RouteInfoMacromodulesFixednetlists30EIS-WuhanUniversityPre-diffused(GateArrays)Pre-wired(FPGA's)Array-based5.基于陣列的設(shè)計方法31EIS-WuhanUniversity預(yù)擴(kuò)散（掩模）陣列

GateArray（Sea-of-gates）編程前VDDGNDpolysiliconmetalpossiblecontact編程后(4-inputNOR)In1In2In3In4Out32EIS-WuhanUniversity門海Sea-of-gate

幾何隔離oxide-isolation柵隔離gate-isolation無布線通道PrimitiveCells柵隔離關(guān)斷晶體管NMOS接GNDPMOS接VDD可用于并聯(lián)33EIS-WuhanUniversitySea-of-gatesRandomLogicMemorySubsystemLSILogicLEA300K(0.6mmCMOS)34EIS-WuhanUniversity預(yù)布線陣列PrewiredArraysBasedonProgrammingTechnique熔絲Fuse-based(program-once)非易失EPROMRAMbasedProgrammableLogicStyleArray-Based查找表Look-upTableProgrammableInterconnectStyleChannel-routingMeshnetworks35EIS-WuhanUniversityFuse-BasedFPGAantifuse

polysiliconONOdielectric絕緣電介質(zhì)n+

antifusediffusion2λFromSmith97Openbydefault,closedbyapplyingcurrentpulse氧化物-氮化物-氧化物36EIS-WuhanUniversityProgrammableArrayLogic(PAL)anycombinationallogiccanberealizedasasum-of-products

PALsfeature—anarrayofAND-ORgateswithprogrammableinterconnect37EIS-WuhanUniversityArray-BasedProgrammableLogicDevice（PLD）IndicatesprogrammableconnectionIndicatesfixedconnectionPROMPLAI5I4O0I3I2I1I0O1O2O3ProgrammableANDarrayProgrammableORarrayPALI5I4O0I3I2I1I0O1O2O3ProgrammableANDarrayFixedORarrayO0I3I2I1I0O1O2O3FixedANDarrayProgrammableORarray38EIS-WuhanUniversityProgrammingaPROMf01X2X1X0f1NANA:programmednode39EIS-WuhanUniversityMoreComplexPALiinputs,j

minterms/macrocell,kmacrocells2iXjk40EIS-WuhanUniversity可編程ASIC的基本資源位于芯片中央的可編程功能單元分布于芯片各處的可編程布線位于芯片四周的可編程IO1.固定功能的功能單元2.基于SRAM查找表結(jié)構(gòu)的功能單元3.基于多路開關(guān)結(jié)構(gòu)的功能單元41EIS-WuhanUniversityLogicCellofActelFuse-BasedFPGAMUXasFunctionBlockF=A?S’+B?S42EIS-WuhanUniversityLook-upTableBasedLogicCell0功能為查找表的SRAM構(gòu)成的函數(shù)發(fā)生器。43EIS-WuhanUniversityLUT-BasedLogicCellCourtesyXilinxD4C1....C4xxxxxxD3D2D1F4F3F2F1LogicfunctionofxxxLogicfunctionofxxxLogicfunctionofxxxxxxx4xxxxxxxxxxxxxxxxxxxxxxxxxxxxxHPBitscontrolBitscontrolMultiplexerControlledbyConfigurationProgramxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxXilinx4000SeriesFFunction.(4輸入查找表)2bit寄存器44EIS-WuhanUniversityArray-BasedProgrammableWiringInput/outputpinProgrammedinterconnectionInterconnectPointHorizontaltracksVerticaltracksCellM45EIS-WuhanUniversityMesh-basedInterconnectNetworkSwitchBoxConnectBoxInterconnect

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