數(shù)字電路系統(tǒng)設(shè)計(jì)中英文課件教程 05 組合邏輯設(shè)計(jì)實(shí)踐- Combinational Logic Design Practices (2)

DIGITALSYSTEMDESIGNESHINEeshine.li@5.6Three-StateDevices

(三態(tài)器件)Three-StateBuffer(Three-StateDriver)

[三態(tài)緩沖器（三態(tài)驅(qū)動(dòng)器）]ThreeStates:ActiveHigh(1)，ActiveLow(0),Hi-Z

(三種狀態(tài)：高電平，低電平，高阻態(tài)）Variousthree-statebuffers:(a)noninverting,active-highenable;(b)non-inverting,active-lowenable;(c)inverting,active-highenable;(d)inverting,active-lowenable.5.6Three-StateDevices

(三態(tài)器件)Three-StateDeviceallowMultipleSourcestoShareaSingle“PartyLine“aslongasOnlyOnedevice“talk”ontheLineatatime三態(tài)器件允許多個(gè)信號(hào)源共享單個(gè)"同線",條件是每次只有一個(gè)器件工作Eightsourcessharingathree-statepartyline.5.6Three-StateDevices

(三態(tài)器件)TypicalThree-StateDevicesareDesignedSothattheygointotheHi-ZstateFasterthantheycomeoutoftheHi-Zstate.對(duì)典型的三態(tài)器件，進(jìn)入高阻態(tài)比離開高阻態(tài)的時(shí)間快

5.6Three-StateDevices

(三態(tài)器件)74x125：activelow,noninverting

低電平使能，輸出不反相74x126：activehigh,noninverting

高電平使能，輸出不反相Independentenableinputs獨(dú)立使能

StandardSSIandMSIThree-StateBuffer

(標(biāo)準(zhǔn)SSI和MSI三態(tài)緩沖器)Pinoutsofthe74x125and74x126threestatebuffers.5.6Three-StateDevices

(三態(tài)器件)

StandardSSIandMSIThree-StateBuffer

(標(biāo)準(zhǔn)SSI和MSI三態(tài)緩沖器)74x541：commonenableinputs,activelow兩個(gè)公共使能端，低電平使能，Schmitttrigger,noninverting施密特觸發(fā)輸入，輸出不反相The74x541octalthree-statebuffer:(a)logicdiagram,includingpinnumbersforastandard20-pindualin-linepackage;(b)traditionallogicsymbolABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EN1EN2_LEN3_LSSRC0SSRC1SSRC2沖突（fighting）Designcontrollogicthatguaranteesadeadtimeduringwhichnooneisdrivingit.利用使能端進(jìn)行時(shí)序控制Three-StateDeviceallowMultipleSourcestoShareaSingle“PartyLine“三態(tài)器件允許信號(hào)共享單個(gè)“同線”P0P1P7SDATATypicalThree-StateDevicesareDesignedsothattheygointotheHi-ZstateFasterthantheycomeoutoftheHi-Zstate.對(duì)典型的三態(tài)器件，進(jìn)入高阻態(tài)比離開高阻態(tài)的時(shí)間快EN1EN2_L,EN3_Lmax(tpLZmax,tpHZmax)min(tpZLmin,tpZHmin)SSRC[2:0]01237SDATAP0P1P2P3P7DeadTime(截止時(shí)間)A1A8G1G2Y1Y874x541DB[0:7]A1A8G1G2Y1Y874x541NotationofDataBus（數(shù)據(jù)總線的表示法）A1B1DIRTransferDatainEitherDirectionsByUsingThree-StateTransceiver(利用三態(tài)緩沖器實(shí)現(xiàn)數(shù)據(jù)雙向傳送)BusTransceiver(總線收發(fā))DIRG_L5.7Multiplexer（多路復(fù)用器）DigitalSwitch,Multi-Switch,DataSelector(又稱數(shù)據(jù)開關(guān)、多路開關(guān)、數(shù)據(jù)選擇器)（縮寫：MUX）

UnderSelectControllingSignals,SelectOneoftheMulti-InputstotheOutput

(在選擇控制信號(hào)的作用下，從多個(gè)輸入數(shù)據(jù)中選擇其中一個(gè)作為輸出。)5.7Multiplexer（多路復(fù)用器）ENSELD0Dn-1YEnable使能Select選擇N1bitDatasourcen個(gè)1位數(shù)據(jù)源Dataoutput(1bit)數(shù)據(jù)輸出（1位）ENSELD0Dn-1YEnable(使能)Select(選擇)NbbitsDataSourcesn個(gè)b位數(shù)據(jù)源DataOutput(bbits)(數(shù)據(jù)輸出)（b位）EN_LCBAYY_L1XXX0000000100100011010001010110011101D0D0’D1D1’D2D2’D3D3’D4D4’D5D5’D6D6’D7D7’(8輸入1位多路復(fù)用器)TruthTablefora74x151ABC8-Input,1-bitMultiplexerinput輸入G_LS1X000100001A2A3A4A1B2B3B4B(2輸入4位多路復(fù)用器)TruthTablefora74x157output輸出1Y2Y3Y4Y1A2A3A4A2-Input,4-bitMultiplexer1G_L2G_LBA1Y2Y11XX000000010010001101000101011001111000100110101011

001C02C01C12C11C22C21C32C31C001C101C201C30

02C002C102C202C3(4輸入2位多路復(fù)用器74x153真值表)AB1G2GTruthTablefora74x1534-Input,2-bitMultiplexerDual4-to-1雙4選1ExpandingMultiplexers

(擴(kuò)展多路復(fù)用器)ExpandingBit(擴(kuò)展位)HowtoRealize8-Input,16-bitMultiplexer?

(如何實(shí)現(xiàn)8輸入，16位多路復(fù)用器？)From8-Input,1-bitto8-Input,16-bit

(由8輸入1位8輸入16位)Need1674x151,EachChipProcess1-bit

(需要16片74x151，每片處理輸入輸出中的1位)ExpandingMultiplexers

(擴(kuò)展多路復(fù)用器)ExpandingBit(擴(kuò)展位)Select-InputsConnecttoC,B,AofEachChip(選擇端連接到每片的C,B,A)Note:TheFanoutAbilityofSelectfield

(注意：選擇端的扇出能力)（驅(qū)動(dòng)16個(gè)負(fù)載）ENYYABCD0D7ExpandingMultiplexers

(擴(kuò)展多路復(fù)用器)ExpandingInputs(擴(kuò)展數(shù)據(jù)輸入端的數(shù)目)Howtorealize32-Input,1-bitMultiplexer

(如何實(shí)現(xiàn)32輸入，1位多路復(fù)用器？)Inputsfrom8to32,Need4chips

(數(shù)據(jù)輸入由832，需4片)HowtocontrolSelectInputsByHighbitplusLowbit.

(如何控制選擇輸入端？

——分為：高位＋低位)ENYYABCD0D7ExpandingMultiplexers

(擴(kuò)展多路復(fù)用器)ExpandingInputs(擴(kuò)展數(shù)據(jù)輸入端的數(shù)目)如何實(shí)現(xiàn)32輸入，1位多路復(fù)用器？HighBitsplusDecoderasSelect

(高位＋譯碼器進(jìn)行片選)LowBitsConnecttoC,B,AofeachChip

(低位接到每片的C,B,A)OutputUsingORGate(4片輸出用或門得最終輸出)ENYYABCD0D7ExpandingMultiplexers

擴(kuò)展多路復(fù)用器Combining74x151stomakea32-to-1multiplexer.D0D1D2D3D4D5D6D7A0A1A2YDual4-to-1Multiplexerto8-to-1Multiplexer(用雙4選1數(shù)據(jù)選擇器構(gòu)成8選1數(shù)據(jù)選擇器)UseMultiplexertodesignlogiccircuit用數(shù)據(jù)選擇器設(shè)計(jì)組合邏輯電路Whenenasserted當(dāng)使能端有效時(shí)，ENABCD0D1D2D3D4D5D6D7YY74x151F=

(A,B,C)(0,1,3,7)CBAVCCF設(shè)計(jì)七段顯示譯碼器邏輯抽象，得到真值表輸入信號(hào)：BCD碼（A3A2A1A0）輸出：七段碼（的驅(qū)動(dòng)信號(hào)）a~g1表示亮，0表示滅選擇器件類型采用基本門電路實(shí)現(xiàn)，利用卡諾圖化簡(jiǎn)采用二進(jìn)制譯碼器實(shí)現(xiàn)，變換為標(biāo)準(zhǔn)和形式采用數(shù)據(jù)選擇器實(shí)現(xiàn),變換為標(biāo)準(zhǔn)和形式電路處理，得到電路圖abcdefg七段顯示譯碼器的真值表00000001001000110100010101100111100010011010101111001101111011111111110011000011011011111001011001110110110011111111000011111111110011000110100110010100011100101100011110000000A3

A2

A1

A0abcdefg0123456789101112131415A1A0A3A200

01

11

10000111101011110010000101a用數(shù)據(jù)選擇器74x151

實(shí)現(xiàn)邏輯函數(shù)F=

(X,Y,Z)(1,3,5,6)AClassProblem(每課一題)ENABCD0D1D2D3D4D5D6D7YY74x151YZWX00

01

11

10000111101111111YWX000111100110ZZZZZ’0Q:use74x151toimplementlogicfunction思考：利用74x151實(shí)現(xiàn)邏輯函數(shù)F=

(W,X,Y,Z)(0,1,3,7,9,13,14)reducingdimensions:4D-3D降維：由4維3維ENABCD0D1D2D3D4D5D6D7YY74x151VCCYXWFZUse利用74x151F=

(W,X,Y,Z)(0,1,3,7,9,13,14)0

2

6

41

3

7

5YWX000111100110ZZZZZ’0Note:nbitmultiplexercanimplementlogicfunctionofn+1bits說明：用具有n位地址輸入端的多路復(fù)用器，可以產(chǎn)生任何形式的輸入變量數(shù)不大于n+1的組合邏輯函數(shù)。Demultiplexer（多路分配器）Routethebusdatatooneofmdestinations

(把輸入數(shù)據(jù)送到m個(gè)目的地之一)Multiplexer多路復(fù)用器SRCASRCBSRCZDemultiplexer多路分配器BUSDSTADSTBDSTZSRCSELDSTSELDST:destinationSRC:sourceSEL:selectDemultiplexer（多路分配器）MultiplexerSRCASRCBSRCZDemultiplexerBUSDSTADSTBDSTZSRCSELDSTSELAbinarydecoderwithanenableinputcanbeusedasademultiplexer(利用帶使能端的二進(jìn)制譯碼器作為多路分配器)ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138DST0_LDST7_Lsource數(shù)據(jù)輸入SRCEN_LDSTSEL0DSTSEL1DSTSEL2Destinationselection地址選擇——

Enableinputisconnectedtothedataline

(利用使能端作為數(shù)據(jù)輸入端)5.8ParityCircuit(奇偶校驗(yàn)電路)Odd-ParityCircuit（奇校驗(yàn)電路）Outputis1ifanoddnumberofitsinputsare1.

(如果輸入有奇數(shù)個(gè)1，則輸出為1。)Even-ParityCircuit（偶校驗(yàn)電路）Outputis1ifanevennumberofitsinputsare1.(如果輸入有偶數(shù)個(gè)1，則輸出為1。)Howtoknowthenumberof1s???回顧：用什么可以判斷1的個(gè)數(shù)？？？5.8ParityCircuit(奇偶校驗(yàn)電路)A0

A1…An=

1oddnumberof1s變量為1的個(gè)數(shù)是奇數(shù)0evennumberof1s變量為1的個(gè)數(shù)是偶數(shù)Outputofodd-paritycircuitisinverted,weGetaneven-paritycircuit.(奇校驗(yàn)電路的輸出反相就得到偶校驗(yàn)電路)NXORgatesmaybecascadedtoformacircuitwithn+1inputsandasingleoutput.(n個(gè)異或門級(jí)聯(lián)，形成具有n+1個(gè)輸入和單一輸出的電路)ReviewofXORANDXNOR

(回顧異或、同或運(yùn)算)A

B=(A⊙B)’A

B’=A⊙BA

B=A⊙B’Anytwosignals(inputsoroutput)ofanXORorXNORgatemaybecomplementedwithoutchangingtheresultinglogicfunction.(Figure5-72)(對(duì)于異或門、同或門的任何2個(gè)信號(hào)（輸入或輸出）都可以取反，而不改變結(jié)果的邏輯功能（

圖5-72)F=A

BABFABFABABFFF=A’

B’F=(A’

B)’F=(A

B’)’I1I2I3I4INODDDaisy-ChainConnection

(菊花鏈?zhǔn)竭B接)I1I2I3I4IMINODDTreeStructure

(樹狀連接)CascadingXORGates(級(jí)聯(lián)異或門）9-bitOdd/EvenParityGenerator74x280(9位奇偶校驗(yàn)發(fā)生器74x280）The74x2809-bitodd/evenparitygenerator:(a)logicdiagram,includingpinnumbersforastandard16-pindualin-linepackage;(b)traditionallogicsymbol.Parity-CheckingApplications

(奇偶校驗(yàn)的應(yīng)用)Todetecterrorsinthetransmissionandstorageofdata用于檢測(cè)代碼在傳輸和存儲(chǔ)過程中是否出現(xiàn)差錯(cuò)AEVENODD74x280HIAEVENODD74x280HItransmitter發(fā)端receiver收端DB[0:7]DB[0:7]ERROREnsureevennumber1s發(fā)端保證有偶數(shù)個(gè)1Ifodd,errorasserted收端ODD有效表示出錯(cuò)odd奇數(shù)even偶數(shù)5.9Comparator（比較器）ComparetwoBinarywordsandindicatewhethertheyareequal(比較2個(gè)二進(jìn)制數(shù)值并指示其是否相等的電路)Comparator:CheckiftwoBinarywordsareequal

(等值比較器：檢驗(yàn)數(shù)值是否相等)MagnitudeComparator:Comparetheirmagnitude(Greaterthan,Equal,Lessthan)(數(shù)值比較器：比較數(shù)值的大?。?gt;,=,<）)5.9Comparator（比較器）Howtobuilda1-bitComparator?

(如何構(gòu)造1位等值比較器？？)

——

UseXOR(XNOR)

(利用異或門（同或門）)ABDIFFABEQDIFF:differentEQ:equalHowtoBuildaN-bitComparator?

(如何構(gòu)造多位等值比較器？？)DIFFA0B0A1B1A2B2A3B3Allindividualbitsarepairwiseequal必須每位都相等——parallelcomparator并行比較——serialcomparator串行比較4bitcomparator4位等值比較器AnIterativeComparator

(迭代比較電路)XYCMPEQIEQOX0Y0X1Y1XN-1YN-1EQ1EQ2EQNEQN-11XYCMPEQIEQOXYCMPEQIEQOserialcomparator——每位串行比較ABEQEQOEQISavelittlecost,butveryslow迭代的方法可能節(jié)省費(fèi)用，但速度慢Cascadinginput用于級(jí)聯(lián)的輸入1-BitMagnitudeComparator

(一位數(shù)值比較器)①A>B（A=1,B=0）then

A·B’=1②A<B（A=0,B=1）then

A’·B=1③A=B，thenA⊙B=1EQ_LABLT_LGT_LActivelow輸出低電平有效EQ_L=A·B’+A’·B=A

B=(A⊙B)’LT:LessThanEQ:EqualGT:GreaterThan(A’·B)’(A·B’)’n-BitMagnitudeComparator

(多位數(shù)值比較器)A(A3A2A1A0)

comparewith

B(B3B2B1B0)fromuptodownA與B自高而低逐位比較EQ=(A3⊙B3)·(A2⊙B2)·(A1⊙B1)·(A0⊙B0)GT=(A3>B3)LT=EQ’·GT’=(EQ+GT)’或(A3=

B3)·(A2=

B2)·

(A1>B1)或(A3=

B3)·(A2=

B2)·(A1=

B1)·

(A0>B0)或(A3=

B3)·

(A2>B2)A3·

B3’A2·

B2’A1·

B1’A0·

B0’⊙⊙⊙⊙⊙⊙+++4-BitComparator74x85

(4位比較器74x85)74x85A0A1A2A3ALTBINAEQBINAGTBINCascadinginputforexpanding級(jí)聯(lián)輸入，用于擴(kuò)展ALTBOUT=(A<B)+(A=B)·ALTBINOutputsofLSBconnecttoinputsofMSB通常低位的輸出接高位的輸入BothhigherandlowerorderbitsareequalA=B：低位和高位都相等AH高位>BH高位AH高位=BH高位&AL低位>BL低位A>BAEQBOUT=(A=B)·AEQBINAGTBOUT=(A>B)+(A=B)·AGTBINSerialExpandingComparators

(比較器的串行擴(kuò)展)XD[11:0]YD[11:0][3:0][7:4][11:8]X<YX=YX>Y+5VA<BIA=BIA>BIA<BOA=BOA>BOA0~A3B0~B374x85A<BIA=BIA>BIA<BOA=BOA>BOA0~A3B0~B374x85A<BIA=BIA>BIA<BOA=BOA>BOA0~A3B0~B374x85A12-bitcomparatorusing74x85s3片74x85構(gòu)成12位比較器Lowerorder低位Higherorder高位8bitcomparator74x682

8位比較器P0P1P2P3P4P5P6P7Q1:logicdiagram?Q2：howtorepresentoutputsbelow？PNEQPEQQPGEQPLTQGELTQ3：Canexpand?能否擴(kuò)展？Note:nocascadinginputs注意：沒有級(jí)聯(lián)輸入端8bitcomparator74x682Logicdiagramforthe74x6828-bitcomparator,includingpinnumbersforastandard20-pindualin-linepackage.8bitcomparator74x682Q2：howtorepresentoutputsbelow？PNEQPEQQPGEQPLTQParalelExpandingComparators

(比較器的并行擴(kuò)展)24bitcomparatorusing374x6823片74x682構(gòu)成24位比較器P0~P7P=QQ0~Q7P>QP0~P7P=QQ0~Q7P>QP0~P7P=QQ0~Q7P>Q[7:0][15:8][23:16]P[23:0]Q[23:0]PEQQPGTQ用數(shù)據(jù)選擇器74x151

實(shí)現(xiàn)邏輯函數(shù)F=

(X,Y,Z)(1,3,5,6)AClassProblem(每課一題)ENABCD0D1D2D3D4D5D6D7YY74x1515.10Adder(加法器)HalfAdderand

FullAdder（半加器和全加器）0000010110011110ABSCO(半加器真值表)Sum(相加的和):

S=A’·B+A·B’=A

BCarry(向高位的進(jìn)位)：CO=A·B0000000101010010111010001101101101011111CIXYSCO(全加器真值表)TruthTableofHalfAdderTruthTableofFullAdder5.10Adder(加法器)SCOXYCIS=X

YCIX·Y00100111CIXY0001111001COX·CICO=

+

+Y·CI=X·Y+(X+Y)·CI0000000101010010111010001101101101011111CIXYSCO全加器真值表HalfAdderand

FullAdder（半加器和全加器）TruthTableofFullAdderRippleAdder(串行進(jìn)位加法器)(缺點(diǎn)：運(yùn)算速度慢，有較大的傳輸延遲)tADD=tXYCout+(n-2)*tCinCout+tCinSXYCICOSXYCICOSXYCICOSXYCICOSC1C2C3C4C0S0S1S2S3X0Y0X1Y1X2Y2X3Y3=0——ImproveSpeed:ParallelAdder

(提高速度：并行加法器)Disadvantage:Slow,MorePropagationDelayXYCICOSXYCICOSXYCICOSXYCICOSC1C2C3C4C0S0S1S2S3X0Y0X1Y1X2Y2X3Y3XYCMPEQIEQOX0Y0X1Y1XN-1YN-1EQ1EQ2EQNEQN-11XYCMPEQIEQOXYCMPEQIEQOAnIterativeComparator(串行比較器)RippleAdder(串行加法器)PrimaryInputs(主輸入)PrimaryOutputs(主輸出)BoundaryInputs(邊界輸入)BoundaryOutputs(邊界輸出)Cascadingoutput級(jí)聯(lián)輸出AnIterativeCircuit（迭代電路）Iterative：重復(fù)的,反復(fù)的,[數(shù)]迭代的PICICOPOPICICOPOPICICOPOC0C1C2CnPO0PO1POn-1PI0PI1PIn-1Figure5-79Cascadingoutput級(jí)聯(lián)輸出BoundaryInputs(邊界輸入)BoundaryOutputs(邊界輸出)PrimaryInputs(主輸入)Primar