硬件描述語言與數(shù)字系統(tǒng)開發(fā)(第8章)-10

硬件描述語言與數(shù)字系統(tǒng)開發(fā)第8章VHDL應用舉例帶權表決器設計奇數(shù)分頻器設計數(shù)控分頻器設計計數(shù)/譯碼驅動/掃描顯示電路串-并轉換與并-串轉換數(shù)字序列的產(chǎn)生與檢測正弦信號發(fā)生器數(shù)字基帶編碼設計libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;entityx3is port(en:in

std_logic;

d:instd_logic_vector(9downto0);

q:out

std_logic);endx3;architeturebehaveofx3isbeginprocess(en,d)variablen:integerrange0to20;beginifen'eventanden='1'thenn:=0;ifd(9)='1'thenn:=2;foriin8downto0loopifd(i)='1'thenn:=n+1;endif;endloop;elsen:=0;endif;ifn>5thenq<='1';elseq<='0';endif;endif;endprocess;endbehave;帶權表決器的VHDL設計奇數(shù)分頻器的VHDL設計LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;ENTITYfp_11ISPORT(clkin:IN

std_logic;

clkout:OUT

std_logic);ENDfp_11;ARCHITECTUREbehaveOFfp_11ISsignalq1,q2:integerrange0to20;signalqq1,qq2:std_logic;beginprocess(clkin)beginif(clkin'eventandclkin='1')thenif(q1=10)thenq1<=0;

elsif(q1<=5)thenqq1<='0';q1<=q1+1;elseqq1<='1';q1<=q1+1; endif;endif;endprocess;process(clkin)beginif(clkin'eventandclkin='0')thenif(q2=10)thenq2<=0;

elsif(q2<=5)thenqq2<='0';q2<=q1+1;elseqq2<='1';q2<=q1+1; endif;endif;endprocess;clkout<=qq1norqq2;ENDbehave;奇數(shù)分頻器仿真波形分頻系數(shù)=11數(shù)控分頻器的VHDL設計LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYFPQISPORT(CLKIN:INSTD_LOGIC;D:INSTD_LOGIC_VECTOR(7DOWNTO0);CLKOUT:OUTSTD_LOGIC);ENDFPQ;ARCHITECTUREoneOFFPQISSIGNALFULL:STD_LOGIC;BEGINP1:PROCESS(CLKIN)VARIABLECNT8:STD_LOGIC_VECTOR(7DOWNTO0);BEGINIFCLKIN'EVENTANDCLKIN='1'THENIFCNT8="11111111"THEN

CNT8:=D;--當CNT8計數(shù)計滿時，輸入數(shù)據(jù)D被同步預置給計數(shù)器CNT8

FULL<='1';--同時使溢出標志信號FULL輸出為高電平

ELSECNT8:=CNT8+1;--否則繼續(xù)作加1計數(shù)

FULL<='0';--且輸出溢出標志信號FULL為低電平

ENDIF;ENDIF;ENDPROCESSP1;P2:PROCESS(FULL)VARIABLECNT2:STD_LOGIC;BEGINIFFULL'EVENTANDFULL='1'THENCNT2:=NOTCNT2;--如果溢出標志信號FULL為高電平，D觸發(fā)器輸出取反

CLKOUT<=CNT2;ENDIF;ENDPROCESSP2;ENDone;數(shù)控分頻器仿真波形分頻系數(shù)=(256-D)*2計數(shù)/譯碼驅動/掃描顯示電路設計上圖所示是8位共陽數(shù)碼管掃描顯示電路，其中每個數(shù)碼管的8個段：h、g、f、e、d、c、b、a(h是小數(shù)點)連在一起,低電平有效;8個數(shù)碼管分別由8個選通信號k1、k2、…k8來選擇,高電平有效;被選通的數(shù)碼管顯示數(shù)據(jù)。例如，某一時刻，k3為高電平，其余選通信號為低電平，這時僅k3對應的數(shù)碼管顯示來自段信號端的數(shù)據(jù)，而其它7個數(shù)碼管呈現(xiàn)關閉狀態(tài)。若希望在8個數(shù)碼管顯示相應的數(shù)據(jù)，就必須使得8個選通信號k1、k2、…k8分別被單獨選通，與此同時，在段信號輸入端加上欲對應顯示的數(shù)據(jù)。隨著選通信號的掃變(掃描頻率>8*25Hz)，實現(xiàn)掃描顯示的目的。

LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYSCAN_LEDISPORT(CLK:INSTD_LOGIC;--掃描時鐘信號輸入

A1，A2，A3，A4，A5，A6，A7，A8:ININTEGERRANGE0TO15;SG:OUTSTD_LOGIC_VECTOR(6DOWNTO0);--段控制信號輸出(g-a)BT:OUTSTD_LOGIC_VECTOR(8DOWNTO1)）;--位控制信號輸出(k8-k1)ENDSCAN_LED;ARCHITECTUREoneOFSCAN_LEDISSIGNALCNT8:STD_LOGIC_VECTOR(2DOWNTO0);SIGNALA:INTEGERRANGE0TO15;BEGINP1：PROCESS(CNT8)BEGIN

掃描譯碼顯示電路的VHDL設計

CASECNT8ISWHEN"000"=>BT<="00000001";A<=A1;WHEN"001"=>BT<="00000010";A<=A2;WHEN"010"=>BT<="00000100";A<=A3;WHEN"011"=>BT<="00001000";A<=A4;WHEN"100"=>BT<="00010000";A<=A5;WHEN"101"=>BT<="00100000";A<=A6;WHEN"110"=>BT<="01000000";A<=A7;WHEN"111"=>BT<="10000000";A<=A8;WHENOTHERS=>NULL;ENDCASE;ENDPROCESSP1;P2：PROCESS(CLK)BEGINIFCLK'EVENTANDCLK='1'THENCNT8<=CNT8+1;ENDIF;ENDPROCESSP2;

P3：PROCESS(A)–-共陽數(shù)碼管譯碼電路

BEGINCASEAISWHEN0=>SG<=“1000000";WHEN1=>SG<=“1111001";WHEN2=>SG<=“0100100";WHEN3=>SG<=“0110000";WHEN4=>SG<=“0011001";WHEN5=>SG<=“0010010";WHEN6=>SG<=“0000010";WHEN7=>SG<=“1111000";WHEN8=>SG<=“0000000";WHEN9=>SG<=“0010000";WHEN10=>SG<=“0001000";WHEN11=>SG<=“0000011";WHEN12=>SG<=“1000110";WHEN13=>SG<=“0100001";WHEN14=>SG<=“0000110";WHEN15=>SG<=“0001110";WHENOTHERS=>NULL;ENDCASE;ENDPROCESSP3;ENDone;

共陰數(shù)碼管及其電路

CASEAISWHEN0=>SG<="0111111";WHEN1=>SG<="0000110";WHEN2=>SG<="1011011";WHEN3=>SG<="1001111";WHEN4=>SG<="1100110";WHEN5=>SG<="1101101";WHEN6=>SG<="1111101";WHEN7=>SG<="0000111";WHEN8=>SG<="1111111";WHEN9=>SG<="1101111";WHEN10=>SG<="1110111";WHEN11=>SG<="1111100";WHEN12=>SG<="0111001";WHEN13=>SG<="1011110";WHEN14=>SG<="1111001";WHEN15=>SG<="1110001";WHENOTHERS=>NULL;ENDCASE;Libraryieee;Useieee.std_logic_1164.all;Entityc_bisPort(clr,din,clk:instd_logic;y:outstd_logic_vector(4downto0));Endc_b;Architecturebehavofc_bissignaltem:std_logic_vector(5downto0);beginp1:process(clk)beginif(clk'eventandclk='1')then ifclr='0'then tem<="000000";

elsiftem(0)='0'then tem<=din&"01111";

elsetem<=din&tem(5downto1);endif;endif;endprocessp1;p2:process(tem)beginiftem(0)='0'theny<=tem(5downto1);elsey<="00000";endif;endprocessp2;endbehav;5位串-并轉換的VHDL設計5位串-并轉換仿真波形注意：串-并轉換需延時輸出4位并-串轉換的VHDL設計libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityb_cisport(clr,clk:instd_logic;din:instd_logic_vector(3downto0);y:outstd_logic);endb_c;architechture

behavofb_cissignaltem:std_logic_vector(3downto0);signalnn:std_logic_vector(1downto0);beginp1:process(clk)beginif(clk'eventandclk='1')then

nn<=nn+1;endif;endprocessp1;

p2:process(nn,clr,clk)beginifclr=‘1'thentem<="0000";

elsif(clk'eventandclk='1')then

ifnn="00"then tem<=din; else y<=tem(3);tem(3downto1)<=tem(2downto0);endif;endif;endprocessp2;endbehav;4位并-串轉換仿真波形分析波形，找出問題，修改完善！數(shù)字序列信號發(fā)生器的VHDL設計libraryieee;useieee.std_logic_1164.all;entityxxisport(cp,res:in

std_logic;

y:out

std_logic);endxx;architecturertlofxxissignalreg:std_logic_vector(8downto0);signaln:integerrange0to10;beginprocess(cp,res)beginifres='1'theny<='0';reg<="111010100";elsif

cp'eventandcp='1'thenifn>=8thenreg<="111010100";n<=0;elsen<=n+1;y<=reg(8);reg<=reg(7downto0)&'0';endif;endif;endprocess;endrtl;數(shù)字序列信號產(chǎn)生波形當reg、n定義為變量時，有何不同？請修改完善！數(shù)字序列檢測器的VHDL設計libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitycxjcisport(cp,cx:in

std_logic;

y:out

std_logic);endcxjc;architecturertlofcxjcistypestateis(s0,s1,s2,s3);signaln:state;beginprocess(cp,cx)beginifcp'eventandcp='1'thencaseniswhens0=>ifcx='1'thenn<=s1;y<='0';elsen<=s0;y<='0';endif;whens1=>ifcx='1'thenn<=s2;y<='0';elsen<=s0;y<='0';endif;whens2=>ifcx='0'thenn<=s3;y<='0';elsen<=s0;y<='0';endif;whens3=>ifcx='1'thenn<=s0;y<='1';elsen<=s0;y<='0';endif;whenothers=>null;endcase;endif;endprocess;endrtl;數(shù)字序列檢測仿真波形數(shù)字序列檢測StateMachinaViewer分析波形，找出問題，修改完善！8位并行數(shù)據(jù)“0”個數(shù)檢測器的VHDL設計libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityzerojcisport(clk,clr:in

std_logic;

d:instd_logic_vector(7downto0);

q:outstd_logic_vector(2downto0));endzerojc;architecturertlofzerojcisbeginprocess(clk,clr)variablesd:std_logic_vector(2downto0);beginifclr='0'thenq<="000";elsif

clk'eventandclk='1'thenifd(0)='1'thensd:=sd+1;endif;ifd(1)='1'thensd:=sd+1;endif;ifd(2)='1'thensd:=sd+1;endif;ifd(3)='1'thensd:=sd+1;endif;ifd(4)='1'thensd:=sd+1;endif;ifd(5)='1'thensd:=sd+1;endif;ifd(6)='1'thensd:=sd+1;endif;ifd(7)='1'thensd:=sd+1;endif;q<=8-sd;endif;sd:="000";endprocess;endrtl;8位并行數(shù)據(jù)“0”個數(shù)檢測仿真波形正弦波形產(chǎn)生電路設計---宏功能模塊應用舉例正弦信號輸出頻率f=f0/N正弦波形產(chǎn)生電路設計要點：自頂向下子電路生成宏模塊調(diào)用混合輸入正弦波形產(chǎn)生電路設計步驟：建立頂層設計項目編程創(chuàng)建子電路定制調(diào)用宏模塊原理框圖混合輸入libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;ENTITYaddr_cnt64ISPORT(clr,en,clk:in

std_logic;addr_cnt64:outstd_logic_vector(5downto0));ENDaddr_cnt64;ARCHITECTUREBHAVOFaddr_cnt64ISBEGINprocess(clr,en,clk)variableq64_v:std_logic_vector(5downto0);begin

ifclr='0'thenq64_v:="000000";

elsif

clk'eventandclk='1'thenifen='1'then q64_v:=q64_v+1;elseq64_v:="000000";endif;endif;

addr_cnt64<=q64_v;endprocess;endbhav;定制LPM_ROM建立.mif格式文件定制LPM_ROM元件LPM宏功能塊設定

7.2.2定制初始化數(shù)據(jù)文件

7.2.3定制LPM_ROM元件選擇data_rom模塊數(shù)據(jù)線和地址線寬度

選擇使能、清零信號端子調(diào)入ROM初始化數(shù)據(jù)文件并選擇在系統(tǒng)讀寫功能完成頂層設計仿真波形輸出嵌入式邏輯分析儀獲得的波形數(shù)字基帶信號的常用碼型單極性(NRZ)碼；(b)雙極性(NRZ)碼；(c)單極性(RZ)碼；(d)雙極性(RZ)碼；(e)差分碼；(f)交替極性碼(AMI)；(g)三階高密度雙極性碼(HDB3)；(h)分相碼；(i)信號反轉碼(CMI)數(shù)字序列AMI編碼設計

AMI碼是傳號交替反轉碼，在AMI碼中，二進制碼0用0電平表示，二進制碼1交替地用+1和-1表示。其編碼規(guī)則是將二進制消息代碼“1”(傳號)交替地變換為傳輸碼的“+1”和“-1”，而“0”(空號)保持不變。例如：數(shù)字序列100110000000110011…AMI碼：+100–1+10000000-1+100-1+1…

AMI編碼程序仿真波形AMI編碼VHDL程序libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityamiisport(clk:inbit;input:inbit;output1:outbit;output2:outbit);endami;architectureaofamiisbeginprocess(clk)variablec:bit:='0';beginifclk'eventandclk='1‘thenifinput='1‘thenifc='0‘thenoutput1<='1';output2<='0';c:=notc;elseoutput1<='0';output2<='1';c:=notc;endif;elseoutput1<='0';output2<='0';endif;endif;endprocess;enda;AMI譯碼程序及仿真波形libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityamiymisport(clk:inbit;input1,input2:inbit;output:outbit);endamiym;architectureaofamiymisbeginprocess(clk)beginifclk'eventandclk='0'thenoutput<=input1orinput2;endif;endprocess;enda;

第8章習題

應用VHDL描述語句設計:(1)分頻系數(shù)為19,47,111的奇數(shù)分頻器

(2)分頻系數(shù)為80,88,100,112的數(shù)控分頻器

(3)掃描驅動共陰數(shù)碼管，顯示字符“HELLO”(4)“01”序列的產(chǎn)生與檢測電路

(5)16位串行數(shù)據(jù)幀“1”個數(shù)檢測

研究生大作業(yè)選題(1)參考P157(數(shù)控分頻器),設計一個SPWM波形發(fā)生器(設開關頻率=10KHz)。(2)參考P162(正弦信號發(fā)生器),設計一個三相正弦信號發(fā)生器(設信號頻率=50Hz)。(3)參考P162(正弦信號發(fā)生器),利用雙口RAM設計一個任意波形回放器(設信號頻率=1KHz)(4)參考P191(頻率計電路),設計一個8位數(shù)碼管顯示頻率計(信號頻率<1M,頻率分辨率1Hz)。(5)參考P191(頻率計電路),設計一個4位數(shù)碼管顯示相位檢測器(信號頻率<1M,相位分辨率1°)(6)參考P219(序列檢測電路),設計一任意序列檢測器(預置序列/右移串入/并出,9600b/s)(7)參考P219(ADC0809控制器),設計一個基于ADC0809的數(shù)據(jù)采集/存儲模塊(信號頻率10kHz,256)。(8)參考P360(DDS信號發(fā)生器),設計一個多功能相/頻可調(diào)信號源(信號頻率=100Hz-10KHz；信號相位=0-180°)

。(9)參考P360(DDS信號發(fā)生器),設計一個載波移相調(diào)制CPS-PWM信號發(fā)生模塊(10kHz,5)(10)參考P390(13.3),設計一個步進電機細分驅動控制器(32細分)。(11)參考P396(13.4),設計一個直流電機PWM控制器(10kHz,占空比0.1-0.9可調(diào))。(12)參考課件內(nèi)容,設計一個數(shù)字基帶信號編碼/解碼模塊(碼元速率9600b/s)。(13)參考課件內(nèi)容,設計一個數(shù)字調(diào)制信號調(diào)制/解調(diào)模塊(碼元速率9600b/s)。(14)參考相關內(nèi)容,設計一個通用PWMIP核模塊(帶死區(qū)控制三相6路互補輸出,頻率10Kz-100KHz

/占空比可0.1-0.9,用戶設置)。實驗內(nèi)容：熟悉Quartus2的圖形編輯器:庫元件/設計單元的調(diào)用與連接。了解Quartus2的LPM編輯器:宏功能模塊LPM的參數(shù)設置與調(diào)用。掌握Quartus2混合輸入方式:底層模塊(HDL)+頂層綜合(BLOCK)?；旌陷斎霊门e例:256點正弦信號發(fā)生器設計與調(diào)試。應用VHDL設計一24進制計數(shù)器,并用2位共陰數(shù)碼管掃描顯示。閱讀附1程序段，分析實體功能并觀測其仿真波形。閱讀附2程序段，分析實體功能并觀測其仿真波形。實驗二VHDL應用程序設計與分析(附1)VHDL程序:libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityexam1isport(clkin:instd_logic;

kf:instd_logic_vector(1downto0);

clkout:outstd_logic);endexam1;architectureoneofexam1isconstantd0:integer:=0;constantd1:integer:=100;signalkk:integerrange0to10;beginp0:process(kf)begincasekfiswhen"00"=>kk<=0;when"01"=>kk<=1;when"10"=>kk<=2;whenothers=>kk<=3;endcase;endprocessp0;p1:process(clkin,kk)variablecnt256:integerrange0to256;variableclkout0,clkout1,clkout2,clkout3:std_logic;variable

q:std_logic_vector(3downto0);beginifclkin‘eventandclkin='1'thencasekkiswhen0=>ifcnt256=256thencnt256:=d0;clkout0:=notclkout0;elsecnt256:=cnt256+1;endif;

clkout<=clkout0;when1=>ifcnt256=256thencnt256:=d1;cl