Vivado從此開始（第2版）課件 31-UltraFast-Design(9)-Timing-Closure-Part1 - 35-TCL-Vivado-One-World-1

Lauren

GaoTiming

ClosurePart1VivadoBaselineTiming

ConstraintTimingClosure

TipsAgendaPage

3AddressingVivadoTiming

ChallengesWithISE,manycustomersreliedonSmartXplorertoclose

timing:EasyandeffectiveinmanycasesDownside->losetimingclosure

skillsCostTablehasthenatureof

randomnessWhentoreadtimingreport:After

MapWithVivado“new”techniqueshavetobe

usedFundamentaltimingclosuretechniqueshavenot

changedCustomersjustneedarefresher:baseliningthe

designWhentoreadtimingreport:After

SynthesisVivadoisextremelypowerfulfordesignanalysistodetermine

therootcauseofthetiming

issuesProgressiveApproachtoDesign

ClosureSynthesis?

AnalysisBaseline

ConstraintsRoute Place?

Analysis ?

AnalysisOptimizeInternal

PathsFmaxBaseline

XDCSynthesis?

AnalysisAddI/O

ConstraintsRoute Place?

Analysis ?

AnalysisOptimizeEntire

ChipFmaxComplete

XDCSynthesisAnalysisRouteAnalysis ?

AnalysisIf

neededAddTimingExceptionsand/or

FloorplanPlaceFine-tuneFmaxFinal

XDCFullySynthesized

NetlistBaseline

Stage

1: Constraint

DevelopmentBaseline

Stage

2: Implementation

withreport_timing_summaryPage

5BaseliningCustomerDesignsWith

VivadoRunreport_timing_summaryaftereachstep(not

optional)EnsureWNS>300

psPage

6BaselineStage

2Q.HowdoI

start?A.OpensynthesizeddesigninVivado

IDEQ.HowdoImakesureI’mstartingfrom

scratch?A.tcl_console>

reset_timingQ.HowdoIknowwhatto

constrain?A.

report_clock_networksDevelopingConstraintsFrom

ScratchQ.HowdoIknowwhenI’mdoneconstraining

clocks?A.Whenreport_clock_networks

showsnounconstrainednetworksQ.HowdoImakesuremyclocksare

correct?A. report_clocks

showsperiodandwaveformofeveryclockinthedesignQ.HowdoIknowwhatclocksshouldbe

related?A.report_clock_interaction–sortbyCommonPrimary

ClockDevelopingConstraintsFrom

ScratchDEMOLauren

GaoTiming

ClosurePart2VivadoBaselineTiming

ConstraintTimingClosure

TipsAgendaCodingstyleisnotindependent,oppositely,it'shighlyrelatedto

devicearchitetureAvoidasynchronousresetAddpipelineregisterinthehierarchyboundaryPipelineisveryhelpfultoimproveclock

frequency–RAMand

DSPReadandanalyzetimingreportafter

synthesisTip1:GoodHDLCoding

StyleSequentialLogic:

RegistersILOGICCLBFFdrivenfrom

LUTCLBFFdrivenfromX

inputLUTRAM(as

SRL)CLBFFdrivenfromMUXFXor

CARRYOLOGICCLBFFinQ

BELCLBFFinMUX

BELILOGICOLOGICLUTRAM(as

SRL)DSPBRAMFASTERClocktoOut

DelaysSetup

RequirementUg949>Ch5>TimingClosure>ReviewingTechnology

ChoicesAregistercanbemappedtooneofseveraltypesofresources

inthe

deviceCLBregister,CLBLUTRAMasan

SRLILOGIC,

OLOGICDSPandblock

RAMsIftheregisterisadjacenttoarithmeticormemory

functionalityBlockRAMorDistributed

RAM128x4Ug949>Ch5>TimingClosure>ReviewingTechnology

ChoicesBlock

RAMDedicatedhardwareresources,higher

capacitySmallerpowerconsumptioncomparedtodistributedRAMofsimilar

capacityHigherdelaygettingtoandfromtheblockRAMcolumnsDistributed

RAMImplementedusingCLB

logicMoresuitedtosmaller

capacity

Virtex-7SpeedGrade:

-28kx32FullyPipelinedDSP48E1Ug949>Ch5>TimingClosure>ReviewingTechnology

ChoicesDSP48E1Itismoresuitedtowide,high-speed

multiplicationMultiplier,MAC,Adder,Subtraction,Counters,Wideparallellogic

gatesCLBcarry

logicItisusuallymoreappropriateforKCMandsmall-width

multipliersCLB-logicbasedfunctionscanbemovedtoDSP48E1

whenCLBsareover

utilizedThelatterisusefulforaddressingareasof

congestionOver

constrainedUsemorememoryand

runtimeTooverconstrain,uncertaintygetsaddeddirectlytoslack

equationset_clock_uncertainty–setup0.3[get_clocks

my_CLK]Afterphys_optorafter

route:set_clock_uncertainty

–setup

0 [get_clocks

my_CLK]Under

constrained–Yourdesignmayclosetimingbutexhibithardwarefailuresduetomissing

pathsAlltheclocksare

contrained–

check_timing–AnalyzeCDCpath:

report_clock_interactionTip2:MakeYourConstraintsPreciseand

ProperIt'sbettertoanalyzetimingwithoutIO

constraintsAddressinternaltimingissues

firstlyVivadowillnotanalyzeIOtimingifIOconstraintsarenot

avaliableIfinternaltimingisclosure,IOconstraintscanbe

setUsesource/systemsynchronoustimingconstraints

templateTimingexception:Lessis

moreset_multicycle_path–from[get_cellsregB]–to[get_cellsregC]N

–setupset_multicycle_path–from[get_cellsregB]–to[get_cellsregC]N-1

–holdTip2:MakeYourConstraintsPreciseand

ProperRecommendedtodrivehighfanoutnetsfromasynchronousstart

pointIdentifyhighfanoutnetsdrivenby

LUTs–report_high_fanout_nets–load_types–max_nets

100Tip3:ManageHighFanout

NetsVerifybottommodulebyOOC,whichcanaccerlatedesign

iterationDesignbasedonIPisbuttom-upEachIPhasitsownDCPwhichcanberesuedineach

iterationVerisoncontrol:Git,Subversion,RCSHierarchydesign

methodologyTip4:BottomtoUpDesign

FlowInSDC,ALLclocksareconsideredrelatedby

defaultCheckclockinteraction

reportreport_clock_interatcionCreateasynchronousclock

groupset_clock_groupsCheckclocknetwork

reportreport_clock_networksCheckCDCreport(2014.3or

later)report_cdcTip5:ClockDomainCrossDesignand

ConstraintSynchronousclockdomaincross

pathBothsourceanddestinationclocksarefromthesame

MMCM/PLLThephasebetweensourceclockanddestinationclockis

specificConstraint:

set_multicycle_pathAsynchronousclockdomaincross

pathSourceclockanddestinationclockarefromdifferent

MMCM/PLLThephasebetweenthemisnot

specificDesign:dual-register;FIFO;

Hand-shakingAdd“ASYNC_REG”attributeto

synchronizerConstraint:set_clock_groups;set_max_delay–datapath_only;set_false_pathTip5:ClockDomainCrossDesignand

ConstraintBeforePCBdesign,run

DRCIO

planningClockplanningLOCfor

MacroBlockRAMand

DSPBeforefloorplan,improvingHDLandconstraintsaredone

firstlyFloorplan:lessis

moreOnlyforcritical

partDon'tcreatthepblockswithhighresource

utilizationAvoidoverlap

pblocksTip6:Physical

ConstraintsThesameprojectcanincludemultipledesignrunswith

differentstrategiesImplementationstrategycancoverdifferentrequirements:performance,power,area,

flowYoucancreateyourown

strategyYoucanaddHookScriptineachdesign

stepMultipleiterationsof

phys_opt_designTip7:ChoosetheProper

StrategyReducecontrol

sets–Checkcontrolsetsreport:

report_control_setsCombinetheclockswiththesame

frequencyIntegrateclockenable

signalsFollowtheprincipleof

resetNoresetis

bestSynchronousresetisbetterifresetis

neededAvoidasynchronousresetBRAMandDSPdon'tsupportasynchronous

resetTip8:ShareControlSet

SignalsAddresscriticalwarningsand

errorsCheckDRCviolations:Aftersynthesisand

ImplementationRunmethodology_checksand

timing_checksUnderstandtimingreportand

violationsBothdatapathandclockpathshouldbe

analyzedCheckdesignanalysis

reportProvidesdataoncriticalpathcharacteristicsandcomplexityofthedesigntohelpidentifyandanalyzeproblemareasthataresubjecttotimingclosureissuesandrouting

congestion–report_design_analysis(2014.3or

later)Tip9:UnderstandLogAndReport

FilesCustomizeyourown

reportsEdit

netlistInsertHookScriptineachdesign

stageTip10:BringTclintoFull

PlayTip1:GoodHDLCoding

StyleTip2:MakeYourConstraintsPreciseandProperTip3:ManageHighFanout

NetsTip4:BottomtoUpDesign

FlowTip5:ClockDomainCrossDesignandConstraintTip6:Physical

ConstraintsTip7:ChoosetheProper

StrategyTip8:ShareControlSet

SignalsTip9:UnderstandLogAndReport

FilesTip10:BringTclintoFull

PlaySummaryLauren

GaoPowerEstimationand

OptimizationEstimationpoweratvariousstagesof

designPost-synthesisto

post-routeHigheraccuracyreportsafter

post-routeTwomodesofpower

estimationVectorbased

(SAIF/VCD)simulationactivityfilefromrealworld

operationRecommendedandfast

estimationVectorlessSimplerinputbutrelativelyless

accurateToolcalculatesprobabilityofswitchrateand

%highPowerEstimationFlowin

VivadoReportPoweratAny

Stagesynth_designpower_opt_designplace_designroute_designreport_powerUnderstandingToggle

RatesToggleRatereflectshowoftenanoutputchangesrelativetoa

givenclock–Itcanbemodeledasapercentagebetween

0-200%Togglerate:100%

,clockfrequency:100MHz,datafrequency:50MHzDataFrequency=ToggleRate*Clock

Frequency/2Realistictogglerates,alongwithloadingaSAIForVCDfileshouldbeusedtoachieveoptimalpower

resultsMore

info:/itp/xilinx10/isehelp/xpa_c_togglerates.htmSwitchingActivityInterchange

FormatItisanoptionaloutputfilefrom

simulationDuringsimulationyoucanspecifyonwhichnodestorecordswitchingactivityTheSAIFfilewascreatedtoprovidemostoftheinformationcontainedinaVCDfilebutinamuchsmallersize

fileLoadinganSAIFfileintoReportPowerwillprovideamore

accuratepower

estimationSAIF

FileWith/Without

SAIFProvideaccuratedeviceandenvironment

informationSupplySAIFinputtotoolif

availableRealactivityofthechipandnotcornercase

testsAtaminimum,captureRTLIO

activityEnsureallclocksareproperlyconstrainedinthe

designUnconstrainedclockwillbeassumedtohavea0MHz

frequencyOverconstrainingclockswillresultinhigherdynamicpower

estimateSpecify%highandactivityoflargefanoutcontrolnetsGlobalset,resetsandclock

enablesBest

PracticesEnablingthePowerOptDesignoptionpriortoplace_designresultsin

acompletepoweroptimizationtobe

performed.ThisoptionyieldsthebestpossiblepowersavingfromtheVivadotoolsreport_power_optset_power_optPower

Optimizationset_power_opt-cell_typesbramset_power_opt-exclude_cells

cpuEngineset_power_opt-include_cells

cpuEngine/cpu_dbg_dat_ipower_opt_designDEMOLauren

GaoDesignWithVivadoIP

IntegratorCompleteIP&SystemCentricDesign

FlowVivadoIP

CatalogVivadoIPIntegratorVivado

RTLIntegrationSystemGeneratorVivadoHLSIP

IntegratorXilinx

IP3rdParty

IPUser

IPUsesmultipleplug-and-playformsofIP

toimplementfunctional

subsystemsIncludessoftwaredriversand

APIAcceleratesintegrationand

productivityPage

3EnablingReuseandDeliveringFullyFunctionalIP

SubsystemsIP

PackagerSource(C,RTL,

IP)Simulation

modelsDocumentationExampleDesignsTest

benchStandardized

IP-XACTIP

SubsystemEmbeddedProcessorHardware

DesignVivado

IPIntegratorISEVivadoXilinxPlatform

StudioSDKMicroBlazeZynqVivadoIPIntegrator:IntelligentIP

IntegrationAutomatedIP

SubsystemsBlockautomationforrapiddesign

creationOneclickIP

customizationCorrect-by-constructionExtensibleIP

repositoryReal-timeDRCsand

parameterpropagation/resolutionDesigner

AssistanceInterfaceConnectionswithLive

DRCsm

HierarchySysteViewTCL

ConsoleHierarchy

SupportExtensible

IPCatalogPage

5AdvancedGUIwithfullTCL

supportPage

6Usermarkssignalsorinterfacesto

debugThisautomaticallysetsupwaveformsinHDLsimulatorto

viewAlsospecifiessignalstodebugin

hardwarePage

7Debug

supportVivadoIPIntegrator

FeatureRunBlock

AutomationRunConnection

AutomationAddress

EditorAdd

MARK_DEBUGRegenerateLayoutValidateDesignGenerateBlock

DesignCreateHDL

WrapperVivadoIPintegratorIsplatformawarewithreal-time

DRCsCanbuildandreuseIP

subsystemsEnablesintelligentIP

integrationSupportsintegrated

debugFullGUIand/orTCL

interfacesRaisesthelevelofdesignabstraction,andincreasesdesigner

productivity!SummaryPage

9DEMOTCL,VivadoOne

WorldPart

1Lauren

GaoTCLbackgroundfromVivado

viewEditsynthesizednetlistwithTCLin

VivadoCustomizevariousreportswithTCLin

VivadoInteractwithVivadoby

TCLAgendaTCLbackgroundfromVivado

viewEditsynthesizednetlistwithTCLin

VivadoCustomizevariousreportswithTCLin

VivadoInteractwithVivadoby

TCLAgendaObjectsinVivado

Netlistcellcellcellcellnetpinportpackage

pinIO

bankcellEachobjecthasitsown

propertySomepropertiesare

read-onlySomepropertiesare

editableObjectcanbefoundbyfilteringwithcertain

propertyFiveCommonlyUsedTCLCommandsin

VivadoCommand-hierarchical-regexp-nocase-filter-of_objectsget_cells√√√√√get_nets√√√√√get_pins√√√√√get_portsX√√√√get_clocksX√√√√-hierarchical→

-hier-of_objects→

-of-filter:usingpropertiesto

filterA.String

Comparisonequal==not

equal!=match=~not

match!~B. Multiple

filter

expressions C. Booleantypeproperties:AND(&&),

OR(||)o get_ports-filter{DIRECTION==IN&&NAME!~

"*RESET*"}② get_cells-filter{IS_PRIMITIVE&&

!IS_SEQUENTIAL}③ get_cells

-hier

{*State* *reg*}④ get_cells→get_cells

*RelationshipAmong

ObjectscellpinportclocknetIO

bankPackage

Pinget_cells-of_objects{pins,timingpaths,nets,belsor

sites}get_clocks-of_objects{nets,ports,or

pins}get_nets-of_objects{pins,ports,cells,timingpathsorclocks}get_pins-of_objects{cells,nets,belpins,timingpathsor

clocks}get_ports-of_objects{nets,instances,sites,clocks,timingpaths,iostandards,

iobanks,package

pins}RelationshipAmong

ObjectsExample:Input:get_cells-of[get_nets-of[get_pins-of[get_cellswbDataForInput_IBUF_inst]-filter

{DIRECTION==OUT}]]Output:wbDataForInputReg_regvalidForEgressFifo_reg[0]_i_1

wbDataForInput_IBUF_instTCLbackgroundfromVivado

viewEditsynthesizednetlistwithTCLin

VivadoCustomizevariousreportswithTCLin

VivadoInteractwithVivadoby

TCLAgendaInsertFFinthe

netlistInsertFFinthelargelogicleveltiming

pathInsertFFbefore/after

DSP48E1InsertFFbefore/after

RAMB36E1Reducefanoutforlargefanout

netsReplicateregisterforlargefanout

netsInsertBUFGforlargefanout

netsModifyprobenetfor

test–ExportinternalnettoFPGApadfortestwithscopeorspectrum

analyzerRemoveunwantedobjectsfromthe

netlist–Removecellsand

netsSomeApplicationsofEditingSynthesizedDesignNetlistwith

TCLSaverun

timeDonotre-synthesize

designIdentifyissue

fastAvoiddifferentsynthesis

resultExample1:InsertFFintheLargeLogicLevelTiming

PathI0I1OQCCEDRI0I1I2I3I4I5