Vivado從此開(kāi)始（第2版）課件 36-TCL-Vivado-One-World-2 - 41-TCL-Vivado-One-World-7

Lauren

GaoTCL,VivadoOne

WorldPart2Howtogetlargefanout

netHowtogettimingreportthroughlargefanout

netHowtoconfirmBUFG

availableSomeItemsShouldBe

CaredTCLbackgroundfromVivado

viewEditsynthesizednetlistwithTCLin

VivadoCustomizevariousreportswithTCLin

VivadoInteractwithVivadoby

TCLAgendaVariousreportsgeneratedbyVivado

GUIReporttimingsummary:

report_timing_summaryReportclockinteraction:

report_clock_interactionReportutilization:

report_utilizationReportPower:

report_powerOtherusefulreportsgeneratedbyVivado

TCLReportclocks:

report_clocksReportclockutilization:

report_clock_utilizationReporttimingforcustormerizedpath:

report_timingReporthighfanoutnets:

report_high_fanout_netsReportcontrolsets:

report_control_setsReportIPstatus:

report_ip_statusReportpoweroptimizations:

report_power_optReportdesignanalysis:

report_design_analysisReportcrossdomainclocks:

report_cdcVariousReportsin

VivadoTheyareveryuseful

fordesignanalysis!Vivado

2014.3ReportHighFanoutNetsandControl

Setsreport_high_fanout_nets-min_fanout500-timing

-load_typesreport_control_sets-verbose-sort_by{clkset}CustomizableUtilization

Reportsreport_utilization-hierarchical-cells[get_cells

usbEngine0/u1]report_clock_utilizationInISE,generatingmoduleresourceutilizationonlywith‘GenerateDetailedMapReport’checkedinMAPproperty

panelInISE,clockutilizationisonlyavailableinresourceutilizationandcannotbegenerated

separatelyInVivado,youcangenerateprolificandcustomizablereportswith

TCLISECustomizableTiming

Reports#Description:-through:netpinor

cell

#Use-throughtogettimingpathandreporttiming

03procthr_timing_rpt{ListOfEmt}

{

04 puts[format{%-40s%-40s%-20s%-20s%7s}"StartPoint""End

point""LaunchClock""CaptureClock"

"Slack"]

091011121314puts[stringrepeat"-"

140]

setpath

[list]

setclass_type[listnetcellpin]

08 foreachthr_opt$ListOfEmt

{

setclass[get_propertyCLASS$thr_opt]

if{[lsearch$class_type$class]==-1}

{

puts"Error:-throughoptmustbenet,cellor

pin!"

return

1

}

setpath_i[get_timing_paths-through$thr_opt-nworst100

-unique_pins]

15 lappendpath

$path_i

16 }

18192021222317 foreachmypath$path

{

setstartpoint[get_propertySTARTPOINT_PIN$mypath]

setstartclock[get_propertySTARTPOINT_CLOCK$mypath]

setendpoint[get_propertyENDPOINT_PIN

$mypath]

setendclock[get_propertyENDPOINT_CLOCK

$mypath]

setslack[get_propertySLACK

$mypath]

puts[format{%-40s%-40s%-20s%-20s%7s}$startpoint

$endpoint$startclock$endclock

$slack]

24 }

25

}

Moreusefuloptionsinreport_timing

and

get_timing_paths-from-to-through-delay_type-max_paths-nworst-unique_pins-sort_by-slack_lesser_thanTCLbackgroundfromVivado

viewEditsynthesizednetlistwithTCLin

VivadoCustomizevariousreportswithTCLin

VivadoInteractwithVivadoby

TCLAgendaInISE,‘PackI/OregistersintoIOBs’isavailableinmapproperty.Therearefouroptions:ForInputsOnly,ForOutputsOnly,ForInputsandOutputs,

OffInVivado,itismoreflexiblewith

TCLPackinputregistersintoIOBsforspecified

portsset_propertyIOBtrue[all_fanout-flat-endpoints_only-only_cells[get_ports

lb_sel_pin]]set_propertyIOBtrue[get_ports

lb_sel_pin]Packallinputregistersinto

IOBsset_propertyIOBtrue[all_fanout-flat-endpoints_only-only_cells

[all_inputs]]set_propertyIOBtrue

[all_inputs]–PackoutputregistersintoIOBsforspecified

portsset_propertyIOBtrue[all_fanin-only_cells-startpoints_only-flat[get_ports

led_pins[0]]]set_propertyIOBtrue[get_ports

led_pins[0]]Packalloutputregistersinto

IOBsset_propertyIOBtrue[all_fanin-flat-startpoints_only-only_cells

[all_outputs]]set_propertyIOBtrue

[all_outputs]PackI/ORegistersinto

IOBset_propertyEstimatepoweratanystageafter

synthesisVectorandvectorlessmodesare

availablePower

optimizationMaximizepower

optimizationMinimizeitsimpacton

timingSetpoweroptexceptBRAMincritical

path–set_power_opt-exclude_cells[get_cells

alu/store_ram]Setpoweroptforspecifiedclock

regionset_power_opt-clocks[get_clocks

rx_clk]Setpoweroptforspecifiedtype

cellsset_power_opt-cell_types{bram

reg}SetPower

OptimizationGetstheobjectscurrentlyselectedintheVivado

IDEget_selected_objectsSelectsthespecifiedobjectintheappropriateopenviewsintheGUI

modeselect_objectsUnselectsthespecifiedobjectorobjectsthatwerepreviously

selectedunselect_objectsHot-keyF4:Generateschematic;F6:Showhierarchy;F7:Gotosource;F12:Unselect

allWorkwithVivadoSchematic

ViewTCLmakeVivadomore

POWERFULYoucandowhatISEcannot

doTCLmakeVivadomore

FLEXIBLEYoucandobetterwhatISEcan

doTCLmakeVivadomore

INTERACTIVEYoucanswitchbetweenGUIandTCL

smoothlySummaryLauren

GaoTCL,VivadoOne

WorldPart3:Hook

ScriptsTclSourcesin

VivadoCustomize

CommandsHook

ScriptXilinxTcl

StoreVivado

Self-containedVivadoug835Whatishook

script?ItisTCL

pre/post

capabilityforaVivado

processAlltheprocessinVivadocontainsthistcl.pre/.post

optionSynthesisandImplementationincludingeach

sub-steptcl.pre:

priorto

synthesisand

implementationtcl.post:

after

synthesisandimplementationHook

ScriptSpecifyahook

scriptCustom

reports–timing,power,utilization,oranyuser-definedtcl

reportModifyingthetimingconstraintsforportionsoftheflow

onlyModificationstonetlist,constraint,ordeviceprogrammingCommonUsesofHook

ScriptstimingpowerutilizationSynthesisImplementationtimingpowerutilizationOpt

DesignPowerOpt

DesignPlace

DesignPhysOpt

DesignSpecifyaHook

ScriptGUIBothin

SynthesisSettings

andin

Implementation

SettingsTclscriptSpecifyahookscriptwithTcl

scriptThepropertiestosetonasynthesis

runSTEPS.SYNTH_DESIGN.TCL.PRESTEPS.SYNTH_DESIGN.TCL.POSTExampleset_propertySTEPS.SYNTH_DESIGN.TCL.PRE

\{C:/Data/report.tcl}[get_runs

synth_1]You can define Tcl scriptsbefore and after each step of theimplementation

processOpt

DesignPowerOpt

DesignPlaceDesign,Post-PlacePowerOpt

DesignPhysOpt

DesignRouteDesignBitstream

generationSpecifyaHook

ScriptSTEPS.OPT_DESIGN.TCL.PRESTEPS.OPT_DESIGN.TCL.POSTSTEPS.POWER_OPT_DESIGN.TCL.PRESTEPS.POWER_OPT_DESIGN.TCL.POSTSTEPS.PLACE_DESIGN.TCL.PRESTEPS.PLACE_DESIGN.TCL.POSTSTEPS.POST_PLACE_POWER_OPT_DESIGN.TCL.PRESTEPS.POST_PLACE_POWER_OPT_DESIGN.TCL.POSTSTEPS.PHYS_OPT_DESIGN.TCL.PRESTEPS.PHYS_OPT_DESIGN.TCL.POSTSTEPS.ROUTE_DESIGN.TCL.PRESTEPS.ROUTE_DESIGN.TCL.POSTSTEPS.WRITE_BITSTREAM.TCL.PRESTEPS.WRITE_BITSTREAM.TCL.POSTIt’sSimpletoSpecifyaHook

ScriptSpecifyahook

scriptSpecifyahook

scriptset_propertySTEPS.<STEP_NAME>.TCL.PRE<Tcl

File>\[get_runssynth_1]set_propertySTEPS.<STEP_NAME>.TCL.POST<TclFile>\[get_runsimpl_1]Relativepathswithinthetcl.preandtcl.postscriptsarerelativeto

theappropriaterundirectoryoftheprojecttheyareapplied

to:<project>/<project.runs>/<run_name>YoucanusetheDIRECTORYpropertyofthecurrentprojector

currentruntodefinetherelativepathsinyourTclhook

scripts:get_propertyDIRECTORY[current_project]get_propertyDIRECTORY[current_run]RelativePathsinHook

ScriptDEMOLauren

GaoTCL,VivadoOne

WorldPart4:CustomizeTCL

CommandsTclSourcesin

VivadoCustomize

CommandsHook

ScriptXilinxTcl

StoreVivado

Self-containedVivadoVivadoitselfcontainsalotofusefulTclcommandswhichcoverdifferentapplicationsProject,Report,SDC,Simulation,Timing,Tools,

etc.TocustomizeTclcommands

canEnrichVivadoTclcontainer

convenientlyMeetsomepersonalizedrequirements

simplyReuseyourownTclscriptseffectivelyandeasilyWhyDoWeNeedtoCustomizeTcl

CommandsVivadoprovidesaseamlessinterfacetoinsertyourownTcl

commandsVivadoDesignSuiteprovidesafullTclinterpreterbuiltintothe

toolCreatingnewcustomcommandsandproceduresisasimple

taskYoucanwriteTclscriptsthatcanbeloadedandrunfromtheVivado

IDEYoucanwriteprocedures(orprocs),

toactlikenewTclcommandsTipsTclProcedureisrecommended,whichcanenhancetheefficiencyofyourTclcodeDefineTcl

ProcedureDEMOLauren

GaoTCL,VivadoOne

WorldPart5:XilinxTcl

StoreTclSourcesin

VivadoCustomize

CommandsHook

ScriptXilinxTcl

StoreVivado

Self-containedVivadoTcl-ToolCommand

LanguageCommonscriptinglanguageforallof

VivadoExtremelyimportantforconstrainingand

debugAmethodtodevelopandshareusefulTcl

codeXilinx3rd

PartiesCustomersand

usersControlled

ExperienceTestedcode-no

malwareNativeintegration-searching,using,

packagingCommon,basiccodingstandardsDocumentationand

helpIntroductiontoXilinxTcl

StoreAmodulethathasfunctionalitythatextendsVivadonative

TclConsistsofsome

codeoneormoreTclfiles,with

procssomepackagingfiles(more

Tcl)Acatalogxml

fileAnicon-

optionalTclApp

RepositoryAcollectionofTcl

AppsRepositoryishostedbya3rdpartyweb

serverLatestversionsofallappsareshippedwith

VivadoWhat'saTcl

App?ArchitectureofXilinxTcl

StoreTcl

RepositoryTcl APPUltraFastDesign

MethodologyDesignUtilitiesProjectUtilitiesDesignComparisonIncremental

CompileVivado

SimulatorUltraFastDesign

MethodologyTclFiles

(procs)TclFiles

(procs)TclFiles

(procs)Tcl

RepositoryTcl

AppsTclFiles

(procs)Installingan

App1123AfterInstallingtheTcl

App…Onceanapphasbeeninstalled,alltheprocsthatbelongtothisapp

canbeaccessedintwodifferent

waysFromthe::xilinx::myappnamespace::Tcl

ProcFromtheappnamespace

::tclapp::mycompany::myappAccessingtheTclprocsfromanInstalled

Appvivado>::xilinx::designutils::write_templateVivado>::tclapp::xilinx::designutils::write_templateThefirstwaysupportsnumberofdefaultcommandline

argumentssuchas-help,-verboseand

-quietUpdatingan

App12Uninstallingan

AppRepositoryHostedon

GitHub:/Xilinx/XilinxTclStoreHowtosetupGitand

GitHub:/articles/set-up-gitWikiexplainshowto

contribute:/Xilinx/XilinxTclStore/wiki/Xilinx-Tcl-App-Store-HomeAdditionalInformationfor

ContributorsDEMOLauren

GaoTCL,VivadoOne

WorldPart6:DesignFlowManagementwithTclinProject

ModeKeyadvantage–manytasksare

automatedSupportspush-button

flowAutomatic

managementProject

statusHDLsources,constraints,

IPsDependency

managementStoresimplementationresults,

reportsSavescheckpoints

(aftereach

step)Multipleruns

supportMultiple

strategiesControlledviaGUIand/or

TclNewVivadoDesignSuiteusers:Good

startingpointPage

2Project

ModeKeyflow

stepsPage

11ProjectMode:GUI→

Tcllaunch_runs

impl_1launch_runs

synth_1launch_runs

impl_1-to_step

write_bitstreamUnifiedData

ModelTcl:Project

ModeCheckPointsrereppoortrstsreportsAutomaticFourtypesofdesign

filesRTLdesign

filesVHDL(.vhd),Verilog(.v),SystemVerilog

(.sv)Testbenchfilesfor

simulationVHDL(.vhd),Verilog(.v),SystemVerilog

(.sv)XDCfilesfordesign

constraints.xdc,supportbothprojectandmoduledesign

constraintsIP

files.xci,IPshavebeengeneratedbyVivadoManage

IPIt’sbettertocreatedifferentfilefoldertostorethedesignfiles

accordinglyPreparingDesignFilesforVivado

ProjectsrcsimxdcIPOtherproject

properties–Targetlanguage:VHDL,

Verilogset_propertytarget_languageVHDL

[current_project]Sourcemanagementmode:All①,DisplayOnly②,

None③set_propertysource_mgmt_modeDisplayOnly

[current_project]Create

Projectcreate_projectwaveprjG:/Vivado/wavegen/waveprj

\-partxc7k325tffg900-2create_project–namewaveprj–dirG:/Vivado/wavegen/waveprj

\-partxc7k325tffg900-2Tclcommand:

create_projectThreeargumentsmustbe

specifiedPart,Projectname,work

directoryThreefilesetssources_1,sim_1andconstrs_1arecreatedinthesame

timeTwodesignrunssynth_1andimpl_1arealso

built.①②③Adddesignsource

filesadd_files-filesetsources_1

./srcupdate_compile_order-fileset

sources_1Addsimulationsource

filesadd_files-filesetsim_1./simupdate_compile_order-fileset

sim_1Addconstraints

filesadd_files-filesetconstrs_1

./xdcAddexisting

IPsadd_files[glob

./ip/*/*.xci]update_compile_order-fileset

sources_1AddDesignFilestoCurrent

ProjectDefineexpectedpropertiesfor

synthesisSetthevalueof

FLATTEN_HIERARCHYSetthemoduleasOOCCreatenewsynthesis

runSynthesis

Settingsset_propertySTEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHYrebuilt\[get_runs

synth_1]create_fileset-blockset-define_fromdac_spi

dac_spicreate_runsynth_2-flow{VivadoSynthesis2014}

\-strategy{VivadoSynthesis

Defaults}Launch

synthesisChecksynthesis

resultLaunchSynthesisandCheckSynthesis

Resultlaunch_runssynth_1wait_on_run

synth_1open_runsynth_1get_timing_paths-slack_lesser_than0

-quietBitfilepropertiesmustbesetafter

synthesisForexample:

CONFIGRATEConfigurationmemorysuchasSPIflashmustbesetaftersynthesisandbefore

implementationTakeSPIflashasan

exampleSPI_BUSWIDTHConfig_modeSettingConfigurationMemory

Propertyset_propertyBITSTREAM.CONFIG.CONFIGRATE66[get_designssynth_2]set_propertyCONFIG_VOLTAGE1.8[get_designssynth_2]set_propertyCFGBVSGND[get_designs

synth_2]set_propertyBITSTREAM.CONFIG.SPI_BUSWIDTH4[get_designssynth_2]set_propertyconfig_modeSPIx4

[current_design]Defineexpectedpropertiesfor

implementationSelectthedesired

strategyEnableorDisableintermediate

flowLaunch

implementationLaunchImplementationset_propertystrategyPerformance_Explore[get_runs

impl_1]set_propertySTEPS.PHYS_OPT_DESIGN.IS_ENABLEDtrue[get_runsimpl_4]set_propertySTEPS.OPT_DESIGN.ARGS.DIRECTIVEAddRemap

\[get_runs

impl_4]launch_runsimpl_1wait_on_run

impl_1GeneratebitfileCombineimplementationwithbitstreamgenerationGeneratememoryconfiguration

fileGenerateBitFilesandMemoryConfigurationFilelaunch_runsimpl_1-to_step

write_bitstreamwait_on_run

impl_1set_propertySTEPS.WRITE_BITSTREAM.ARGS.BIN_FILEtrue\[get_runsimpl_1]launch_runsimpl_1-to_stepwrite_bitstreamwait_on_runimpl_1write_cfgmem-force-formatMCS-interfaceSPIx4-loadbit

\"up0x0G:/Vivado/wavegen/waveprj/waveprj.runs/impl_2/wave_gen.bit"\G:/Vivado/wavegen/waveprj/waveprj.runs/impl_2/wave_gen_impl_2Page

20ScriptedProjectFlow:

Overview%add_files

…%import_files

…%launch_runs

synth_1%wait_on_run

synth_1Addsources:automatically

managed(VHDL,Verilog,IP,XDC,

…)Launchsynthesisrunand

waitLaunchimplementationrunand

waitGenerate

bitstreamsynth_1:Post-synthesisdesign=

DCPReportsimpl_1:Implementeddesign=post-routedDCPReportsRecall:Designsnapshotsandreportsautomaticallygeneratedsynth_1impl_1%launch_runs

impl_1%wait_on_run

impl_1%launch_runsimpl_1\-to_step

write_bitstream011010010001111001001100010100011111001001000010001000100100100010101001000010101000010bitstreamMaycombineProjectmode–directaccesstodesign

database– Post-synthesis– Post-implementationNeedto“openadesign”

firstopen_run

synth_1open_run

impl_1Available

toolsreport_timing,report_utilization,…create_clock,set_max_delay,…Reporting:Constraining:Netlistexploration:get_cells,get_nets,get_property,

…Page

21Project

ModeCustomDesign

Analysis%launch_runs

synth_1%wait_on_run

synth_1synth_1impl_1%launch_runs

impl_1%wait_on_run

impl_1Example:report_timingusingpost-implementation

designPage

22Project

ModeCustomDesign

AnalysisVivado%

report_timingERROR:[Common17-53]UserException:Noopendesign.Pleaseopenadesignbeforeexecutingthis

command.Vivado%

get_runssynth_1impl_1Vivado%open_run

impl_1INFO:[Netlist29-17]Analyzing290Unisimelementsfor

replacement...open_run:Time(s):cpu=00:00:29;elapsed=00:00:29.Memory(MB):peak

=4957.078;gain=40.016Vivado%

report_timingINFO:[Timing38-91]UpdateTimingParams:Speedgrade:-2,DelayType:max,Constraintstype:

SDC....Page

23Project

ModeAccesstoIntermediateImplementation

Resultslunch_runimpl_1–asetoffine-granularity

commandsInprojectmode:DCPstoredaftereach

commandOpenintermediateresults=open

checkpoint%opt_design%

place_design_opt.dcp_placed.dcp%

route_design…_routed.dcpimpl_1%launch_runs

impl_1%wait_on_run

impl_1open_checkpoint_opt.dcpopen_checkpoint

_placed.dcpProsHighdegreeof

automationFlow:asingleTclcommand–multipleflow

stepsSourceandresult

managementMultiplestrategies:easy

runConsFlowReducedflexibilitytoworkwithintermediateimplementation

resultsNotallfeaturesareeasily

accessible(ex:re-entrant

routing)Filestructure:fixedfile

organizationRevisioncontrol–manyproject

filesSummaryDemoLauren

GaoTCL,VivadoOne

WorldPart7:DesignFlowManagementwithTclinNonProject

ModeKeyadvantage–fullcontrolovereachdesignflow

step–Fullfreedomandresponsibilitytomanagea

designProject

statusHDLsources,constraints,

IPsDependency

managementStoreresults,

reportsSave

checkpointsNoautomaticmultiple-run

supportFlowcontrolSynthesis/implementation–

TclDesignanalysis–Tcland/orGUINon-ProjectMode–ASICType

Flowroute_designopt_designsynth_designwrite_bitstream…UnifiedData

ModelFullUser

ControlManualCheckpointsrereppoortrstsreportsFourtypesofdesign

filesRTLdesign

filesVHDL(.vhd),Verilog(.v),SystemVerilog

(.sv)XDCfilesfordesign

constraints.xdc,supportbothprojectandmoduledesign

constraintsIP

files.xci,IPshavebeengeneratedbyVivadoManage

IPEDIForNGC

filesIt’sbettertocreatedifferentfilefoldertostorethedesign

filesaccordinglyPreparingDesignFilesforVivadoNon

ProjectsrcsimxdcIPReaddesignconstraints

files–

read_xdcReadIPfilescustomizedby

Vivado–

read_ip– AlloutputproductsassociatedwiththeIPcore,includingthedesigncheckpointfile(DCP)willbereadintothein-memory

designReadDesignFilesintotheIn-memory

Designset_propertyFILE_TYPE"VerilogHeader"[get_filesinclude.v]set_propertyIS_GLOBAL_INCLUDEtrue[get_files

include.v]synth_ip Generate_targetRead

VHDL

files Read3rdpartyfiles(EDIFor

NGC)read_vhdl –

read_edifReadVerilog

filesread_verilog– ForverilogincludefilesScriptedNon-Project

FlowUnifiedData

Modelopt.dcppost-opttiming.rptsynth_designopt_designpower_opt_design