04_FPGA功耗優(yōu)化.ppt

1、Power Reduction Techniques,Altera Asia Pacific Regional Support Center,2,Agenda,Introduction Power-Driven Synthesis Power-Driven Fitting Clock Power Management Low-Power Design Conclusion,3,Introduction,67%,22%,11%,Dynamic Power DominantFocus of Power Optimization,99 Customer Designson Stratix II De

2、vices,4,Dynamic Power Optimization Flow,Automatic, but less accurate,Requires testbench,more accurate,Evaluate Power,RTL,Simulation,Power-Driven Fit,Design,Power Report,Vectorless,Estimation,Hardware,Measurement,Gate-Level Simulation,+ Power Analyzer,Estimate Toggle Rates,Normal,or,Extra effort,Powe

3、r-Driven,Synthesis,5,Power-Driven Synthesis,Located under: “Analysis 1kwords=deeper) MW “Maximum Depth” option selects wider/shallow RAMs for power e.g. 4 256 x16 blocks (x16=wider; 256words=shallow) Access only valid memory slice, disable the rest Does require additional decoder and mux logic howev

4、er,8,RAM Enable Optimization,Convert read/write enables to clock read/write enables Shuts RAM down when unused, using less power Set RAM Block Type = “Auto” Quartus II Power Optimizer chooses best RAM block configuration,9,Memory Balancing,Power Efficient Option,16,2:4 Decoder,4 256 x16 M4K RAMs,Def

5、ault Option,16,4 1k x4 M4K RAMs,1k x16 RAM,10,Maximum Depth Parameter,4k x36 Simple Dual-Port memory implementation using M4K blocks For 128-deep M4K memory block depth, extra logic power outweighs lower memory power Average Dynamic Power saving up to 50% PowerPlay Power Analyzer results based on si

6、mulation,M4K Blocks Configuration with Different Memory Depth and Width,Power Saving,Best Range,11,Power-Driven Fitting,Located under:“Fitter Settings”,12,Power-Driven Fitting Options,Extra effort Optimizes at the expense of speed and compile time Group high-toggling logic together to minimize routi

7、ng loads Group logic from same clock domains to minimize clock routing Runs PowerPlay Power Analyzer Best with Value Charge Dump (.VCD) or Signal Activity (.SAF) Normal compilation Optimizes without affecting speed or compile time Uses power efficient DSP block configurations by swapping input opera

8、nd order (transparent to designer),13,Minimize Routing Loads,Minimize capacitance of high-toggling signals Timing constraints maintained,14,Minimize Clock Routing,Standard Place else reg = reg; end;,21,Dynamic Clock Enable for RAMs,RAM power primarily from dynamic clocking Pre-charge, discharge of R

9、AM array Reducing number of clock events reduces dynamic power Address/data inputs have minimal effect on power Internal memory circuitry active whether address or data has changed Use memory clock enable control in MegaWizard Can obtain near zero dynamic power on cycles when RAM not accessed,22,Dyn

10、amic Clock Enable in MegaWizard,23,Low-Power Design,Design techniques utilize specific architecture features, focusing on low power TriMatrix memory optimizedfor different RAM functions Quartus II can select best sizeand configuration Use altsyncram MegaFunction DSP Implementation Mode Multiplicatio

11、n Multiply-Accumulation Multiply-Addition Less power than using ALM,24,Low-Power Design Glitch Reduction,Some logic produces many edges/transitions per cycle E.g. CRC/parity, combinational multipliers Each transition, or glitch, results in unnecessary power consumption Register inputs & outputs of t

12、o filter out “glitchy” behavior Insert pipeline registers if possible,Downstream,Logic,D,Q,25,Low-Power Design Pipelining,Effective for glitch prone arithmetic systems Advantages Increased speed Short logic depth Reduced switching (less dynamic power) Disadvantages Increased logic and register utili

13、zation May increase power for designs with minimal glitches Latency and throughput changed,26,Power Optimization Advisor,Explains power analysis best practices Provides Optimization suggestions Highlights recommended settings not enabled in design,27,Design Space Explorer,Searches Quartus options to

14、 find best implementation “Search for Lowest Power” Finds settings that minimize power while meeting timing constraints “quartus_sh dse”, or Tools Menu,28,Conclusion,Power reduction is a major part of successful FPGA design Quartus II software provides options to reduce power Power-Driven Synthesis Power-Driven Fitti