論文結構框圖及模塊化寫作2013n.docx

論文結構框圖與各部分寫作參考模板I題目及摘要Title必須清晰簡短(clear，short)Abstracts是paper的一個縮寫(miniature of whole paper)，一定要簡明扼要(less than 200 words)，按照paper的順序介紹主要研究對象(subject)、設計(design)、方法步驟(procedures)以及最后結果(results)。1） 目的研究、研制、調(diào)查等的前提、目的和任務，所涉及的主題范圍。2） 方法所用的原理、理論、條件、對象、材料、工藝、結構、手段、裝備、程序等。3） 結果實驗的、研究的結果、數(shù)據(jù)，被確定的關系，觀察結果，得到的效果、性能等。4） 結論結果的分析、研究、比較、評價、應用，提出的問題等。An Improved Buck PFC Converter With High Power FactorAbstractAn improved buck power factor correction (PFC) converter topology is proposed （presented） in this paper. By adding an auxiliary switch and two diodes, the dead zones in ac input current of traditional buck PFC converter can be eliminated. An improved constant ON-time control is proposed and utilized in this improved buck PFC converter to force it that operates in critical conduction mode (CRM).With optimal control parameters, nearly unit power factor can be achieved and the input current harmonics can meet the IEC61000-3-2 class C standard within the universal input voltage range. Moreover, the efficiency of the proposed converter is not deteriorated compared to the conventional buck converter. Detailed theoretical analysis and optimal design considerations for the proposed converter are presented and verified by a 100-W labmade prototype.Index TermsACDC, buck power factor correction (PFC),class C, high efficiency, high power factor (PF).An Adaptive Output Current Estimation Circuit for a Primary-Side Controlled LED DriverAbstractA primary-side controlled method is commonly used in flyback LED driver to regulate output current by employing an auxiliary winding. However, owing to intrinsic propagation delay in real-world circuits, a primary-side controlled flyback converter experiences a worse line regulation. This paper proposes a smart output current estimation scheme to improve line regulation for constant on-time control, and it can be compatible with the current flyback topology. A 9.5-W prototype of the proposed flyback LED driver has been fabricated in Nuvoton Technology Corporation 0.6-m 5-V/40-V CMOS process. The maximum switching frequency is set to around 100 kHz with universal-line input, single-stage power factor correction for LED lighting applications. Experimental results prove that the proposed scheme can improve the line regulation within 1.5% and the power efficiency can be up to 89.7%.Index Terms Flyback converter, light-emitting diode (LED) driver, line regulation, primary-side controlled.A Very Simple Control Strategy for Power Factor Correctors Driving High-Brightness LEDsAbstractThis paper presents a new control strategy for power factor correctors (PFCs) that are used to drive high-brightness LEDs. This control strategy is extremely simple and is based on the use of a conventional peak-current-mode controller with a suitable selection of the compensation ramp waveform. Neither an analog multiplier nor an input voltage sensor is needed to achieve quasi sinusoidal line waveforms at nominal conditions and full load. If the converter belongs to the flyback family (flyback, buckboost,SEPIC, Cuk and Zeta), the line waveform appears notably distorted if the compensation function is a linear ramp, but becomes almost sinusoidal if the linear ramp is substituted by a properly chosen exponential function. The linewaveform is slightly distorted when the load varies or when the converter works under either overvoltage or undervoltage conditions. However, the waveform maintains a very high power factor (PF) even under these conditions. Moreover, the line current is cycle-by-cycle-controlled due to the peak-current-mode control, and hence, the input-current feedback loop is extremely fast, thereby allowing this type of control to be used with high-frequency lines (above 400 Hz).Index TermsAC/DC converters, converters for lighting, current-mode control, high brightness (HB) LEDs, single-phase power factor (PF) correction.Load Current Adaptive Control of a Monolithic CMOS DC/DC Converter for Dynamic Power ManagementAbstract This paper presents the design of a monolithic current-mode CMOS DC/DC converter with integrated power switches and an on-chip passive adaptive controller with the sensed average inductor current. The sensed switched current, combined with the integration of inductor voltage, and avoltage-controlled floating resistor, can be used for the adaptive control of a CMOS DC/DC converter. The nonlinear carrier control can adjust carrier according to input voltage to reduce the input disturbance. The proposed control scheme has been design and simulation verified based on the TSMC 0.35um technology. The designed CMOS DC/DC switching regulator is based on a rated output current of 500mA with an adjustable output voltage from 1.0V to 1.8V. Simulation results shows the proposed adaptive control scheme can achieve a fast dynamic power on transient response as well as a robust voltage regulation against large loading current variation.Index Terms CMOS DC/DC converters, synchronous buck regulator, load current adaptive control, nonlinear carrier,fast dynamic response, dynamic power management.New Digital-Controlled Technique for Battery Charger With Constant Current and Voltage Control Without Current FeedbackAbstractThe main theme of this paper is to present a new digital-controlled technique for battery charger to achieve constant current and voltage control while not requiring current feedback. The basic idea is to achieve constant current charging control by limiting the duty cycle of charger. Therefore, the current feedback signal is not required and thereby reducing the cost of A/D converter, current sensor, and computation complexity required for current control. Moreover, when the battery voltage is increased to the preset voltage level using constant current charge, the charger changes the control mode to constant voltage charge. A digital-controlled charger is designed and implemented for uninterrupted power supply (UPS) applications. The charger control is based upon the proposed control method in software. As a result, the UPS control, including boost converter, charger, and inverter control can be realized using only one low cost MCU. Experimental results demonstrate that the effectiveness of the design and implementation.Index TermsCharger, constant current charge, constant voltage charge.Digitally Controlled Switching Converter with Automatic Multi-Mode Switching AbstractThis paper presents a multi-mode digital controller with dead-time self-exploration (DTSE) for synchronous buck converters that simultaneously achieves high efficiency and a fast transient response. The automatic mode switching technique uses the duty-cycle command to determine multi-mode operation without sensing any current signals. The DTSE algorithm is used to minimize the steady-state duty-cycle command to maximize converter efficiency. During load transients, a non-linear control mode is employed to reduce the transient response. The proposed digital controller is fabricated in a CMOS 0.18-m process. The experimental results for a 1.2-V output voltage show that the measured power efficiency is higher than 85% for a load range of 10600 mA and that the measured transient response is improved by 28% compared to that of the traditional voltage-mode converter. Index TermsMulti-mode control, synchronous buck regulator, digital control, dead time, automatic mode switching.II.前言Introduction同樣要保證簡短，順序是一般背景介紹、別人工作成果、自己的研究目的及論文工作簡介，其中介紹別人工作時只需介紹和自己最相關的方面(very relevant)，而對自己的工作介紹不用說明細節(jié)，因為這個要放到body中去。不要忘記在介紹自己工作之前要有一個declarative statement。INTRODUCTIONNOWADAYS, most ac/dc power converters are forced to reduce the harmonic current to meet the IEC61000-3-2 limits 1. Some special power products such as lighting equipments should meet the stricter IEC61000-3-2 class C limits.Power factor correction (PFC) is a good method for providing an almost sinusoidal input current. The boost converter is the most popular topology for PFC applications due to its inherent current shaping ability 24. However, with universal input, usually a 400 Vdc output voltage is required for the boost PFC. The boost PFC cannot achieve high efficiency at low line input because it works with large duty cycle in order to get high-voltage conversion gain. Therefore, it is hard to increase the power density of boost PFC converter due to the thermal concern at low line input. THE Sepic converter 5, 6 and quadratic buck-boost 7, 8can achieve high power factor (PF) and reduce the output voltage stress. But the voltage stress of switch in these two topologies is much higher than that in the boost PFC converter that reduces the efficiency and increases the cost. The buck PFC converter has some attractive merits. First, the output voltage of buck converter is always regulated lower than the boost converter. Second, the voltage across the main switch of the buck converter is almost clamped to the input voltage. Therefore, the buck PFC converter can achieve relatively high efficiency within the universal input voltage range and it has drawn more and more attention in the past years 925. However, if the buck converter operates in hard switching mode, the switching loss especially at high input will be large, which deteriorates the merit of the buck converter 918. The buck dcdc converter operating in critical continuous conduction mode (CRM) can eliminate the reverse recovery loss in diode and achieve zero voltage switching (ZVS) for the switch 19, 20. The constant ON-time (COT) control for CRM buck PFC converter is introduced in 2123. With COT control, the peak current in the switch is almost proportional to the input voltage, and then high PF can be achieved. However, it is still difficult to pass the IEC61000-3-2 criteria due to the dead zones in the input current that appears when the input voltage is lower than output V0 . An improved COT control is introduced in 24. This improved COT control can help improve the PF of the conventional buck PFC converter. However, this improved COT control method needs careful parameters design. Even so, it is still hard to meet the limits imposed by IEC61000-3-2 class C Criteria at the low line input voltage. In this paper, an improved buck PFC converter is proposed, as shown in Fig. 1. Compared with the conventional buck PFC converter, an auxiliary switch and two diodes are added in the improved buck PFC converter. The proposed converter has two different operation modes in a line period. When the input voltage is higher than the output voltage, the proposed converter operates in buck mode, which is same as the conventional buck converter. When the input voltage is lower than the output voltage, the proposed converter operates in buck-boost mode. Hence, there are no dead zones in the input current. The PF can be improved obviously, and then the proposed converter can meet IEC61000-3-2 class C criteria easily with enough margins. Moreover, the efficiency of the proposed converter is very close to the conventional buck converter. The proposed converter is suitable for the PFC front stage of ac/dc converter and LED drivers with the power range from 60 to 300 W. The detailed operation principle is illustrated in Section II and the circuit parameters design considerations are presented in Section III. Finally, the experimental results based on a 100-W prototype will be given in Section IV.INTRODUCTIONRECENTLY, light-emitting diodes (LEDs) have become popular as solid-state lighting sources 13. For application of LED lighting, several control methods for dcdc converters were proposed in 4, 5 to obtain a constant output current for driving LED. Moreover, in Energy Star requirement for solid-state lighting luminaires 6, the power factor(PF) needs to be higher than 0.7. In order to meet the Energy Star specifications, the LED driver can mainly be classified into single-stage 711 and two-stage topologies 12. In recent years, the single-stage primary-side controlled flyback converter is more and more adopted in general lighting applications because of its low cost, electrical isolation, compact volume, and simplicity 1322.In the flyback converter, the primary-side controlled method regulates its output current by employing an auxiliary winding for indirect sensing output voltage on the primary side. Hence,the primary-side peak current is usually constant in order to keep constant output current 2326. In contrast to the conventional control method, the primary-side controlled method does not need optocoupler to transfer the error signal from the secondary side to the primary side. However, owing to the intrinsicpropagation delay of control signals in real-world circuits, the primary-side controlled flyback converter experiences a worse line regulation in a universal-line power-supply system.The relevant issue was discussed in 27 and 28 and illustrated in Section III. Therefore, in the primary-side controlled flyback converter, the line regulation is a key parameter.In this paper, a smart output current estimation scheme has been proposed to improve line regulation for the universal-line system. This paper is organized as follows. The control method with constant on-time scheme is illustrated in Section II. Then,the line regulation variation phenomenon and the proposed peakcurrent estimator schemewill be discussed in Sections III and IV,respectively. The experimental results are shown in Section V.Finally, the conclusion is made in Section VI.III主體部分Body部分可以分為principle、methods、result三個部分：Methods，詳盡的介紹自己的設計方案以便于他人能夠重復自己的設計過程，對于通用的方案可以簡略，重點要放到自己的獨創(chuàng)性上(own procedures)。Result，使用text、table、figure等手段表達出來，其中table不要使用過多，而figure必須保證圖線清楚、注解明確。PRINCIPLE OF OPERATIONIn this section, the proposed converter operates in CRM will be analyzed in detail. To simplify the analysis, the transitions between the switches and the output diode Do are omitted. After that, there still exist eight operation stages in a line period. Fig. 2 shows the equivalent circuits of the stages. Fig. 1. Proposed improved buck PFC converter.MODEL Fig. Simplified ACMC DC-DC converters Control loop block diagram of ACMC DC-DC convertersDESIGN PROCESSDesign considerations of the proposed buck PFC converter controlled by the improved COT control are presented in this section. All the calculations next are based on a 100Wprototype with 90 V265 Vac universal input. The output voltage is set to 80 V. Considering the output voltage ripple, the boundary voltage between the buck mode and buck-boost mode is set to 90 V. Main components parameters are shown in Fig. 3.Flow chart of modified DTSE algorithm.IV. EXPERIMENTAL RESULTSThe PFC circuit has been implemented in a 0.35-m BCDMOS process and its microphotograph is shown in Fig. 9.The area of the whole chip is 2.03 mm2 . The PFC circuit is designed so that it can select one between the conventional ZCD with a sensing resistor and the proposed resistor-free ZCD. The conventional ZCD with a sensing resistor includes the VtON processing circuit as well, and its sensing resistor is 0.1 .Fig. Microphotograph of the PFC circuitExperimental Set-Up The experimental set-up shown in Fig. 9 demonstrates the closed-loop operation. The power MOSFET chips are SI2300DS, which have been used as both high- and low-side MOSFETs with a single gate driver (MCP147000). The A/D conversion is made using an AD7822 chip. The error signal en, which ranges from -4 to 4, is sent to the chip over a parallel bus. Measurement Results The measured steady-state waveform of PFM operation is shown in Fig. 10. The ripple on the output voltage is less than 16 mV. Note that the switching frequency in PFM mode and the output voltage ripple agree with the design considerations described in Section IV. Fig. 11 shows the waveform of PWM operation. The ripple on the output voltage is less than 10 mV. In Fig. 11(a), the dead times are not optimized and the body-diode conduction loss is large. The power loss reduces the efficiency of the converter. In Fig. 11(b), the dead times are optimized. The body-diode conduction loss is almost eliminated and thus the converter efficiency is improved in steady-state operation. Fig. 12 shows that the input voltage sensor works well at input voltages of 2.7 V and 3.6 V.Fig. 9. Experimental set-up.The system characteristics and specifications of the proposed controller and a comparison with existing digital switching DC-DC converters are summarized in Table III. The proposed controller achieves a higher efficiency and a faster transient response. Compared with other works, the proposed architecture does not need an additional current sensor to select the optimal operation mode because automatic mode switching is decided from the duty-cycle command. In addition, the advantage of the fast transient and adjusted dead times are obvious for our proposed multi-mode control scheme. Notably, compared to 19, the recovery times and overshoots are large. For recovery times, the work in 19 increases the unity-gain frequency and improves phase margin by using a predictive PID controller. Design of a digital PID compensator is more complexity. Thus, we proposed a simple algorithm and low computation complexity to improve transient response, but sacrifice the recovery times. Also, the feed-forward control in 19 successfully limits the overshoot and undershoot to the desired values. In this work, the input voltage sensor only used to sense the input voltage Vin and then quantizes it into Vinn. The proposed digital controller is suitable for SoC integration.The performance of the implemented PFC circuit employing the proposed resistor-free ZCD scheme is summarized in Table I.V結論：給出論文工作的主要結