AD9854對(duì)照翻譯.docx

資料整理 AD9854 FEATURES 300 MHz internal clock rate FSK, BPSK, PSK, chirp, AM operation Dual integrated 12-bit digital-to-analog converters (DACs) Ultrahigh speed comparator, 3 ps rms jitter Excellent dynamic performance 80 dB SFDR at 100 MHz (1 MHz) AOUT 4 to 20 programmable reference clock multiplier Dual 48-bit programmable frequency registers Dual 14-bit programmable phase offset registers 12-bit programmable amplitude modulation and on/off output shaped keying function Single-pin FSK and BPSK data interfaces PSK capability via input/output interface Linear or nonlinear FM chirp functions with single-pin frequency hold function Frequency-ramped FSK 25 ps rms total jitter in clock generator mode 特征300 MHz內(nèi)部時(shí)鐘速率支持FSK, BPSK, PSK, chirp, AM調(diào)制集成雙路12位數(shù)/模轉(zhuǎn)換器（DAC）超高速比較器，3個(gè)PS RMS抖動(dòng)出色的動(dòng)態(tài)性能80dB的SFDR在100 MHz（ 1 MHz）的AOUT4 20可編程參考時(shí)鐘倍頻器雙48位可編程頻率寄存器雙通道，14位可編程相位偏移寄存器12位可編程振幅調(diào)制ON / OFF輸出形鍵控功能單引腳FSK和BPSK的數(shù)據(jù)接口通過(guò)輸入/輸出接口實(shí)現(xiàn)PSK功能單線實(shí)現(xiàn)線性或非線性的調(diào)頻功能 頻率暫停功能頻率ramped的FSK25 ps的均方根時(shí)鐘發(fā)生器模式的總抖動(dòng)Automatic bidirectional frequency sweeping Sin(x)/x correction Simplified control interfaces 10 MHz serial 2- or 3-wire SPI compatible 100 MHz parallel 8-bit programming 3.3 V single supply Multiple power-down functions Single-ended or differential input reference clock Small, 80-lead LQFP or TQFP with exposed pad APPLICATIONS Agile, quadrature LO frequency synthesis Programmable clock generators FM chirp source for radar and scanning systems Test and measurement equipment Commercial and amateur RF exciters 雙向自動(dòng)掃頻sin（x）/ x修正簡(jiǎn)化的控制接口兼容10 MHz串行2 或3線SPI總線100兆赫并行8位總線3.3 V單電源供電多重省電功能參考時(shí)鐘可單端或差分輸入小型，80引腳LQFP或帶有散熱焊盤的TQFP封裝 應(yīng)用正交LO頻率合成可編程時(shí)鐘發(fā)生器調(diào)頻雷達(dá)和掃描系統(tǒng)的線性調(diào)頻源測(cè)試與測(cè)量設(shè)備商業(yè)及業(yè)余射頻發(fā)射器目錄特點(diǎn). .一應(yīng)用. .一功能框圖. .一修訂歷史. .三一般描述. . 4規(guī)格. . 5絕對(duì)最大額定值. . 8熱阻. . 8測(cè)驗(yàn)等級(jí)說(shuō)明. . 8防靜電提示. . 8引腳配置和功能說(shuō)明. 9典型性能特征. 12典型應(yīng)用. . 16操作原理. . 19操作模式. . 19使用AD9854 . . 29內(nèi)部和外部更新時(shí)鐘. 29ON / OFF輸出形鍵控（僑豐）. 29I和Q數(shù)模轉(zhuǎn)換器. . 30控制DAC . . 30逆Sinc函數(shù). . 31REFCLK乘法器. 31編程AD9854 . . 32主復(fù)位. . 32并行I / O操作. . 34串行端口I / O操作. . 34一般操作的串行接口. 36指令字節(jié). . 37串行接口引腳說(shuō)明. 37串口操作的注意事項(xiàng). . 37的MSB / LSB的轉(zhuǎn)移. . 38控制寄存器的說(shuō)明. . 38功耗和散熱考慮. 40熱阻抗. . 40結(jié)溫事項(xiàng). 40評(píng)價(jià)工作條件. 41熱增強(qiáng)型封裝安裝指南. 41評(píng)估板. . 42評(píng)估板說(shuō)明. . 42一般操作說(shuō)明. 42使用提供的軟件. . 44支持. . 44外形尺寸. . 52訂購(gòu)指南. . 52GENERAL DESCRIPTION The AD9854 digital synthesizer is a highly integrated device that uses advanced DDS technology, coupled with two internal high speed, high performance quadrature DACs to form a digitally programmable I and Q synthesizer function. When referenced to an accurate clock source, the AD9854 generates highly stable, frequency-phase, amplitude-programmable sine and cosine outputs that can be used as an agile LO in communications, radar, and many other applications. The innovative high speed DDS core of the AD9854 provides 48-bit frequency resolution (1 Hz tuning resolution with 300 MHz SYSCLK). Maintaining 17 bits ensures excellent SFDR. 概述在AD9854數(shù)字頻率合成器是一種高度集成的器件，采用先進(jìn)的DDS技術(shù)，具有兩個(gè)內(nèi)部耦合高速，高性能正交數(shù)模轉(zhuǎn)換器以實(shí)現(xiàn)數(shù)字可編程的I/Q合成功能。使用精確的時(shí)鐘參考源，AD9854生成高度穩(wěn)定，頻率相位、幅度可編程的正弦和余弦信號(hào)，可作為通信，雷達(dá)以及許多其他應(yīng)用中的可變本振輸。新型的高速AD9854高速DDS內(nèi)核可提供48位頻率分辨率（300 MHz的系統(tǒng)時(shí)鐘1Hz調(diào)諧分辨率）。保持17位，確保優(yōu)秀的SFDR。The circuit architecture of the AD9854 allows the generation of simultaneous quadrature output signals at frequencies up to 150 MHz, which can be digitally tuned at a rate of up to 100 million new frequencies per second. The sine wave output (externally filtered) can be converted to a square wave by the internal comparator for agile clock generator applications. The device provides two 14-bit phase registers and a single pin for BPSK operation. AD9854電路結(jié)構(gòu)允許輸出高達(dá)150兆赫的正交頻率信號(hào)，同時(shí)可支持每秒1億次品率更新。正弦波輸出（外部過(guò)濾）可以經(jīng)由片內(nèi)比較器轉(zhuǎn)換為方波信號(hào)，以用作時(shí)鐘發(fā)生器。該器件提供兩個(gè)14位相位寄存器和一個(gè)BPSK操作引腳。For higher-order PSK operation, the I/O interface can be used for phase changes. The 12-bit I and Q DACs, coupled with the innovative DDS architecture, provide excellent wideband and narrow-band output SFDR. The Q DAC can also be configured as a user-programmable control DAC if the quadrature function is not desired. When configured with the comparator, the 12-bit control DAC facilitates static duty cycle control in high speed clock generator applications. 對(duì)于高階PSK應(yīng)用，I / O接口可用于相位控制。 12位I和Q數(shù)模轉(zhuǎn)換器，與新結(jié)構(gòu)的DDS結(jié)合，提供良好的寬帶或窄帶輸出的SFDR。如果不需要正交樹(shù)出，DAC的Q路也可以配置為一個(gè)用戶可編程控制DAC。當(dāng)與比較器配合用作高速時(shí)鐘發(fā)生器時(shí)，12位控制DAC有利于穩(wěn)定占空比。Two 12-bit digital multipliers permit programmable amplitude modulation, on/off output shaped keying, and precise amplitude control of the quadrature output. Chirp functionality is also included to facilitate wide bandwidth frequency sweeping applications. The programmable 4 to 20 REFCLK multiplier circuit of the AD9854 internally generates the 300 MHz system clock from an external lower frequency reference clock. This saves the user the expense and difficulty of implementing a 300 MHz system clock source. 兩個(gè)12位可編程數(shù)字乘法器允許調(diào)幅，ON / OFF輸出形鍵控和正交輸出的精確幅度控制。啁啾的功能還適用于寬帶掃頻應(yīng)用。AD9854內(nèi)部的可編程4至20倍的REFCLK倍頻電路可以從較低頻率的外部參考時(shí)鐘頻率方便地產(chǎn)生300 MHz的系統(tǒng)時(shí)鐘。這樣可以節(jié)省用戶的費(fèi)用，降低采用300 MHz系統(tǒng)時(shí)鐘源的困難。Direct 300 MHz clocking is also accommodated with either single-ended or differential inputs. Single-pin conventional FSK and the enhanced spectral qualities of ramped FSK are supported. The AD9854 uses advanced 0.35 m CMOS technology to provide a high level of functionality on a single 3.3 V supply. The AD9854 is pin-for-pin compatible with the AD9852 single-tone synthesizer. It is specified to operate over the extended industrial temperature range of 40C to +85C.單端或差分輸入的300 MHz時(shí)鐘也是允許的。支持常規(guī)單引腳FSK和增強(qiáng)譜FSK。AD9854采用先進(jìn)的0.35微米CMOS技術(shù)，可在3.3 V單電源下提供高性能的功能。AD9854與AD9852引腳對(duì)引腳地兼容。它可以在-40 C至+85 C工業(yè)溫度范圍內(nèi)工作。第8頁(yè)To determine the junction temperature on the application PCB use the following equation: TJ = Tcase + (JT PD) where: TJ is the junction temperature expressed in degrees Celsius. Tcase is the case temperature expressed in degrees Celsius, as measured by the user at the top center of the package. JT = 0.3C/W. PD is the power dissipation (PD); see the Power Dissipation and Thermal Considerations section for the method to calculate PD.要確定PCB上應(yīng)用中的器件的結(jié)溫使用下列公式：TJ = Tcase + (JT PD) 其中：TJ是結(jié)溫的攝氏度表示。Tcase是外殼溫度的攝氏度表示，由用戶在封裝的頂部的中心位置測(cè)量。JT = 0.3C/W. PD是散熱焊盤;見(jiàn)功耗計(jì)算方法和PD的散熱設(shè)計(jì)部分。ESD警告ESD(靜電放電)敏感器件帶電器件和電路板可能會(huì)在沒(méi)有覺(jué)察的情況下放電。盡管本產(chǎn)品具有專利或?qū)Ｓ玫谋Ｗo(hù)電路，但在遇到高能量的ESD時(shí)，器件可能會(huì)損壞。因此，應(yīng)當(dāng)采用適當(dāng)?shù)腅SD防范措施，以避免器件性能下降或功能喪失。THEORY OF OPERATION The AD9854 quadrature output digital synthesizer is a highly flexible device that addresses a wide range of applications. The device consists of an NCO with a 48-bit phase accumulator, a programmable reference clock multiplier, inverse sinc filters, digital multipliers, two 12-bit/300 MHz DACs, a high speed analog comparator, and interface logic. This highly integrated device can be configured to serve as a synthesized LO, an agile clock generator, or an FSK/BPSK modulator. Analog Devices, Inc., provides a technical tutorial about the operational theory of the functional blocks of the device. The tutorial includes a technical description of the signal flow through a DDS device and provides basic applications information for a variety of digital synthesis implementations. The document, A Technical Tutorial on Digital Signal Synthesis, is available from the DDS Technical Library, on the Analog Devices DDS website at /dds. 操作原理正交輸出的AD9854數(shù)字頻率合成器是一個(gè)高度靈活的設(shè)備，應(yīng)用廣泛。該裝置由一個(gè)48位相位累加器，一個(gè)可編程參考時(shí)鐘倍頻器，反SINC濾波器，數(shù)字乘法器，兩個(gè)12-bit/300 MHz的DAC，1個(gè)高速模擬比較器和接口邏輯構(gòu)成。這種高度集成的器件可以配置集成本地震蕩器，捷變頻的時(shí)鐘發(fā)生器或者FSK/ BPSK的調(diào)制器。ADI公司提供了有關(guān)該設(shè)備的功能說(shuō)明和使用教程。本教程包括對(duì)DDS的設(shè)備信號(hào)流程的技術(shù)說(shuō)明，并提供了數(shù)字頻率合成器實(shí)現(xiàn)各種基本應(yīng)用的信息。該數(shù)字信號(hào)合成技術(shù)指導(dǎo)，可從DDS的技術(shù)資料庫(kù)，在ADI公司的的網(wǎng)站/dds.下載MODES OF OPERATION The AD9854 has five programmable operational modes. To select a mode, three bits in the control register (parallel Address 1F hex) must be programmed, as described in Table 5.操作模式AD9854有五個(gè)可編程的運(yùn)作模式。要選擇某一模式，三個(gè)控制寄存器（并行地址為十六進(jìn)制1F）位必須進(jìn)行編程，如表5所示。In each mode, some functions may be prohibited. Table 6 lists the functions and their availability for each mode.每種模式，某些功能可能被禁止。表6列出了每種模式下可用的功能。Single Tone (Mode 000) This is the default mode when the MASTER RESET pin is asserted. It can also be accessed if the user programs this mode into the control register. The phase accumulator, responsible for generating an output frequency, is presented with a 48-bit value from the Frequency Tuning Word 1 registers that have default values of 0. Default values from the remaining applicable registers further define the single-tone output signal qualities. The default values after a master reset configure the device with an output signal of 0 Hz and zero phase. At power-up and reset, the output from the I and Q DACs is a dc value equal to the midscale output current. This is the default mode amplitude setting of 0. See the On/Off Output Shaped Keying (OSK) section for more details about the output amplitude control. All or some of the 28 program registers must be programmed to produce a user-defined output signal. Figure 35 shows the transition from the default condition (0 Hz) to a user-defined output frequency (F1). 單音（模式000）這是主復(fù)位引腳有效后的默認(rèn)模式。它也可由用戶程序通過(guò)控制寄存器來(lái)設(shè)置。相位累加器所產(chǎn)生輸出頻率，由頻率控制字1寄存器中默認(rèn)值為0的48位設(shè)置。剩余的頻率控制字1寄存器進(jìn)一步明確單音輸出信號(hào)質(zhì)量，這些位默認(rèn)值是0。主復(fù)位后的默認(rèn)信號(hào)輸出值設(shè)定為0赫茲和零相位。在上電和復(fù)位，從I和Q路 DAC的輸出是直流，其值等于量程輸出電流。這是默認(rèn)模式幅度設(shè)置為0。請(qǐng)參閱振蕩鍵控調(diào)制關(guān)于輸出幅度控制更詳細(xì)的部分。為了產(chǎn)生用戶所需的信號(hào)頻率，需要對(duì)全部或部分的28個(gè)寄存器進(jìn)行編程。圖35顯示了從默認(rèn)設(shè)置（0 Hz）到用戶定義的輸出頻率（F1）的過(guò)渡。As with all Analog Devices DDS devices, the value of the frequency tuning word is determined by和ADI公司所有DDS器件一樣，頻率控制字值由下式?jīng)Q定:where: N is the phase accumulator resolution (48 bits in this instance). Desired Output Frequency is expressed in hertz. FTW (frequency tuning word) is a decimal number. 其中：N為相位累加器的分辨率（在此處為48位）。所需的輸出頻率單位為赫茲。FTW（頻率調(diào)諧字）是一個(gè)小數(shù)。After a decimal number has been calculated, it must be rounded to an integer and then converted to binary format, that is, a series of 48 binary-weighted 1s and 0s. The fundamental sine wave DAC output frequency range is from dc to one-half SYSCLK. Changes in frequency are phase continuous, meaning that the first sampled phase value of the new frequency is referenced from the time of the last sampled phase value of the previous frequency. The I and Q DACs of the AD9854 are always 90 out of phase. The 14-bit phase registers do not independently adjust the phase of each DAC output. Instead, both DACs are affected equally by a change in phase offset.經(jīng)過(guò)一個(gè)十進(jìn)制數(shù)進(jìn)行了計(jì)算，必須四舍五入為整數(shù)，然后轉(zhuǎn)換為二進(jìn)制格式，也就是48個(gè)二進(jìn)制加權(quán)的1和0?；镜恼也―AC輸出頻率范圍從DC到二分之一的系統(tǒng)時(shí)鐘SYSCLK。在頻率變化是相位連續(xù)的，既是說(shuō)新的頻率相位值參考從先前的最后一次采樣頻率的相位值。I和Q的AD9854 DAC的總是90 的相位差。 14位相位寄存器不獨(dú)立調(diào)節(jié)每個(gè)DAC輸出相位。相反，兩個(gè)DAC是同樣受到了相同偏置的影響。The single-tone mode allows the user to control the following signal qualities: Output frequency to 48-bit accuracy Output amplitude to 12-bit accuracy Fixed, user-defined amplitude control Variable, programmable amplitude control Automatic, programmable, single-pin-controlled on/off output shaped keying Output phase to 14-bit accuracy These qualities can be changed or modulated via the 8-bit parallel programming port at a 100 MHz parallel byte rate or at a 10 MHz serial rate. Incorporating this attribute permits FM, AM, PM, FSK, PSK, and ASK operation in single-tone mode.單音頻模式允許用戶控制以下信號(hào)特征：輸出頻率為48位精度輸出幅度為12位精度固定，用戶定義的幅度控制可變，可編程振幅控制自動(dòng)，可編程，單引腳控制開(kāi)/關(guān)輸出形鍵控輸出相位，以14位精度這些參數(shù)可以通過(guò)100 MHz并行字節(jié)率 的8位并行總線或在10 MHz串行速率的串行總線設(shè)置。此外,這一特性使單頻模式支持FM, AM, PM, FSK, PSK和 ASK等多種調(diào)制方式.Unramped FSK (Mode 001) When the unramped FSK mode is selected, the output frequency of the DDS is a function of the values loaded into Frequency Tuning Word Register 1 and Frequency Tuning Word Register 2 and the logic level of Pin 29 (FSK/BPSK/HOLD). A logic low on Pin 29 chooses F1 (Frequency Tuning Word 1, Parallel Address 4 hex to Parallel Address 9 hex), and a logic high chooses F2 (Frequency Tuning Word 2, Parallel Register Address A hex to Parallel Register Address F hex). Changes in frequency are phase continuous and are internally coincident with the FSK data pin (Pin 29); however, there is deterministic pipeline delay between the FSK data signal and the DAC output. (Refer to the pipeline delays in Table 1.) The unramped FSK mode, shown in Figure 36, represents traditional FSK, radio teletype (RTTY), or teletype (TTY) transmission of digital data. FSK is a very reliable means of digital communication; however, it makes inefficient use of the bandwidth in the RF spectrum. Ramped FSK, shown in Figure 37, is a method of conserving bandwidth.unramped FSK（模式001）當(dāng)unramped FSK模式時(shí)，DDS的輸出頻率是頻率調(diào)諧字寄存器1、頻率調(diào)諧字寄存器2和引腳29（FSK/BPSK/HOLD）邏輯電平的函數(shù)。引腳29的邏輯低電平選擇頻率F1（頻率調(diào)諧字1，十六進(jìn)制并行地址4到9），邏輯高電平選擇頻率F2（頻率調(diào)諧字2，十六進(jìn)制并行地址A到F）。輸出頻率變化時(shí)相位是連續(xù)的，并在內(nèi)部與FSK數(shù)據(jù)引腳（引腳29）一致，但是， FSK數(shù)據(jù)信號(hào)與DAC輸出之間存在確定性的流水線延遲。（請(qǐng)參考表1中的流水線延遲。）該unramped FSK模式，如圖36所示，代表傳統(tǒng)的FSK，無(wú)線電電傳印字機(jī)（RTTY）或電傳（TTY的）的數(shù)字?jǐn)?shù)據(jù)傳輸。數(shù)字通信的FSK是一個(gè)非?？煽康氖侄?，但是，它的頻帶利用率不高。 Ramped的FSK，如圖37所示，是一個(gè)節(jié)約帶寬的方法。Ramped FSK (Mode 010) This mode is a method of FSK whereby changes from F1 to F2 are not instantaneous, but are accomplished in a frequency sweep or ramped fashion (the ramped notation implies that the sweep is linear). Although linear sweeping, or frequency ramping, is easily and automatically accomplished, it is only one of many schemes. Other frequency transition schemes can be implemented by changing the ramp rate and ramp step size on the fly in a piecewise fashion.Ramped的FSK（模式010）此模式是一種FSK的方法，即從F1到F2變化不是瞬間，而是在頻率掃描或ramped方式完成（即ramped符號(hào)意味著掃描是線性的）。雖然線性掃頻，或頻率斜坡，很容易和自動(dòng)完成，它只是眾多方案之一。其他頻率的掃頻，可以通過(guò)改變掃頻速率和掃頻步長(zhǎng)實(shí)現(xiàn)。Frequency ramping, whether linear or nonlinear, necessitates that many intermediate frequencies between F1 and F2 are output in addition to the primary F1 and F2 frequencies. Figure 37 and Figure 38 depict the frequency vs. time characteristics of a linear ramped FSK signal. 頻率掃描，無(wú)論是線性或非線性，必須是從F1 到F2除了F1和F2的中間頻率主頻率輸出。圖37和圖38描述了線性ramped FSK信號(hào)的頻率隨時(shí)間變化的特點(diǎn)。Note that in ramped FSK mode, the delta frequency word (DFW) is required to be programmed as a positive twos complement value. Another requirement is that the lowest frequency (F1) be programmed in the Frequency Tuning Word 1 register. 請(qǐng)注意，在ramped FSK模式，頻率變化字（DFW的）必須被編程為一個(gè)正的補(bǔ)碼值。另一個(gè)要求是最低的頻率（F1）寫入到頻率調(diào)諧字1寄存器。The purpose of ramped FSK is to provide better bandwidth containment than traditional FSK by replacing the instantaneous frequency changes with more gradual, user-defined frequency changes. The dwell time at F1 and F2 can be equal to or much greater than the time spent at each intermediate frequency. The user controls the dwell time at F1 and F2, the number of inter-mediate frequencies, and the time spent at each frequency. Unlike unramped FSK, ramped FSK requires the lowest frequency to be loaded into F1 registers and the highest frequency to be loaded into F2 registers.該ramped FSK的目的是利用逐步取代、用戶定義的頻率變化替代瞬時(shí)頻率變化，以提供更好的帶寬控制。在F1和F2的停留時(shí)間可等于或遠(yuǎn)大于在每個(gè)中間頻率所花費(fèi)的時(shí)間。用戶控制在F1和F2的駐留時(shí)間，中間頻率數(shù)量，并在每個(gè)中間頻率上的駐留時(shí)間。不像unramped FSK，ramped FSK要求最低頻率加載到F1寄存器，最高頻率加載到F2寄存器。Several registers must be programmed to instruct the DDS on the resolution of intermediate frequency steps (48 bits) and the time spent at each step (20 bits). Furthermore, the CLR ACC1 bit in the control register should be toggled (low-high-low) prior to operation to ensure that the frequency accumulator is starting from an all 0s output condition. For piecewise, nonlinear frequency transitions, it is necessary to reprogram the registers while the frequency transition is in progress to affect the desired response. 為了確定DDS中間頻率步進(jìn)值（48位）的分辨率和每一步駐留時(shí)間（20位），必須對(duì)幾個(gè)寄存器進(jìn)行編程。此外，在控制寄存器中的CLR ACC1位應(yīng)在操作前切換（低-高-低），以確保頻率累加器是從全0輸出狀態(tài)開(kāi)始。對(duì)于分段，非線性頻率轉(zhuǎn)換，當(dāng)頻率切換有可能影響到相位時(shí)，需要重新編程寄存器的頻