基于單片機(jī)的步進(jìn)電機(jī)電路控制設(shè)計(jì)英文文獻(xiàn)及翻譯

基于單片機(jī)的步進(jìn)電機(jī)電路控制設(shè)計(jì)英文文獻(xiàn)及翻譯THESTEPPERMOTORCONTROLCIRCUITBEBASEDONSINGLECHIPMICROCOMPUTERTHEAT89C51ISALOWPOWER,HIGHPERFORMANCECMOS8BITMICROCOMPUTERWITH4KBYTESOFFLASHPROGRAMMABLEANDERASABLEREADONLYMEMORYPEROMTHEDEVICEISMANUFACTUREDUSINGATMELSHIGHDENSITYNONVOLATILEMEMORYTECHNOLOGYANDISCOMPATIBLEWITHTHEINDUSTRYSTANDARDMCS51INSTRUCTIONSETANDPINOUTTHEONCHIPFLASHALLOWSTHEPROGRAMMEMORYTOBEREPROGRAMMEDINSYSTEMORBYACONVENTIONALNONVOLATILEMEMORYPROGRAMMERBYCOMBININGAVERSATILE8BITCPUWITHFLASHONAMONOLITHICCHIP,THEATMELAT89C51ISAPOWERFULMICROCOMPUTERWHICHPROVIDESAHIGHLYFLEXIBLEANDCOSTEFFECTIVESOLUTIONTOMANYEMBEDDEDCONTROLAPPLICATIONSFUNCTIONCHARACTERISTICTHEAT89C51PROVIDESTHEFOLLOWINGSTANDARDFEATURES4KBYTESOFFLASH,128BYTESOFRAM,32I/OLINES,TWO16BITTIMER/COUNTERS,AFIVEVECTORTWOLEVELINTERRUPTARCHITECTURE,AFULLDUPLEXSERIALPORT,ONCHIPOSCILLATORANDCLOCKCIRCUITRYINADDITION,THEAT89C51ISDESIGNEDWITHSTATICLOGICFOROPERATIONDOWNTOZEROFREQUENCYANDSUPPORTSTWOSOFTWARESELECTABLEPOWERSAVINGMODESTHEIDLEMODESTOPSTHECPUWHILEALLOWINGTHERAM,TIMER/COUNTERS,SERIALPORTANDINTERRUPTSYSTEMTOCONTINUEFUNCTIONINGTHEPOWERDOWNMODESAVESTHERAMCONTENTSBUTFREEZESTHEOSCILLATORDISABLINGALLOTHERCHIPFUNCTIONSUNTILTHENEXTHARDWARERESETPINDESCRIPTIONVCCSUPPLYVOLTAGEGNDGROUNDPORT0PORT0ISAN8BITOPENDRAINBIDIRECTIONALI/OPORTASANOUTPUTPORT,EACHPINCANSINKEIGHTTTLINPUTSWHEN1SAREWRITTENTOPORT0PINS,THEPINSCANBEUSEDASHIGHIMPEDANCEINPUTSPORT0MAYALSOBECONFIGUREDTOBETHEMULTIPLEXEDLOWORDERADDRESS/DATABUSDURINGACCESSESTOEXTERNALPROGRAMANDDATAMEMORYINTHISMODEP0HASINTERNALPULLUPSPORT0ALSORECEIVESTHECODEBYTESDURINGFLASHPROGRAMMING,ANDOUTPUTSTHECODEBYTESDURINGPROGRAMVERIFICATIONEXTERNALPULLUPSAREREQUIREDDURINGPROGRAMVERIFICATIONPORT1PORT1ISAN8BITBIDIRECTIONALI/OPORTWITHINTERNALPULLUPSTHEPORT1OUTPUTBUFFERSCANSINK/SOURCEFOURTTLINPUTSWHEN1SAREWRITTENTOPORT1PINSTHEYAREPULLEDHIGHBYTHEINTERNALPULLUPSANDCANBEUSEDASINPUTSASINPUTS,PORT1PINSTHATAREEXTERNALLYBEINGPULLEDLOWWILLSOURCECURRENTIILBECAUSEOFTHEINTERNALPULLUPSPORT1ALSORECEIVESTHELOWORDERADDRESSBYTESDURINGFLASHPROGRAMMINGANDVERIFICATIONPORT2PORT2ISAN8BITBIDIRECTIONALI/OPORTWITHINTERNALPULLUPSTHEPORT2OUTPUTBUFFERSCANSINK/SOURCEFOURTTLINPUTSWHEN1SAREWRITTENTOPORT2PINSTHEYAREPULLEDHIGHBYTHEINTERNALPULLUPSANDCANBEUSEDASINPUTSASINPUTS,PORT2PINSTHATAREEXTERNALLYBEINGPULLEDLOWWILLSOURCECURRENT,BECAUSEOFTHEINTERNALPULLUPSPORT2EMITSTHEHIGHORDERADDRESSBYTEDURINGFETCHESFROMEXTERNALPROGRAMMEMORYANDDURINGACCESSESTOEXTERNALDATAMEMORYTHATUSE16BITADDRESSESINTHISAPPLICATION,ITUSESSTRONGINTERNALPULLUPSWHENEMITTING1SDURINGACCESSESTOEXTERNALDATAMEMORYTHATUSE8BITADDRESSES,PORT2EMITSTHECONTENTSOFTHEP2SPECIALFUNCTIONREGISTERPORT2ALSORECEIVESTHEHIGHORDERADDRESSBITSANDSOMECONTROLSIGNALSDURINGFLASHPROGRAMMINGANDVERIFICATIONPORT3PORT3ISAN8BITBIDIRECTIONALI/OPORTWITHINTERNALPULLUPSTHEPORT3OUTPUTBUFFERSCANSINK/SOURCEFOURTTLINPUTSWHEN1SAREWRITTENTOPORT3PINSTHEYAREPULLEDHIGHBYTHEINTERNALPULLUPSANDCANBEUSEDASINPUTSASINPUTS,PORT3PINSTHATAREEXTERNALLYBEINGPULLEDLOWWILLSOURCECURRENTIILBECAUSEOFTHEPULLUPSPORT3ALSOSERVESTHEFUNCTIONSOFVARIOUSSPECIALFEATURESOFTHEAT89C51ASLISTEDBELOWPORT3ALSORECEIVESSOMECONTROLSIGNALSFORFLASHPROGRAMMINGANDVERIFICATIONRSTRESETINPUTAHIGHONTHISPINFORTWOMACHINECYCLESWHILETHEOSCILLATORISRUNNINGRESETSTHEDEVICEALE/PROGADDRESSLATCHENABLEOUTPUTPULSEFORLATCHINGTHELOWBYTEOFTHEADDRESSDURINGACCESSESTOEXTERNALMEMORYTHISPINISALSOTHEPROGRAMPULSEINPUTPROGDURINGFLASHPROGRAMMINGINNORMALOPERATIONALEISEMITTEDATACONSTANTRATEOF1/6THEOSCILLATORFREQUENCY,ANDMAYBEUSEDFOREXTERNALTIMINGORCLOCKINGPURPOSESNOTE,HOWEVER,THATONEALEPULSEISSKIPPEDDURINGEACHACCESSTOEXTERNALDATAMEMORYIFDESIRED,ALEOPERATIONCANBEDISABLEDBYSETTINGBIT0OFSFRLOCATION8EHWITHTHEBITSET,ALEISACTIVEONLYDURINGAMOVXORMOVCINSTRUCTIONOTHERWISE,THEPINISWEAKLYPULLEDHIGHSETTINGTHEALEDISABLEBITHASNOEFFECTIFTHEMICROCONTROLLERISINEXTERNALEXECUTIONMODEPSENPROGRAMSTOREENABLEISTHEREADSTROBETOEXTERNALPROGRAMMEMORYWHENTHEAT89C51ISEXECUTINGCODEFROMEXTERNALPROGRAMMEMORY,PSENISACTIVATEDTWICEEACHMACHINECYCLE,EXCEPTTHATTWOPSENACTIVATIONSARESKIPPEDDURINGEACHACCESSTOEXTERNALDATAMEMORYEA/VPPEXTERNALACCESSENABLEEAMUSTBESTRAPPEDTOGNDINORDERTOENABLETHEDEVICETOFETCHCODEFROMEXTERNALPROGRAMMEMORYLOCATIONSSTARTINGAT0000HUPTOFFFFHNOTE,HOWEVER,THATIFLOCKBIT1ISPROGRAMMED,EAWILLBEINTERNALLYLATCHEDONRESETEASHOULDBESTRAPPEDTOVCCFORINTERNALPROGRAMEXECUTIONSTHISPINALSORECEIVESTHE12VOLTPROGRAMMINGENABLEVOLTAGEVPPDURINGFLASHPROGRAMMING,FORPARTSTHATREQUIRE12VOLTVPPXTAL1INPUTTOTHEINVERTINGOSCILLATORAMPLIFIERANDINPUTTOTHEINTERNALCLOCKOPERATINGCIRCUITXTAL2OUTPUTFROMTHEINVERTINGOSCILLATORAMPLIFIEROSCILLATORCHARACTERISTICSXTAL1ANDXTAL2ARETHEINPUTANDOUTPUT,RESPECTIVELY,OFANINVERTINGAMPLIFIERWHICHCANBECONFIGUREDFORUSEASANONCHIPOSCILLATOR,ASSHOWNINFIGURE1EITHERAQUARTZCRYSTALORCERAMICRESONATORMAYBEUSEDTODRIVETHEDEVICEFROMANEXTERNALCLOCKSOURCE,XTAL2SHOULDBELEFTUNCONNECTEDWHILEXTAL1ISDRIVENASSHOWNINFIGURE2THEREARENOREQUIREMENTSONTHEDUTYCYCLEOFTHEEXTERNALCLOCKSIGNAL,SINCETHEINPUTTOTHEINTERNALCLOCKINGCIRCUITRYISTHROUGHADIVIDEBYTWOFLIPFLOP,BUTMINIMUMANDMAXIMUMVOLTAGEHIGHANDLOWTIMESPECIFICATIONSMUSTBEOBSERVEDFIGURE1OSCILLATORCONNECTIONSFIGURE2EXTERNALCLOCKDRIVECONFIGURATIONIDLEMODEINIDLEMODE,THECPUPUTSITSELFTOSLEEPWHILEALLTHEONCHIPPERIPHERALSREMAINACTIVETHEMODEISINVOKEDBYSOFTWARETHECONTENTOFTHEONCHIPRAMANDALLTHESPECIALFUNCTIONSREGISTERSREMAINUNCHANGEDDURINGTHISMODETHEIDLEMODECANBETERMINATEDBYANYENABLEDINTERRUPTORBYAHARDWARERESETITSHOULDBENOTEDTHATWHENIDLEISTERMINATEDBYAHARDWARERESET,THEDEVICENORMALLYRESUMESPROGRAMEXECUTION,FROMWHEREITLEFTOFF,UPTOTWOMACHINECYCLESBEFORETHEINTERNALRESETALGORITHMTAKESCONTROLONCHIPHARDWAREINHIBITSACCESSTOINTERNALRAMINTHISEVENT,BUTACCESSTOTHEPORTPINSISNOTINHIBITEDTOELIMINATETHEPOSSIBILITYOFANUNEXPECTEDWRITETOAPORTPINWHENIDLEISTERMINATEDBYRESET,THEINSTRUCTIONFOLLOWINGTHEONETHATINVOKESIDLESHOULDNOTBEONETHATWRITESTOAPORTPINORTOEXTERNALMEMORYPOWERDOWNMODEINTHEPOWERDOWNMODE,THEOSCILLATORISSTOPPED,ANDTHEINSTRUCTIONTHATINVOKESPOWERDOWNISTHELASTINSTRUCTIONEXECUTEDTHEONCHIPRAMANDSPECIALFUNCTIONREGISTERSRETAINTHEIRVALUESUNTILTHEPOWERDOWNMODEISTERMINATEDTHEONLYEXITFROMPOWERDOWNISAHARDWARERESETRESETREDEFINESTHESFRSBUTDOESNOTCHANGETHEONCHIPRAMTHERESETSHOULDNOTBEACTIVATEDBEFOREVCCISRESTOREDTOITSNORMALOPERATINGLEVELANDMUSTBEHELDACTIVELONGENOUGHTOALLOWTHEOSCILLATORTORESTARTANDSTABILIZEPROGRAMMEMORYLOCKBITSONTHECHIPARETHREELOCKBITSWHICHCANBELEFTUNPROGRAMMEDUORCANBEPROGRAMMEDPTOOBTAINTHEADDITIONALFEATURESLISTEDINTHETABLEBELOWWHENLOCKBIT1ISPROGRAMMED,THELOGICLEVELATTHEEAPINISSAMPLEDANDLATCHEDDURINGRESETIFTHEDEVICEISPOWEREDUPWITHOUTARESET,THELATCHINITIALIZESTOARANDOMVALUE,ANDHOLDSTHATVALUEUNTILRESETISACTIVATEDITISNECESSARYTHATTHELATCHEDVALUEOFEABEINAGREEMENTWITHTHECURRENTLOGICLEVELATTHATPININORDERFORTHEDEVICETOFUNCTIONPROPERLYINTRODUCTIONSTEPPERMOTORSAREELECTROMAGNETICINCREMENTALMOTIONDEVICESWHICHCONVERTDIGITALPULSEINPUTSTOANALOGANGLEOUTPUTSTHEIRINHERENTSTEPPINGABILITYALLOWSFORACCURATEPOSITIONCONTROLWITHOUTFEEDBACKTHATIS,THEYCANTRACKANYSTEPPOSITIONINOPENLOOPMODE,CONSEQUENTLYNOFEEDBACKISNEEDEDTOIMPLEMENTPOSITIONCONTROLSTEPPERMOTORSDELIVERHIGHERPEAKTORQUEPERUNITWEIGHTTHANDCMOTORSINADDITION,THEYAREBRUSHLESSMACHINESANDTHEREFOREREQUIRELESSMAINTENANCEALLOFTHESEPROPERTIESHAVEMADESTEPPERMOTORSAVERYATTRACTIVESELECTIONINMANYPOSITIONANDSPEEDCONTROLSYSTEMS,SUCHASINCOMPUTERHARDDISKDRIVERSANDPRINTERS,XYTABLES,ROBOTMANIPULATORS,ETCALTHOUGHSTEPPERMOTORSHAVEMANYSALIENTPROPERTIES,THEYSUFFERFROMANOSCILLATIONORUNSTABLEPHENOMENONTHISPHENOMENONSEVERELYRESTRICTSTHEIROPENLOOPDYNAMICPERFORMANCEANDAPPLICABLEAREAWHEREHIGHSPEEDOPERATIONISNEEDEDTHEOSCILLATIONUSUALLYOCCURSATSTEPPINGRATESLOWERTHAN1000PULSE/S,ANDHASBEENRECOGNIZEDASAMIDFREQUENCYINSTABILITYORLOCALINSTABILITY1,ORADYNAMICINSTABILITY2INADDITION,THEREISANOTHERKINDOFUNSTABLEPHENOMENONINSTEPPERMOTORS,THATIS,THEMOTORSUSUALLYLOSESYNCHRONISMATHIGHERSTEPPINGRATES,EVENTHOUGHLOADTORQUEISLESSTHANTHEIRPULLOUTTORQUETHISPHENOMENONISIDENTIFIEDASHIGHFREQUENCYINSTABILITYINTHISPAPER,BECAUSEITAPPEARSATMUCHHIGHERFREQUENCIESTHANTHEFREQUENCIESATWHICHTHEMIDFREQUENCYOSCILLATIONOCCURSTHEHIGHFREQUENCYINSTABILITYHASNOTBEENRECOGNIZEDASWIDELYASMIDFREQUENCYINSTABILITY,ANDTHEREISNOTYETAMETHODTOEVALUATEITMIDFREQUENCYOSCILLATIONHASBEENRECOGNIZEDWIDELYFORAVERYLONGTIME,HOWEVER,ACOMPLETEUNDERSTANDINGOFITHASNOTBEENWELLESTABLISHEDTHISCANBEATTRIBUTEDTOTHENONLINEARITYTHATDOMINATESTHEOSCILLATIONPHENOMENONANDISQUITEDIFFICULTTODEALWITH384LCAOANDHMSCHWARTZMOSTRESEARCHERSHAVEANALYZEDITBASEDONALINEARIZEDMODEL1ALTHOUGHINMANYCASES,THISKINDOFTREATMENTSISVALIDORUSEFUL,ATREATMENTBASEDONNONLINEARTHEORYISNEEDEDINORDERTOGIVEABETTERDESCRIPTIONONTHISCOMPLEXPHENOMENONFOREXAMPLE,BASEDONALINEARIZEDMODELONECANONLYSEETHATTHEMOTORSTURNTOBELOCALLYUNSTABLEATSOMESUPPLYFREQUENCIES,WHICHDOESNOTGIVEMUCHINSIGHTINTOTHEOBSERVEDOSCILLATORYPHENOMENONINFACT,THEOSCILLATIONCANNOTBEASSESSEDUNLESSONEUSESNONLINEARTHEORYTHEREFORE,ITISSIGNIFICANTTOUSEDEVELOPEDMATHEMATICALTHEORYONNONLINEARDYNAMICSTOHANDLETHEOSCILLATIONORINSTABILITYITISWORTHNOTINGTHATTAFTANDGAUTHIER3,ANDTAFTANDHARNED4USEDMATHEMATICALCONCEPTSSUCHASLIMITCYCLESANDSEPARATRICESINTHEANALYSISOFOSCILLATORYANDUNSTABLEPHENOMENA,ANDOBTAINEDSOMEVERYINSTRUCTIVEINSIGHTSINTOTHESOCALLEDLOSSOFSYNCHRONOUSPHENOMENONNEVERTHELESS,THEREISSTILLALACKOFACOMPREHENSIVEMATHEMATICALANALYSISINTHISKINDOFSTUDIESINTHISPAPERANOVELMATHEMATICALANALYSISISDEVELOPEDTOANALYZETHEOSCILLATIONSANDINSTABILITYINSTEPPERMOTORSTHEFIRSTPARTOFTHISPAPERDISCUSSESTHESTABILITYANALYSISOFSTEPPERMOTORSITISSHOWNTHATTHEMIDFREQUENCYOSCILLATIONCANBECHARACTERIZEDASABIFURCATIONPHENOMENONHOPFBIFURCATIONOFNONLINEARSYSTEMSONEOFCONTRIBUTIONSOFTHISPAPERISTORELATETHEMIDFREQUENCYOSCILLATIONTOHOPFBIFURCATION,THEREBY,THEEXISTENCEOFTHEOSCILLATIONISPROVEDTHEORETICALLYBYHOPFTHEORYHIGHFREQUENCYINSTABILITYISALSODISCUSSEDINDETAIL,ANDANOVELQUANTITYISINTRODUCEDTOEVALUATEHIGHFREQUENCYSTABILITYTHISQUANTITYISVERYEASYTOCALCULATE,ANDCANBEUSEDASACRITERIATOPREDICTTHEONSETOFTHEHIGHFREQUENCYINSTABILITYEXPERIMENTALRESULTSONAREALMOTORSHOWTHEEFFICIENCYOFTHISANALYTICALTOOLTHESECONDPARTOFTHISPAPERDISCUSSESSTABILIZINGCONTROLOFSTEPPERMOTORSTHROUGHFEEDBACKSEVERALAUTHORSHAVESHOWNTHATBYMODULATINGTHESUPPLYFREQUENCY5,THEMIDFREQUENCYINSTABILITYCANBEIMPROVEDINPARTICULAR,PICKUPANDRUSSELL6,7HAVEPRESENTEDADETAILEDANALYSISONTHEFREQUENCYMODULATIONMETHODINTHEIRANALYSIS,JACOBISERIESWASUSEDTOSOLVEAORDINARYDIFFERENTIALEQUATION,ANDASETOFNONLINEARALGEBRAICEQUATIONSHADTOBESOLVEDNUMERICALLYINADDITION,THEIRANALYSISISUNDERTAKENFORATWOPHASEMOTOR,ANDTHEREFORE,THEIRCONCLUSIONSCANNOTAPPLIEDDIRECTLYTOOURSITUATION,WHEREATHREEPHASEMOTORWILLBECONSIDEREDHERE,WEGIVEAMOREELEGANTANALYSISFORSTABILIZINGSTEPPERMOTORS,WHERENOCOMPLEXMATHEMATICALMANIPULATIONISNEEDEDINTHISANALYSIS,ADQMODELOFSTEPPERMOTORSISUSEDBECAUSETWOPHASEMOTORSANDTHREEPHASEMOTORSHAVETHESAMEQDMODELANDTHEREFORE,THEANALYSISISVALIDFORBOTHTWOPHASEANDTHREEPHASEMOTORSUPTODATE,ITISONLYRECOGNIZEDTHATTHEMODULATIONMETHODISNEEDEDTOSUPPRESSTHEMIDFREQUENCYOSCILLATIONINTHISPAPER,ITISSHOWNTHATTHISMETHODISNOTONLYVALIDTOIMPROVEMIDFREQUENCYSTABILITY,BUTALSOEFFECTIVETOIMPROVEHIGHFREQUENCYSTABILITY2DYNAMICMODELOFSTEPPERMOTORSTHESTEPPERMOTORCONSIDEREDINTHISPAPERCONSISTSOFASALIENTSTATORWITHTWOPHASEORTHREEPHASEWINDINGS,ANDAPERMANENTMAGNETROTORASIMPLIFIEDSCHEMATICOFATHREEPHASEMOTORWITHONEPOLEPAIRISSHOWNINFIGURE1THESTEPPERMOTORISUSUALLYFEDBYAVOLTAGESOURCEINVERTER,WHICHISCONTROLLEDBYASEQUENCEOFPULSESANDPRODUCESSQUAREWAVEVOLTAGESTHISMOTOROPERATESESSENTIALLYONTHESAMEPRINCIPLEASTHATOFSYNCHRONOUSMOTORSONEOFMAJOROPERATINGMANNERFORSTEPPERMOTORSISTHATSUPPLYINGVOLTAGEISKEPTCONSTANTANDFREQUENCYOFPULSESISCHANGEDATAVERYWIDERANGEUNDERTHISOPERATINGCONDITION,OSCILLATIONANDINSTABILITYPROBLEMSUSUALLYARISEFIGURE1SCHEMATICMODELOFATHREEPHASESTEPPERMOTORAMATHEMATICALMODELFORATHREEPHASESTEPPERMOTORISESTABLISHEDUSINGQDFRAMEREFERENCETRANSFORMATIONTHEVOLTAGEEQUATIONSFORTHREEPHASEWINDINGSAREGIVENBYVARIALDIA/DTMDIB/DTMDIC/DTDPMA/DT,VBRIBLDIB/DTMDIA/DTMDIC/DTDPMB/DT,VCRICLDIC/DTMDIA/DTMDIB/DTDPMC/DT,WHERERANDLARETHERESISTANCEANDINDUCTANCEOFTHEPHASEWINDINGS,ANDMISTHEMUTUALINDUCTANCEBETWEENTHEPHASEWINDINGS_PMA,_PMBAND_PMCARETHEFLUXLINKAGESOFTHEPHASESDUETOTHEPERMANENTMAGNET,ANDCANBEASSUMEDTOBESINUSOIDFUNCTIONSOFROTORPOSITION_ASFOLLOWPMA1SINN,PMB1SINN2/3,PMC1SINN2/3,WHERENISNUMBEROFROTORTEETHTHENONLINEARITYEMPHASIZEDINTHISPAPERISREPRESENTEDBYTHEABOVEEQUATIONS,THATIS,THEFLUXLINKAGESARENONLINEARFUNCTIONSOFTHEROTORPOSITIONBYUSINGTHEQDTRANSFORMATION,THEFRAMEOFREFERENCEISCHANGEDFROMTHEFIXEDPHASEAXESTOTHEAXESMOVINGWITHTHEROTORREFERTOFIGURE2TRANSFORMATIONMATRIXFROMTHEABCFRAMETOTHEQDFRAMEISGIVENBY8FOREXAMPLE,VOLTAGESINTHEQDREFERENCEAREGIVENBYINTHEABCREFERENCE,ONLYTWOVARIABLESAREINDEPENDENTIACIBCICD0THEREFORE,THEABOVETRANSFORMATIONFROMTHREEVARIABLESTOTWOVARIABLESISALLOWABLEAPPLYINGTHEABOVETRANSFORMATIONTOTHEVOLTAGEEQUATIONS1,THETRANSFERREDVOLTAGEEQUATIONINTHEQDFRAMECANBEOBTAINEDASVQRIQL1DIQ/DTNL1IDN1,VDRIDL1DID/DTNL1IQ,5FIGURE2A,B,CANDD,QREFERENCEFRAMEWHEREL1DLCM,ANDISTHESPEEDOFTHEROTORITCANBESHOWNTHATTHEMOTORSTORQUEHASTHEFOLLOWINGFORM2T3/2N1IQTHEEQUATIONOFMOTIONOFTHEROTORISWRITTENASJD/DT3/2N1IQBFTL,WHEREBFISTHECOEFFICIENTOFVISCOUSFRICTION,ANDTLREPRESENTSLOADTORQUE,WHICHISASSUMEDTOBEACONSTANTINTHISPAPERINORDERTOCONSTITUTETHECOMPLETESTATEEQUATIONOFTHEMOTOR,WENEEDANOTHERSTATEVARIABLETHATREPRESENTSTHEPOSITIONOFTHEROTORFORTHISPURPOSETHESOCALLEDLOADANGLE_8ISUSUALLYUSED,WHICHSATISFIESTHEFOLLOWINGEQUATIOND/DT0,WHERE0ISSTEADYSTATESPEEDOFTHEMOTOREQUATIONS5,7,AND8CONSTITUTETHESTATESPACEMODELOFTHEMOTOR,FORWHICHTHEINPUTVARIABLESARETHEVOLTAGESVQANDVDASMENTIONEDBEFORE,STEPPERMOTORSAREFEDBYANINVERTER,WHOSEOUTPUTVOLTAGESARENOTSINUSOIDALBUTINSTEADARESQUAREWAVESHOWEVER,BECAUSETHENONSINUSOIDALVOLTAGESDONOTCHANGETHEOSCILLATIONFEATUREANDINSTABILITYVERYMUCHIFCOMPAREDTOTHESINUSOIDALCASEASWILLBESHOWNINSECTION3,THEOSCILLATIONISDUETOTHENONLINEARITYOFTHEMOTOR,FORTHEPURPOSESOFTHISPAPERWECANASSUMETHESUPPLYVOLTAGESARESINUSOIDALUNDERTHISASSUMPTION,WECANGETVQANDVDASFOLLOWSVQVMCOSN,VDVMSINN,WHEREVMISTHEMAXIMUMOFTHESINEWAVEWITHTHEABOVEEQUATION,WEHAVECHANGEDTHEINPUTVOLTAGESFROMAFUNCTIONOFTIMETOAFUNCTIONOFSTATE,ANDINTHISWAYWECANREPRESENTTHEDYNAMICSOFTHEMOTORBYAAUTONOMOUSSYSTEM,ASSHOWNBELOWTHISWILLSIMPLIFYTHEMATHEMATICALANALYSISFROMEQUATIONS5,7,AND8,THESTATESPACEMODELOFTHEMOTORCANBEWRITTENINAMATRIXFORMASFOLLOWSFX,UAXFNXBU,10WHEREXDTIQID_UT,UDT1TLUTISDEFINEDASTHEINPUT,AND1DN0ISTHESUPPLYFREQUENCYTHEINPUTMATRIXBISDEFINEDBYTHEMATRIXAISTHELINEARPARTOFF_/,ANDISGIVENBYFNX/REPRESENTSTHENONLINEARPARTOFF_/,ANDISGIVENBYTHEINPUTTERMUISINDEPENDENTOFTIME,ANDTHEREFOREEQUATION10ISAUTONOMOUSTHEREARETHREEPARAMETERSINFXU/,THEYARETHESUPPLYFREQUENCY1,THESUPPLYVOLTAGEMAGNITUDEVMANDTHELOADTORQUETLTHESEPARAMETERSGOVERNTHEBEHAVIOUROFTHESTEPPERMOTORINPRACTICE,STEPPERMOTORSAREUSUALLYDRIVENINSUCHAWAYTHATTHESUPPLYFREQUENCY1ISCHANGEDBYTHECOMMANDPULSETOCONTROLTHEMOTORSSPEED,WHILETHESUPPLYVOLTAGEISKEPTCONSTANTTHEREFORE,WESHALLINVESTIGATETHEEFFECTOFPARAMETER13BIFURCATIONANDMIDFREQUENCYOSCILLATIONBYSETTINGD0,THEEQUILIBRIAOFEQUATION10AREGIVENASANDISITSPHASEANGLEDEFINEDBYARCTAN1L1/R16EQUATIONS12AND13INDICATETHATMULTIPLEEQUILIBRIAEXIST,WHICHMEANSTHATTHESEEQUILIBRIACANNEVERBEGLOBALLYSTABLEONECANSEETHATTHEREARETWOGROUPSOFEQUILIBRIAASSHOWNINEQUATIONS12AND13THEFIRSTGROUPREPRESENTEDBYEQUATION12CORRESPONDSTOTHEREALOPERATINGCONDITIONSOFTHEMOTORTHESECONDGROUPREPRESENTEDBYEQUATION13ISALWAYSUNSTABLEANDDOESNOTRELATETOTHEREALOPERATINGCONDITIONSINTHEFOLLOWING,WEWILLCONCENTRATEONTHEEQUILIBRIAREPRESENTEDBYEQUATION12基于單片機(jī)的步進(jìn)電機(jī)電路控制設(shè)計(jì)89C51是一種帶4K字節(jié)閃爍可編程可擦除只讀存儲(chǔ)器（FPEROMFALSHPROGRAMMABLEANDERASABLEREADONLYMEMORY）的低電壓、高性能CMOS8位微處理器，俗稱單片機(jī)。該器件采用ATMEL高密度非易失存儲(chǔ)器制造技術(shù)制造，與工業(yè)標(biāo)準(zhǔn)的MCS51指令集和輸出管腳相兼容。由于將多功能8位CPU和閃爍存儲(chǔ)器組合在單個(gè)芯片中，ATMEL的89C51是一種高效微控制器，89C2051是它的一種精簡(jiǎn)版本。89C單片機(jī)為很多嵌入式控制系統(tǒng)提供了一種靈活性高且價(jià)廉的方案。功能特點(diǎn)與MCS51兼容4K字節(jié)可編程閃爍存儲(chǔ)器壽命1000寫/擦循環(huán)數(shù)據(jù)保留時(shí)間10年全靜態(tài)工作0HZ24MHZ三級(jí)程序存儲(chǔ)器鎖定1288位內(nèi)部RAM32可編程I/O線兩個(gè)16位定時(shí)器/計(jì)數(shù)器5個(gè)中斷源可編程串行通道低功耗的閑置和掉電模式片內(nèi)振蕩器和時(shí)鐘電路管腳說(shuō)明VCC供電電壓。GND接地。P0口P0口為一個(gè)8位漏級(jí)開路雙向I/O口，每腳可吸收8TTL門電流。當(dāng)P1口的管腳第一次寫1時(shí)，被定義為高阻輸入。P0能夠用于外部程序數(shù)據(jù)存儲(chǔ)器，它可以被定義為數(shù)據(jù)/地址的低八位。在FIASH編程時(shí)，P0口作為原碼輸入口，當(dāng)FIASH進(jìn)行校驗(yàn)時(shí)，P0輸出原碼，此時(shí)P0外部必須被拉高。P1口P1口是一個(gè)內(nèi)部提供上拉電阻的8位雙向I/O口，P1口緩沖器能接收輸出4TTL門電流。P1口管腳寫入1后，被內(nèi)部上拉為高，可用作輸入，P1口被外部下拉為低電平時(shí)，將輸出電流，這是由于內(nèi)部上拉的緣故。在FLASH編程和校驗(yàn)時(shí)，P1口作為第八位地址接收。P2口P2口為一個(gè)內(nèi)部上拉電阻的8位雙向I/O口，P2口緩沖器可接收，輸出4個(gè)TTL門電流，當(dāng)P2口被寫1時(shí)，其管腳被內(nèi)部上拉電阻拉高，且作為輸入。并因此作為輸入時(shí)，P2口的管腳被外部拉低，將輸出電流。這是由于內(nèi)部上拉的緣故。P2口當(dāng)用于外部程序存儲(chǔ)器或16位地址外部數(shù)據(jù)存儲(chǔ)器進(jìn)行存取時(shí)，P2口輸出地址的高八位。在給出地址1時(shí)，它利用內(nèi)部上拉優(yōu)勢(shì)，當(dāng)對(duì)外部八位地址數(shù)據(jù)存儲(chǔ)器進(jìn)行讀寫時(shí)，P2口輸出其特殊功能寄存器的內(nèi)容。P2口在FLASH編程和校驗(yàn)時(shí)接收高八位地址信號(hào)和控制信號(hào)。P3口P3口管腳是8個(gè)帶內(nèi)部上拉電阻的雙向I/O口，可接收輸出4個(gè)TTL門電流。當(dāng)P3口寫入1后，它們被內(nèi)部上拉為高電平，并用作輸入。作為輸入，由于外部下拉為低電平，P3口將輸出電流（ILL）這是由于上拉的緣故。P3口也可作為AT89C51的一些特殊功能口口管腳備選功能P30RXD（串行輸入口）P31TXD（串行輸出口）P32/INT0（外部中斷0）P33/INT1（外部中斷1）P34T0（記時(shí)器0外部輸入）P35T1（記時(shí)器1外部輸入）P36/WR（外部數(shù)據(jù)存儲(chǔ)器寫選通）P37/RD（外部數(shù)據(jù)存儲(chǔ)器讀選通）P3口同時(shí)為閃爍編程和編程校驗(yàn)接收一些控制信號(hào)。RST復(fù)位輸入。當(dāng)振蕩器復(fù)位器件時(shí)，要保持RST腳兩個(gè)機(jī)器周期的高電平時(shí)間。ALE/PROG當(dāng)訪問(wèn)外部存儲(chǔ)器時(shí)，地址鎖存允許的輸出電平用于鎖存地址的地位字節(jié)。在FLASH編程期間，此引腳用于輸入編程脈沖。在平時(shí)，ALE端以不變的頻率周期輸出正脈沖信號(hào)，此頻率為振蕩器頻率的1/6。因此它可用作對(duì)外部輸出的脈沖或用于定時(shí)目的。然而要注意的是每當(dāng)用作外部數(shù)據(jù)存儲(chǔ)器時(shí)，將跳過(guò)一個(gè)ALE脈沖。如想禁止ALE的輸出可在SFR8EH地址上置0。此時(shí)，ALE只有在執(zhí)行MOVX，MOVC指令是ALE才起作用。另外，該引腳被略微拉高。如果微處理器在外部執(zhí)行狀態(tài)ALE禁止，置位無(wú)效。/PSEN外部程序存儲(chǔ)器的選通信號(hào)。在由外部程序存儲(chǔ)器取指期間，每個(gè)機(jī)器周期兩次/PSEN有效。但在訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器時(shí)，這兩次有效的/PSEN信號(hào)將不出現(xiàn)。/EA/VPP當(dāng)/EA保持低電平時(shí)，則在此期間外部程序存儲(chǔ)器（0000HFFFFH），不管是否有內(nèi)部程序存儲(chǔ)器。注意加密方式1時(shí)，/EA將內(nèi)部鎖定為RESET；當(dāng)/EA端保持高電平時(shí)，此間內(nèi)部程序存儲(chǔ)器。在FLASH編程期間，此引腳也用于施加12V編程電源（VPP）。XTAL1反向振蕩放大器的輸入及內(nèi)部時(shí)鐘工作電路的輸入。XTAL2來(lái)自反向振蕩器的輸出。振蕩器特性XTAL1和XTAL2分別為反向放大器的輸入和輸出。該反向放大器可以配置為片內(nèi)振蕩器。石晶振蕩和陶瓷振蕩均可采用。如采用外部時(shí)鐘源驅(qū)動(dòng)器件，XTAL2應(yīng)不接。由于輸入至內(nèi)部時(shí)鐘信號(hào)要通過(guò)一個(gè)二分頻觸發(fā)器，因此對(duì)外部時(shí)鐘信號(hào)的脈寬無(wú)任何要求，但必須保證脈沖的高低電平要求的寬度。FIGURE1OSCILLATORCONNECTIONSFIGURE2EXTERNALCLOCKDRIVE芯片擦除整個(gè)PEROM陣列和三個(gè)鎖定位的電擦除可通過(guò)正確的控制信號(hào)組合，并保持ALE管腳處于低電平10MS來(lái)完成。在芯片擦操作中，代碼陣列全被寫1且在任何非空存儲(chǔ)字節(jié)被重復(fù)編程以前，該操作必須被執(zhí)行。此外，AT89C51設(shè)有穩(wěn)態(tài)邏輯，可以在低到零頻率的條件下靜態(tài)邏輯，支持兩種軟件可選的掉電模式。在閑置模式下，CPU停止工作。但RAM，定時(shí)器，計(jì)數(shù)器，串口和中斷系統(tǒng)仍在工作。在掉電模式下，保存RAM的內(nèi)容并且凍結(jié)振蕩器，禁止所用其他芯片功能，直到下一個(gè)硬件復(fù)位為止?？臻e模式在空閑模式下,中央處理器把自己睡所有的微外設(shè)保持活躍。該模式調(diào)用的軟件。片上的內(nèi)容的公綿羊、所有的特殊功能寄存器不變?cè)谶@個(gè)模式下?？臻e模式可以終止任何使中斷或由硬件復(fù)位。應(yīng)該指出的是,閑時(shí)終止一個(gè)硬件復(fù)位,設(shè)備通常程序執(zhí)行,從簡(jiǎn)歷在它停止兩封,機(jī)器周期之前,內(nèi)部重置算法以控制。樣品的硬件抑制進(jìn)入內(nèi)部RAM在這種情況下,但進(jìn)入港口大頭針空洞。消除這種可能性一個(gè)出乎意料的寫信給一個(gè)港口銷閑時(shí)被終止,由復(fù)位、指導(dǎo)證明那個(gè)中調(diào)用一個(gè)空閑不應(yīng)該寫端口銷或外部存儲(chǔ)器。POWERDOWN模式在POWERDOWN模式下,振子是結(jié)束了,但這個(gè)指令用它召喚“POWERDOWN是最后的指令執(zhí)行。這片上的公綿羊、特殊功能寄存器值,直到POWERDOWN保留自己的方式終止。唯一的退出,是一家五金POWERDOWN重置。SFRS重置重新定義,但不改變樣品的公羊。重置不應(yīng)該被激活之前VCC回到正常操作水平,都必須保持活躍的時(shí)間還不夠久,允許振