模擬舞臺(tái)燈光控制系統(tǒng)軟硬件設(shè)計(jì)文件tlc5628_h

1、TLC5628C, TLC5628I OCTAL8-BITDIGITAL-TO-ANALOGCONVERTERSSLAS089E NOVEMBER 1994 REVISED APRIL 1997 Eight 8-Bit Voltage Output DACs 5-V Single-Supply Operation Serial InterfaceN OR DW PACKAGE (TOP VIEW)POST OFFICE BOX 655303 DALLAS, TEXAS 752651 High-Impedance Reference Inputs Programmable 1 or 2 Time

2、s Output Range Simultaneous Update Facility Internal Power-On Reset Low-Power Consumption Half-Buffered Outputapplications Programmable Voltage Sources Digitally Controlled Amplifiers/Attenuators Mobile Communications Automatic Test Equipment Process Monitoring and Control Signal Synthesisdescriptio

3、nDACB1DACA2GND3DATA4CLK5VDD6DACE7DACF816 DACC15 DACD14 REF113 LDAC12 LOAD11 REF210 DACH9 DACGThe TLC5628C and TLC5628I are octal 8-bit voltage output digital-to-analog converters (DACs) with buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either one

4、 or two times the reference voltages and GND and are monotonic. The device is simple to use, running from a single supply of 5 V. A power-on reset function is incorporated to ensure repeatable start-up conditions.Digital control of the TLC5628C and TLC5628I are over a simple three-wire serial bus th

5、at is CMOS compatible and easily interfaced to all popular microprocessor and microcontroller devices. The 12-bit command word comprises eight bits of data, three DAC select bits, and a range bit, the latter allowing selection between the times 1 or times 2 output range. The DAC registers are double

6、 buffered, allowing a complete set of new values to be written to the device, then all DAC outputs are updated simultaneously through control of LDAC. The digital inputs feature Schmitt triggers for high-noise immunity.The 16-terminal small-outline (D) package allows digital control of analog functi

7、ons pace-critical applications. The TLC5628C is characterized for operation from 0C to 70C. The TLC5628I is characterized for operation from 40C to 85C. The TLC5628C and TLC5628I do not require external trimming.AVAILABLE OPTIONSPACKAGETASMALL OUTLINE (DW)PLASTIC DIP (N)0C to 70CTLC5628CDWTLC5628CN4

8、0C to 85CTLC5628IDWTLC5628INPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas truments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of public

9、ation date.Products conform to specifications per the terms of Texas ruments standardwarranty.Productionprocessingdoesnotnecessarilyinclude testing of allparameters.Copyright 1997, Texastruments IncorporatedTLC5628C, TLC5628I OCTAL8-BITDIGITAL-TO-ANALOGCONVERTERSSLAS089E NOVEMBER 1994 REVISED APRIL

10、1997functional block diagramREF1 14+9LatchLatchDAC8 2+2 DACAPOST OFFICE BOX 655303 DALLAS, TEXAS 752651REF2 11 +LatchLatchDAC8 2+15 DACDLatch LatchDAC8 2+7 DACELatchLatchDAC8 2+10DACHCLK 5DATA 4LOAD 12Serial Interface13LDACPower-On ResetTerminal FunctionsTERMINALNAMENO.I/ODESCRIPTIONCLK5ISerial inte

11、rface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock applied to the CLK terminal.DACA2ODAC A analog outputDACB1ODAC B analog outputDACC16ODAC C analog outputDACD15ODAC D analog outputDACE7ODAC E analog outputDACF8ODAC F analog outputDACG9

12、ODAC G analog outputDACH10ODAC H analog outputDATA4ISerial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially. Each data bit is clocked into the register on the falling edge of the clock signal.GND3IGround return and reference terminalLD

13、AC13ILoad DAC. When LDAC is high, no DAC output updates occur when the input digital data is read into the serial interface. The DAC outputs are only updated when LDAC is taken from high to low.LOAD12ISerial interface load control. When LDAC is low, the falling edge of the LOAD signal latches the di

14、gital data into the output latch and immediately produces the analog voltage at the DAC output terminal.REF114IReference voltage input to DAC ABCD. This voltage defines the analog output range.REF211IReference voltage input to DAC EFGH. This voltage defines the analog output range.VDD6IPositive supp

15、ly voltageTLC5628C, TLC5628I OCTAL8-BITDIGITAL-TO-ANALOGCONVERTERSSLAS089E NOVEMBER 1994 REVISED APRIL 1997detailed descriptionThe TLC5628 is implemented using eight resistor-string DACs. The core of each DAC is a single resistor with 256 taps, corresponding to the 256 possible codes listed in Table

16、 1. One end of each resistor string is connected to GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use of the resistor strings. Linearity depends upon the matching of the resistor segments and upon the performance of the output buffer. Since

17、 the inputs are buffered, the DACs always present a high-impedance load to the reference sources. There are two input reference terminals; REF1 is used for DACA through DACD and REF2 is used by DACE through DACH.Each DAC output is buffered by a configurable-gain output amplifier, that can be program

18、med to times 1 or times 2 gain.On power up, the DACs are reset to CODE 0. Each output voltage is given by:V (DACA|B|C|D|E|F|G|H) = REF X CODE X (1 -t- RNG bit value)O256where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word.Table 1. Ideal Output Transf

19、erD7D6D5D4D3D2D1D0OUTPUT VOLTAGE00000000GND00000001(1/256) REF (1+RNG)01111111(127/256) REF (1+RNG)10000000(128/256) REF (1+RNG)11111111(255/256) REF (1+RNG)data interfaceWith LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have been clocked in, LOAD

20、 is pulsed low to transfer the data from the serial input register to the selected DAC as shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low. When LDAC is high during serial programming, the new value is stored within the device and can be transferred

21、to the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered most significant bit (MSB) first. Data transfers using two 8-clock cycle periods are shown in Figures 3 and 4.tsu(DATA-CLK) tv(DATA-CLK)tsu(LOAD-CLK)A2A1A0RNGD7D6D5D4D2D1D0tsu(CLK-LOAD)tw(LOAD)CLKDATAPOST OFF

22、ICE BOX 655303 DALLAS, TEXAS 7526511LOADFigure 1. LOAD-Controlled Update (LDAC = Low)DAC Updatedata interface (continued)tsu(DATA-CLK) tv(DATA-CLK)A2A1A0RNGD7D6D5D4D2D1D0tsu(LOAD LDAC)tw(LDAC)CLKDATALOADLDACCLKA2A1A0RNGD7D6D5D4D3D2D1D0DATALOAD LDACFigure 2. LDAC-Controlled UpdateCLK LowFigure 3. Loa

23、d-Controlled Update Using 8-Bit Serial Word (LDAC = Low)DAC UpdateCLKDATALOAD LDACCLK LowA2A1A0RNGD7D6D5D4D3D2D1D0Figure 4. LDAC-Controlled Update Using 8-Bit Serial WordTable 2 lists the A2, A1, and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output range. When RNG =

24、 low, the output range is between the applied reference voltage and GND, and when RNG = high, the range is between twice the applied reference voltage and GND.Table 2. Serial Input DecodeA2A1A0DAC UPDATED000DACA001DACB010DACC011DACD100DACE101DACF110DACG111DACHlinearity, offset, and gain error using

25、single-end suppliesWhen an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset voltage, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depend

26、ing on the magnitude of the offsetvoltage.The output amplifier, therefore, attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground.DAC CodeThe output voltage rema at 0 V until the input code value produces a s

27、ufficient output voltage to overcome the inherent negative offset voltage, resulting in the transfer function shown in Figure 5.Output Voltage0 VNegativeOffsetFigure 5. Effect of Negative Offset (Single Supply)This offset error, not the linearity error, produces the breakpoint. The transfer function

28、 would have followed the dotted line if the output buffer could drive below ground.For a DAC, linearity is measured between the zero-input code (all inputs are 0) and the full-scale code (all inputs are 1) after offset and full scale are adjusted out or accounted for ome way. However, single-supply

29、operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity in the unipolar mode is measured between full-scale code and the lowest code that produces a positive output voltage.The code is calculated from the maximum specificat

30、ion for the negative offset voltage.equivalent of inputs and outputsINPUT CIRCUITOUTPUT CIRCUITVDDDACVoltage OutputISINK 60 mATypical GNDVDDInput from_Vref InputDecoded DAC Register String + 1To DACResistor StringOutput84 kWRange 2 Select84 kWGNDabsolute maximum ratings over operating free-air tempe

31、rature range (unless otherwise noted)Supply voltage (VDD GND)VDigital input voltage range, VIDGND 0.3 V to VDD + 0.3 VReference input voltage rangeGND 0.3 V to VDD + 0.3 VOperating free-air temperature range, TA: TLC5628C0C to 70CTLC5628I40C to 85CStorage temperature range, Tstg50C to 150CLead tempe

32、rature 1,6 mm (1/16 inch) from case for10 seconds260C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommend

33、ed operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.recommended operating conditionsMINNOMMAXUNITSupply voltage, VDD4.755.25VHigh-level voltage, VIH0.8 VDDVLow-level voltage, VIL0.8VReference voltage, Vref A|B|C|D|

34、E|F|G|HVDD 1.5VAnalog full-scale output voltage, RL = 10 kW3.5VLoad resistance, RL10kWSetup time, data input, tsu(DATA-CLK) (see Figures 1 and 2)50nsValid time, data input valid after CLK, tv(DATA-CLK) (see Figures 1 and 2)50nsSetup time, CLK eleventh falling edge to LOAD, tsu(CLK-LOAD) (see Figure

35、1)50nsSetup time, LOAD to CLK, tsu(LOAD-CLK) (see Figure 1)50nsPulse duration, LOAD, tw(LOAD) (see Figure 1)250nsPulse duration, LDAC, tw(LDAC) (see Figure 2)250nsSetup time, LOAD to LDAC, tsu(LOAD-LDAC) (see Figure 2)0nsCLK frequency1MHzOperating free-air temperature, TATLC5628C070CTLC5628I4085Cele

36、ctrical characteristics over recommended operating free-air temperature range, VDD = 5 V 5%, Vref = 2 V, 1 gain output range (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPMAXUNITIIHHigh-level input currentVI = VDD 10mAIILLow-level input currentVI = 0 V 10mAIO(sink)Output sink currentEach DAC

37、 output20mAIO(source)Output source current2mACiInput capacitance15pFReference input capacitance15IDDSupply currentVDD = 5 V4mAIrefReference input currentVDD = 5 V,Vref = 2 V 10mAELLinearity error (end point corrected)Vref = 2 V, 2 gaee Note 1) 1LSBEDDifferential-linearity errorVref = 2 V, 2 gaee Not

38、e 2) 0.9LSBEZSZero-scale errorVref = 2 V, 2 gaee Note 3)030mVZero-scale-error temperature coefficientVref = 2 V, 2 gaee Note 4)10mV/CEFSFull-scale errorVref = 2 V, 2 gaee Note 5) 60mVFull-scale-error temperature coefficientVref = 2 V, 2 gaee Note 6) 25mV/CPSRRPower supply rejection ratioSee Notes 7

39、and 80.5mV/VNOTES: 1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full-scale errors).2. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of

40、any two adjacent codes. Monotonic means the output voltage changes in the same direction (or rema constant) as a change in the digital input code.3. Zero-scale error is the deviation from zero voltage output when the digital input code iszero.4. Zero-scale-error temperature coefficient is given by:

41、ZSETC =ZSE(Tmax) ZSE(Tmin)/Vref 106/(Tmax Tmin).5. Full-scale error is the deviation from the ideal full-scale output (Vref 1 LSB) with an output load of 10 kW.6. Full-scale error temperature coefficient is given by: FSETC = FSE(Tmax) FSE (Tmin)/Vref 106/(Tmax Tmin).7. Zero-scale-error rejection rat

42、io (ZSE RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the zero-code output voltage.8. Full-scale-error rejection ratio (FSE RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed

43、 on the full-scale output voltage.operating characteristics over recommended operating free-air temperature range, VDD = 5 V 5%, Vref = 2 V, 1 gain output range (unless otherwise noted)TEST CONDITIONSMINTYPMAXUNITOutput slew rateCL = 100 pF,RL = 10 kW1V/msOutput settling timeTo 0.5 LSB,CL = 100 pF,

44、RL = 10 kW,See Note 910msLarge signal bandwidthMeasured at 3 dB point100kHzDigital crosstalkCLK = 1-MHz square wave measured at DACA-DACD50dBReference feedthroughSee Note 1060dBChannel-to-channel isolationSee Note 1160dBReference input bandwidthSee Note 12100kHzNOTES: 9. Settling time is the time be

45、tween a LOAD falling edge and the DAC output reaching full-scale voltage within 0.5 LSB starting from an initial output voltage equal to zero.10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1 V dc + 1 Vpp at 10 kHz.11. Channel-to-channel isolat

46、ion is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hexwith Vref input = 1 V dc + 1 Vpp at 10 kHz.12. Reference bandwidth is the 3 dB bandwidth with an input at Vref = 1.25 V dc + 2 Vpp and with a full-scale digital input code.10 kWTLC5628DACA DACBDACH

47、PARAMETER MEASUREMENT INFORMATIONCL = 100 pFFigure 6. Slew, Settling Time, and Linearity MeasurementsTYPICAL CHARACTERISTICSPOSITIVE RISE AND SETTLING TIMENEGATIVE FALL AND SETTLING TIMELDACVDD = 5 V TA = 25CCode 00 to FF HexRange = 2 Vref = 2 VLDACVDD = 5 V TA = 25CCode FF to 00 HexRange = 2 Vref =

48、 2 V66VO Output Voltage VVO Output Voltage V442200024681012141618t Time msFigure 7024681012141618t Time msFigure 8TYPICAL CHARACTERISTICS54.8VO DAC Output Voltage V3.23DAC OUTPUT VOLTAGEVDD = 5 V, Vref = 2.5 V, Range = 2xvs OUTPUT LOAD4VO DAC Output Voltage V3.532.521.510.50DAC OU

49、TPUT VOLTAGEvs OUTPUT LOADVDD = 5 V, Vref = 3.5 V, Range = 1x010 20 30 40 50 60 70 80 90 10001020 30405060708090 100RL Output Load kWRL Output Load kWFigure 9Figure 10OUTPUT SOURCE CURRENTvs OUTPUT VOLTAGEVDD = 5 V TA = 25CVref = 2 VRange = 2 Input Code = 2558IO(source) Output Source Current mA76543

50、2101.21.15IDD Supply Current mA1.11.0510.950.90.850.8SUPPLY CURRENTvs TEMPERATURERange = 2 Input Code = 255VDD = 5 VVref = 2V012345VO Output Voltage V 50050100t Temperature CFigure 11Figure 12TYPICAL CHARACTERISTICSRELATIVE GAINvs FREQUENCYVDD = 5 V TA = 25CVref = 1.25 Vdc + 2 Vpp Input Code = 2550RELATIVE GAINvs FREQUENCYVDD = 5 V TA = 25CVref = 2 Vdc + 0.5 Vpp Input Code = 2551024G Relative G