PLL PCB布局法則

1、Board Layout Practices for SynthesizersThe newest generation of Hittite synthesizers have exceptionally good spur performance. In order to achieve these results, though, isolation on the PCB is a particular concern. On one of the integrated PLL+VCO products, by only modifying PCB component placement

2、 and isolation structures, the worst-case integer boundary spurs were reduced from -45 to - 60dBc ( 2 GHz).While there are some general guidelines that can be applied, often times its very minor details that can create a dominant coupling path on the board.Isolate any high power RF energy from the s

3、ynthesizer.- This includes VCO power, ground and signal path (VCO input signal only requires -10dBm)- The loop-filter ground, charge-pump and reference paths are particularly sensitive to RF coupling- The charge-pump and VCO should have separate supply regulation. If this is not possible, isolate he

4、avily with RF choke and resistance where possible.- In the PLL+VCO products, it has been seen that the AC ground of the RF output matching network coupling to the loop-filter ground create problems.Treat the loop filter very carefully-The first capacitor on the output of the charge-pump must be as c

5、lose-as-possible to the device ( 2mm). The inductance of the capacitors package should be minimized. Inductance from the CP output pin, through the capacitor, to paddle ground should be minimized. Keep this capacitor as large as the loop dynamics permit, while keeping it in a small package. Greater

6、than 500pF is recommended if possible.- The roofing filter (LPF RC sections) can be an unexpected problem. Based on where the capacitors connect to the ground plane, they may pick noise and spurs, rather than filter it out. A 6dB improvement in far-out spurs has been observed by moving the ground co

7、nnection of the final stage roofing capacitor about 4mm further from the reference path (it was picking up reference from the trace and delivering it direct to Vtune). If the far out spurs are rolling off at only 20dB/dec (1/s from the VCO) rather than 40dB/dec (loop-filter response), this is a sign

8、 that the coupling path is bypassing the PLL.Protect the reference- Generally the reference has been observed to be a victim (picking up noise & spurs) rather than an aggressor (inflicting spurs elsewhere on the PLL).- Shield the reference trace very heavily!- XTAL Termination may be necessary near

9、the PLL to clean up reflections. Be sure to include a place-holder on the PCB for a termination resistor.- In one case, the normally static SPI control lines were acting as a medium from the reference path to the loop filter dominating the spuriousperformance. This was an example of what seemed like

10、 a minor detail dominating performance.Heavily decouple the digital- Be careful to keep the digital supply away from the reference signal/supplies as much as possible.Use a reduced DVDD Supply Voltage- Reducing the digital supply voltage, DVDD if a reduced maximum fractional PFD rate is acceptable.

11、The maximum PFD rate is 70MHz (DSM Feedforward)/100MHz (DSM Feedback) at 3V DVDD. With 2.7V DVDD these rates scale back to 63MHz/90MHz3.3VVery near PLL2.7V DVDD DVDD- The digital power supply decoupling should be wideband and close to the part.- Turn off the SCK when not reading/writing. Do not use the GPO to drive active signals during normal