杭電計(jì)組實(shí)驗(yàn) 實(shí)現(xiàn)R型指令的CPU設(shè)計(jì)實(shí)驗(yàn)

1、 杭電計(jì)組實(shí)驗(yàn)-實(shí)現(xiàn)R型指令的CPU設(shè)計(jì)實(shí)驗(yàn) 作者： 日期： 2 實(shí)驗(yàn)報(bào) 成績(jī) 2018 61 日 姓陽(yáng)光學(xué)16041321班16052317計(jì)算機(jī)組成原理與系統(tǒng)結(jié)構(gòu)課程名專(zhuān)計(jì)算機(jī)科學(xué)與技驗(yàn)指導(dǎo)機(jī)位張翔老張翔老任課老實(shí)驗(yàn)實(shí)驗(yàn)實(shí)實(shí)驗(yàn)序型指令8CP設(shè)計(jì)實(shí)驗(yàn)實(shí)驗(yàn)設(shè)實(shí)驗(yàn)225實(shí)驗(yàn)時(shí)2018/5/25個(gè)人電 一、實(shí)驗(yàn)程序源代頂LE測(cè)試模塊module Top_LED(clk,rst,SW,LED);input clk,rst;input 2:0SW;output reg7:0LED;wire ZF,OF;wire 31:0ALU_F;top_R_cpu test_cpu(rst,clk,ZF,OF,AL

2、U_F);always(*)begincase(SW)3b000:LED=ALU_F7:0;3b001:LED=ALU_F15:8;3b010:LED=ALU_F23:16;3b011:LED=ALU_F31:24;3b100:begin LED7:2=0;LED1=OF;LED0=ZF;enddefault:LED=0;endcaseend 1 endmodule CPU模塊：頂層Rmodule top_R_cpu(input rst,input clk,output ZF,output OF,output 31:0F);reg write_reg;wire 31:0Inst_code;wi

3、re 31:0R_Data_A;wire 31:0R_Data_B;reg 2:0ALU_OP;pc pc_connect(clk,rst,Inst_code);Register_file R_connect(Inst_code25:21,Inst_code20:16,Inst_code15:11,write_reg,F,clk,rst,R_Data_A,R_Data_B);,ZF,OF);ALU ALU_connect(R_Data_A,R_Data_B,F,ALU_Oalways(*)beginwrite_reg=0;ALU_OP=0;if(Inst_code31:26=0)beginca

4、se(Inst_code5:0)6b100000:ALU_OP=3b100;6b100010:ALU_OP=3b101;6b100100:ALU_OP=3b000;6b100101:ALU_OP=3b001;6b100110:ALU_OP=3b010;6b100111:ALU_OP=3b011;6b101011:ALU_OP=3b110;6b000100:ALU_OP=3b111;endcasewrite_reg=1;endendendmodule 2 PC取指令模塊：module pc(input clk,input rst,output 31:0Inst_code);reg 31:0PC;

5、wire31:0PC_new;initialPC=32h00000000;Inst_ROM Inst_ROM1 (.clka(clk),.addra(PC7:2),.douta(Inst_code);assign PC_new=24h000000,PC_new7:0;always(negedge clk or posedge rst)beginif(rst)PC=32h00000000;else PC=PC_new;endendmodule寄存器堆模塊moduleRegister_file(R_Addr_A,R_Addr_B,W_Addr,Write_Reg,W_Data,Clk,Reset,

6、R_Data_A,R_Data_B);input 4:0R_Addr_A;input 4:0R_Addr_B;input 4:0W_Addr;input Write_Reg;input 31:0W_Data;input Clk;input Reset;output 31:0R_Data_A;output 31:0R_Data_B;reg 31:0REG_Files0:31;reg 5:0i; 3 仿真過(guò)程中的初始化initial/beginfor(i=0;i=31;i=i+1)REG_Filesi=0;endassign R_Data_A=REG_FilesR_Addr_A;assign R_

7、Data_B=REG_FilesR_Addr_B;always(posedge Clk or posedge Reset)beginif(Reset)for(i=0;i=31;i=i+1)REG_Filesi=0;elseif(Write_Reg&W_Addr!=0)REG_FilesW_Addr=W_Data;endendmoduleAL算術(shù)邏輯運(yùn)算單元模塊,ZF,OF);module ALU(A,B,F,ALU_Oinput 31:0A,B;input 2:0ALU_OP;output reg ZF,OF;output reg31:0F;reg C32;always(*)beginOF=1

8、b0;C32=1b0;case(ALU_OP)3b000:F=A&B;3b001:F=A|B;3b010:F=AB;3b011:F=(AB); 4 3b100:begin C32,F=A+B;OF=A31B31F31C32;end 3b101:begin C32,F=A-B;OF=A31B31F31C32;end 3b110:if(AB)F=1;elseF=0;3b111:F=BA;endcaseif(F=0)ZF=1;elseZF=0;endendmodule測(cè)試代碼module test;/ Inputsreg rst;reg clk;/ Outputswire ZF;wire OF;wi

9、re 31:0 F;/ Instantiate the Unit Under Test (UUT)top_R_cpu uut (.rst(rst),.clk(clk),.ZF(ZF),.OF(OF), 5 .F(F) ); initial begin/ Initialize Inputsrst = 0;clk = 0;/ Wait 100 ns for global reset to finish#100;clk=1;/ Add stimulus hereforeverbegin#50;clk=clk;endendendmodule二、仿真波形 6 三、電路頂層電路模 頂層電路內(nèi)部構(gòu) 7 四、

10、引腳配置（約束文件NET LED7 LOC = T11;NET LED6 LOC = R11;NET LED5 LOC = N11;NET LED4 LOC = M11;NET LED3 LOC = V15;NET LED2 LOC = U15;NET LED1 LOC = V16;NET LED0 LOC = U16;NET SW2 LOC = V9;NET SW1 LOC = T9;NET SW0 LOC = T10;NET clk LOC = C9;NET st LOC = C4;五、思考與探實(shí)驗(yàn)結(jié)果記錄型指CP結(jié)標(biāo)指執(zhí)行結(jié)序正000000827FFFFFFFF1正000001102b0000_00012正00004218200000_00023正00006220200000_00034正00000_00050500832820正0000_000700600a33020正007004638040000_000E正00800a648200000_000C正00012640040000_7000