基于FPGA控制的LED漢字滾動顯示器設(shè)計

1、基于fpga控制的led漢字滾動顯示器設(shè)計2 硬件原理圖整個電路由五大部分組成：時鐘計數(shù)模塊gel_clk，存儲漢字字模的rom模塊romzi，數(shù)據(jù)分配器模塊mux，移位模塊yw及顯示模塊xiansh-i。時鐘計數(shù)模塊用于產(chǎn)生整個電路所需要的時鐘及其對時鐘的計數(shù)值，例如：移位時鐘clk yw，移位計數(shù)器cnt yw，字計數(shù)器cnt word，顯示掃描計數(shù)器cnt sm。romzi模塊是由qualtus中的lpm 1port rom定制成，用來存儲8個待顯示的漢字。mux模塊用于在掃描時鐘及掃描計數(shù)器的作用下，從rom中讀出一個漢字的8個行字模信息，送給移位模塊yw，yw模塊在移位時鐘及移位計數(shù)

2、器作用下，根據(jù)select信號選擇對讀出的字模信息，進行相應(yīng)的移位(左移、右移、上移、下移)后，最后送顯示模塊disp驅(qū)動led點陣顯示漢字。原理圖如圖2所示。32 romzi模塊利用lpm參數(shù)化模塊庫中單口rom，利用qualtus中的megawizard plug-in manager定制而成，定制前首先要制作lpm rom初始化文件，其中存儲待顯示漢字的字模數(shù)據(jù)，然后按照lpm megawizardplug-in manager的向?qū)崾?，結(jié)合設(shè)計要求進行定制。圖3為所定制rom中的初始化漢字“元旦生日開心快樂”的字型碼。數(shù)據(jù)分配模塊mux要求能在8個時鐘作用下，從rom中讀出一行(一個

3、漢字的8個字型碼)分別送到數(shù)據(jù)分配器中的wllwl8輸出端。圖4為數(shù)據(jù)分配模塊在掃描時鐘作用下讀取的字模數(shù)據(jù)，比較圖3和圖4可知，仿真結(jié)果正確，能滿足題目要求。33 移位模塊yw移位模塊yw是整個設(shè)計的核心，行掃描實現(xiàn)左移，是通過每來一個移位時鐘，將每一行的字模按位左移一位，掃描時鐘到來時送出移位后的新字模。通過8次移位，可將一個漢字移出點陣平面，按類似的道理，也可以將一個漢字經(jīng)8次移位后移進點陣平面。本例(圖2)中，cnt yw為移位時鐘的計數(shù)值，以wllwl8為欲顯示漢字的原始字模，l10l80為移位后從列上送出的8行顯示字模信息，lllll8為8個原始字模信息未送出位的暫存信號。設(shè)計中需

4、要16個移位時鐘，通過前8個時鐘將wllwl8字模移進led點陣平面，再經(jīng)后8個時鐘，將漢字又一位一位地移出。移位設(shè)計參考文獻中有關(guān)移位寄存器的設(shè)計，分計數(shù)值為“0000和非0000兩部分處理，對第一行字模的處理為：其他行可按相同方法處理，具體參見如下的程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity memtest isport (rst : in std_logic;clk : in std_logic;den : i

5、n std_logic;-serial input enablerxd : in std_logic;-serial input dataouten : in std_logic;- output data requestrdmem : out std_logic;-read memorywrmem : out std_logic;- write memorycsmem : out std_logic;- chip enable memorymemdata: inout std_logic_vector(7 downto 0);- memory data interfacememaddr: o

6、ut std_logic_vector(2 downto 0);- memory addressdataout: out std_logic_vector(7 downto 0);-data outputdataclkout: out std_logic -data output sync clk );end memtest;architecture behav of memtest is constant s0 :std_logic_vector(2 downto 0):= 001; constant s1 :std_logic_vector(2 downto 0):= 010; const

7、ant s2 :std_logic_vector(2 downto 0):= 100;signal ss: std_logic_vector(2 downto 0);signal rdmemaddr,wrmemaddr: std_logic_vector(2 downto 0);signal rxdcnt: std_logic_vector(3 downto 0);signal rdmemdata, wrmemdata :std_logic_vector(7 downto 0);signal wrmem_s, wrrdy, dataclkout_s :std_logic;beginproces

8、s(rst,clk)beginif rst = 0 thenwrmemdata 0);elsif clkevent and clk = 1 thenif den = 1 thenwrmemdata(7) = wrmemdata(6);wrmemdata(6) = wrmemdata(5);wrmemdata(5) = wrmemdata(4);wrmemdata(4) = wrmemdata(3);wrmemdata(3) = wrmemdata(2);wrmemdata(2) = wrmemdata(1);wrmemdata(1) = wrmemdata(0);wrmemdata(0) =

9、rxd;end if;end if;end process;process(rst,clk)beginif rst = 0 thenrxdcnt 0);elsif clkevent and clk = 1 thenif den = 1 thenif rxdcnt = 9 thenrxdcnt = rxdcnt;elserxdcnt = rxdcnt +1;end if;elserxdcnt 0);end if;end if;end process;process(rst,clk)beginif rst = 0 thenss if wrrdy = 1 thenss = s1;elsif oute

10、n = 1 thenss ss ss ss = s0;end case;end if;end process;process(rst,clk)beginif rst = 0 thenwrrdy = 0;elsif clkevent and clk = 1 thenif ss = s1 thenwrrdy = 0;elseif rxdcnt = 8 thenwrrdy = 1;elsewrrdy = 0;end if;end if;end if;end process;wrmem_s = 0 when ss = s1 else 1;rdmem = 0 when ss = s2 else 1;cs

11、mem = 1 when ss = s1 or ss = s2 else 0;process(rst,clk)beginif rst = 0 thendataclkout_s = 0;elsif clkevent and clk = 1 thenif ss = s2 thendataclkout_s = 1;elsedataclkout_s = 0;end if;end if;end process;process(clk)beginif clkevent and clk = 1 thendataclkout = dataclkout_s;end if;end process;process(

12、rst,clk)beginif rst = 0 thendataout 0);elsif clkevent and clk = 1 thenif ss = s2 thendataout = rdmemdata;end if;end if;end process;process(rst,clk)beginif rst = 0 thenwrmemaddr 0);elsif clkevent and clk = 1 thenif ss = s1 thenwrmemaddr = wrmemaddr +1;end if;end if;end process;process(rst,clk)beginif

13、 rst = 0 thenrdmemaddr 0);elsif clkevent and clk = 1 thenif ss = s2 thenrdmemaddr = rdmemaddr +1 ;end if;end if;end process;memaddr = wrmemaddr when wrmem_s = 0 else rdmemaddr;memdata = wrmemdata when wrmem_s = 0 else zzzzzzzz;rdmemdata = memdata;wrmem = wrmem_s;end behav;library ieee;use ieee.std_l

14、ogic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity states isport (rst : in std_logic;clk : in std_logic;nscar: in std_logic;ewcar: in std_logic;nsred: out std_logic;nsgreen: out std_logic;nsyellow: out std_logic;ewred: out std_logic;ewgreen: out std_logic;ewyellow: out

15、 std_logic );end states;architecture behav of states is constant s0 :std_logic_vector(1 downto 0):= 00;- ewgreen constant s1 :std_logic_vector(1 downto 0):= 01; constant s2 :std_logic_vector(1 downto 0):= 11;- nsgreen constant s3 :std_logic_vector(1 downto 0):= 10;signal ss: std_logic_vector(1 downt

16、o 0);signal tm60s,tm40s :std_logic_vector(5 downto 0);signal tm3s :std_logic_vector(1 downto 0);signal entm60s,entm40s,entm3s,tm60soc,tm40soc,tm3soc :std_logic;beginprocess(rst,clk)beginif rst = 0 thenss if nscar = 1 thenif ewcar = 1 thenif tm60soc = 1 thenss = s1;end if;else ss if tm3soc = 1 thenss

17、 if nscar = 1 thenif ewcar = 1 thenif tm40soc = 1 thenss = s3;end if;end if;elsess if tm3soc = 1 thenss ss = s0;end case;end if;end process;process(rst,clk)beginif rst = 0 thenentm60s = 0;elsif clkevent and clk = 1 thenif ss = s0 thenentm60s = 1;elseentm60s = 0;end if;end if;end process;process(rst,

18、clk)beginif rst = 0 thenentm40s = 0;elsif clkevent and clk = 1 thenif ss = s2 thenentm40s = 1;elseentm40s = 0;end if;end if;end process;process(rst,clk)beginif rst = 0 thenentm3s = 0;elsif clkevent and clk = 1 thenif ss = s1 or ss = s3 thenentm3s = 1;elseentm3s = 0;end if;end if;end process;process(

19、rst,clk)beginif rst = 0 thentm60s = b000000;elsif clkevent and clk = 1 thenif entm60s = 1 thenif tm60s = 59 thentm60s = b000000;elsetm60s = tm60s + 1;end if;elsetm60s = b000000;end if;end if;end process;process(rst,clk)beginif rst = 0 thentm40s = b000000;elsif clkevent and clk = 1 thenif entm40s = 1

20、 thenif tm40s = 39 thentm40s = b000000;elsetm40s = tm40s + 1;end if;elsetm40s = b000000;end if;end if;end process;process(rst,clk)beginif rst = 0 thentm3s = b00;elsif clkevent and clk = 1 thenif entm3s = 1 thenif tm3s = 2 thentm3s = b00;elsetm3s = tm3s + 1;end if;elsetm3s = b00;end if;end if;end process;process(rst,clk)beginif rst = 0 thentm60soc = 0; elsif clkevent and clk = 1 thenif tm60s = 59 thentm60soc = 1;elsetm60soc = 0;end if;end if;end process;process(rst,clk)b