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1、西安交通大學(xué)城市學(xué)院本科生畢業(yè)設(shè)計(jì)(論文)at89c51外文翻譯descriptionthe at89c51 is a low-power, high-performance cmos 8-bit microcomputer with 4k bytes of flash programmable and erasable read only memory (perom). the device is manufactured using atmels high density nonvolatile memory technology and is compatible with the in
2、dustry standard mcs-51 instruction-set and pinout. the on-chip flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. by combining a versatile 8-bit cpu with flash on a monolithic chip, the atmel at89c51 is a powerful microcomputer which prov
3、ides a highly flexible and cost effective solution to many embedded control applications.features compatible with mcs-51 products 4k bytes of in-system reprogrammable flash memory endurance: 1,000 write/erase cycles fully static operation: 0 hz to 24 mhz three-level program memory lock 128 x 8-bit i
4、nternal ram 32 programmable i/o lines two 16-bit timer/counters six interrupt sources programmable serial channel low power idle and power down modesthe at89c51 provides the following standard features: 4k bytes of flash,128 bytes of ram, 32 i/o lines, two 16-bit timer/counters, a five vector two-le
5、vel interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. in addition, the at89c51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. the idle mode stops the cpu while allowing the ram, time
6、r/counters, serial port and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator disabling all other chip functions until the next hardware reset.vccsupply voltage.gndground.port 0port 0 is an 8-bit open-drain bi-directional i/o port. as an
7、output port, each pin can sink eight ttl inputs. when 1s are written to port 0 pins, the pins can be used as high-impedance inputs. port 0 may also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. in this mode p0 has internal pullups
8、.port 0 also receives the code bytes during flash programming, and outputs the code bytes during program verification. external pullups are required during program verification. port 1port 1 is an 8-bit bi-directional i/o port with internal pullups.the port 1 output buffers can sink/source four ttl
9、inputs.when 1s are written to port 1 pins they are pulled high by the internal pullups and can be used as inputs. as inputs,port 1 pins that are externally being pulled low will source current (iil) because of the internal pullups.port 1 also receives the low-order address bytes during flash program
10、ming and verification. port 2port 2 is an 8-bit bi-directional i/o port with internal pullups.the port 2 output buffers can sink/source four ttl inputs.when 1s are written to port 2 pins they are pulled high by the internal pullups and can be used as inputs. as inputs,port 2 pins that are externally
11、 being pulled low will source current (iil) because of the internal pullups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx dptr). in this application, it uses strong internal pullups wh
12、en emitting 1s. during accesses to external data memory that use 8-bit addresses (movx ri), port 2 emits the contents of the p2 special function register. port 2 also receives the high-order address bits and some control signals during flash programming and verification.port 3port 3 is an 8-bit bi-d
13、irectional i/o port with internal pullups. the port 3 output buffers can sink/source four ttl inputs.when 1s are written to port 3 pins they are pulled high by the internal pullups and can be used as inputs. as inputs,port 3 pins that are externally being pulled low will source current (iil) because
14、 of the pullups. port 3 also serves the functions of various special features of the at89c51 as listed below:port 3 also receives some control signals for flash programming and verification. rstreset input. a high on this pin for two machine cycles while the oscillator is running resets the device.
15、ale/progaddress latch enable output pulse for latching the low byte of the address during accesses to external memory. this pin is also the program pulse input (prog) during flash programming. in normal operation ale is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for
16、external timing or clocking purposes. note, however, that one ale pulse is skipped during each access to external datamemory. if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with the bit set, ale is active only during a movx or movc instruction. otherwise, the pin is
17、weakly pulled high. setting the ale-disable bit has no effect if the microcontroller is in external execution mode.psenprogram store enable is the read strobe to external program memory. when the at89c51 is executing code from external program memory, psen is activated twice each machine cycle, exce
18、pt that two psen activations are skipped during each access to external data memory. ea/vppexternal access enable. ea must be strapped to gnd in order to enable the device to fetch code from external program memory locations starting at 0000h up to ffffh.note, however, that if lock bit 1 is programm
19、ed, ea will be internally latched on reset. ea should be strapped to vcc for internal program executions.this pin also receives the 12-volt programming enable voltage (vpp) during flash programming, for parts that require 12-volt vpp.xtal1input to the inverting oscillator amplifier and input to the
20、internal clock operating circuit. xtal2output from the inverting oscillator amplifier.oscillator characteristics xtal1 and xtal2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 1. either a quartz crystal or
21、 ceramic resonator may be used. to drive the device from an external clock source, xtal2 should be left unconnected while xtal1 is driven as shown in figure 2.there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a div
22、ide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.idle mode in idle mode, the cpu puts itself to sleep while all the on-chip peripherals remain active. the mode is invoked by software. the content of the on-chip ram and all the special functions
23、registers remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hardware reset. it should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before t
24、he internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write to a port pin when idle is terminated by reset, the instruction following the one that invokes
25、idle should not be one that writes to a port pin or to external memory.figure 1. oscillator connectionsnote: c1, c2 = 30 pf 10 pf for crystals= 40 pf 10 pf for ceramic resonatorsfigure 2. external clock drive configurationpower-down mode in the power-down mode, the oscillator is stopped, and the ins
26、truction that invokes power-down is the last instruction executed. the on-chip ram and special function registers retain their values until the power-down mode is terminated. the only exit from power-down is a hardware reset. reset redefines the sfrs but does not change the on-chip ram. the reset sh
27、ould not be activated before vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.program memory lock bits on the chip are three lock bits which can be left unprogrammed (u) or can be programmed (p) to obtain the additiona
28、l features listed in the table below.when lock bit 1 is programmed, the logic level at the ea pin is sampled and latched during reset. if the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. it is necessary that the latched
29、 value of ea be in agreement with the current logic level at that pin in order for the device to function properly.programming the flash the at89c51 is normally shipped with the on-chip flash memory array in the erased state (that is, contents = ffh)and ready to be programmed. the programming interf
30、ace accepts either a high-voltage (12-volt) or a low-voltage (vcc) program enable signal. the low-voltage programming mode provides a convenient way to program the at89c51 inside the users system, while the high-voltage programming mode is compatible with conventional thirdparty flash or eprom progr
31、ammers.the at89c51 is shipped with either the high-voltage or low-voltage programming mode enabled. the respective top-side marking and device signature codes are listed in the following table.the at89c51 code memory array is programmed byte-by-byte in either programming mode. to program any non-bla
32、nk byte in the on-chip flash memory, the entire memory must be erased using the chip erase mode. programming algorithm: before programming the at89c51, the address, data and control signals should be set up according to the flash programming mode table and figures 3 and 4. to program the at89c51, ta
33、ke the following steps.1. input the desired memory location on the address lines.2. input the appropriate data byte on the data lines. 3. activate the correct combination of control signals.4. raise ea/vpp to 12v for the high-voltage programming mode. 5. pulse ale/prog once to program a byte in the
34、flash array or the lock bits. the byte-write cycle is self-timedand typically takes no more than 1.5 ms. repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.data polling: the at89c51 features data polling to indicate the end of
35、a write cycle. during a write cycle, anattempted read of the last byte written will result in the complement of the written datum on po.7. once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. data polling may begin any time after a write cycle ha
36、s been initiated. ready/busy: the progress of byte programming can also be monitored by the rdy/bsy output signal. p3.4 is pulled low after ale goes high during programming to indicate busy. p3.4 is pulled high again when programming is done to indicate ready.program verify: if lock bits lb1 and lb2
37、 have not been programmed, the programmed code data can be read back via the address and data lines for verification. the lock bits cannot be verified directly. verification of the lock bits is achieved by observing that their features are enabled. chip erase: the entire flash array is erased electr
38、ically by using the proper combination of control signals and by holding ale/prog low for 10 ms. the code array is written with all “1”s. the chip erase operation must be executed before the code memory can be re-programmed.reading the signature bytes: the signature bytes are read by the same proced
39、ure as a normal verification of locations 030h, 031h, and 032h, except that p3.6 and p3.7 must be pulled to a logic low. the values returned are as follows. (030h) = 1eh indicates manufactured by atmel (031h) = 51h indicates 89c51 (032h) = ffh indicates 12v programming (032h) = 05h indicates 5v prog
40、rammingprogramming interfaceevery code byte in the flash array can be written and the entire array can be erased by using the appropriate combination of control signals. the write operation cycle is selftimed and once initiated, will automatically time itself to completion.all major programming vend
41、ors offer worldwide support for the atmel microcontroller series. please contact your local programming vendor for the appropriate software revision. flash programming and verification waveforms - high-voltage mode (vpp = 12v)flash programming and verification waveforms - low-voltage mode (vpp = 5v)
42、flash programming and verification characteristics ta = 0c to 70c, vcc = 5.0 10%absolute maximum ratings*notice: stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any
43、 other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.dc characteristicsta = -40c to 85c, vcc = 5.0v 20% (unless otherwise noted)notes: 1. under stea
44、dy state (non-transient) conditions, iol must be externally limited as follows:maximum iol per port pin: 10 mamaximum iol per 8-bit port: port 0: 26 maports 1, 2, 3: 15 mamaximum total iol for all output pins: 71 maif iol exceeds the test condition, vol may exceed the related specification. pins are
45、 not guaranteed to sink current greater than the listed test conditions.2. minimum vcc for power-down is 2v.ac characteristicsunder operating conditions, load capacitance for port 0, ale/prog, and psen = 100 pf; load capacitance for all other outputs = 80 pf.external program and data memory characte
46、risticsexternal program memory read cycleexternal data memory read cycleexternal data memory write cycleexternal clock drive waveformsexternal clock driveserial port timing: shift register mode test conditions(vcc = 5.0 v 20%; load capacitance = 80 pf)shift register mode timing waveformsac testing i
47、nput/output waveforms(1)note: 1. ac inputs during testing are driven at vcc - 0.5v for a logic 1 and 0.45v for a logic 0. timing measurements are made at vih min. for a logic 1 and vil max. for a logic 0.float waveforms(1)note: 1. for timing purposes, a port pin is no longer floating when a 100mv ch
48、ange from load voltage occurs. a port pin begins to float when 100mv change from the loaded voh/vol level occurs.at89c51中文原文at89c51是美國atmel公司生產(chǎn)的低電壓,高性能cmos8位單片機(jī),片內(nèi)含4k bytes的可反復(fù)擦寫的只讀程序存儲器(perom)和128 bytes的隨機(jī)存取數(shù)據(jù)存儲器(ram),器件采用atmel公司的高密度、非易失性存儲技術(shù)生產(chǎn),兼容標(biāo)準(zhǔn)mcs-51指令系統(tǒng),片內(nèi)置通用8位中央處理器(cpu)和flash存儲單元,功能強(qiáng)大at89c51
49、單片機(jī)可為您提供許多高性價(jià)比的應(yīng)用場合,可靈活應(yīng)用于各種控制領(lǐng)域。主要性能參數(shù):與mcs-51產(chǎn)品指令系統(tǒng)完全兼容4k字節(jié)可重擦寫flash閃速存儲器1000次擦寫周期全靜態(tài)操作:0hz24mhz三級加密程序存儲器1288字節(jié)內(nèi)部ram32個(gè)可編程io口線2個(gè)16位定時(shí)計(jì)數(shù)器6個(gè)中斷源可編程串行uart通道低功耗空閑和掉電模式功能特性概述:at89c51 提供以下標(biāo)準(zhǔn)功能:4k 字節(jié)flash 閃速存儲器,128字節(jié)內(nèi)部ram,32 個(gè)io 口線,兩個(gè)16位定時(shí)計(jì)數(shù)器,一個(gè)5向量兩級中斷結(jié)構(gòu),一個(gè)全雙工串行通信口,片內(nèi)振蕩器及時(shí)鐘電路。同時(shí),at89c51可降至0hz的靜態(tài)邏輯操作,并支持兩種
50、軟件可選的節(jié)電工作模式。空閑方式停止cpu的工作,但允許ram,定時(shí)計(jì)數(shù)器,串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存ram中的內(nèi)容,但振蕩器停止工作并禁止其它所有部件工作直到下一個(gè)硬件復(fù)位。 引腳功能說明vcc:電源電壓gnd:地p0 口:p0 口是一組8 位漏極開路型雙向io 口,也即地址數(shù)據(jù)總線復(fù)用口。作為輸出口用時(shí),每位能吸收電流的方式驅(qū)動(dòng)8個(gè)ttl邏輯門電路,對端口寫“1”可作為高阻抗輸入端用。在訪問外部數(shù)據(jù)存儲器或程序存儲器時(shí),這組口線分時(shí)轉(zhuǎn)換地址(低8位)和數(shù)據(jù)總線復(fù)用,在訪問期間激活內(nèi)部上拉電阻。在fiash編程時(shí),p0口接收指令字節(jié),而在程序校驗(yàn)時(shí),輸出指令字節(jié),校驗(yàn)時(shí),要求
51、外接上拉電阻。p1口:p1是一個(gè)帶內(nèi)部上拉電阻的8位雙向io口,p1的輸出緩沖級可驅(qū)動(dòng)(吸收或輸出電流)4個(gè)ttl邏輯門電路。對端口寫“1”,通過內(nèi)部的上拉電阻把端口拉到高電平,此時(shí)可作輸入口。作輸入口使用時(shí),因?yàn)閮?nèi)部存在上拉電阻,某個(gè)引腳被外部信號拉低時(shí)會輸出一個(gè)電流(iil)。fiash編程和程序校驗(yàn)期間,p1接收低8位地址。p2口:p2是一個(gè)帶有內(nèi)部上拉電阻的8位雙向io口,p2的輸出緩沖級可驅(qū)動(dòng)(吸收或輸出電流)4個(gè)ttl邏輯門電路。對端口寫“1”,通過內(nèi)部的上拉電阻把端口拉到高電平,此時(shí)可作輸入口,作輸入口使用時(shí),因?yàn)閮?nèi)部存在上拉電阻,某個(gè)引腳被外部信號拉低時(shí)會輸出一個(gè)電流(iil)
52、。在訪問外部程序存儲器或16位地址的外部數(shù)據(jù)存儲器(例如執(zhí)行movxdptr指令)時(shí),p2口送出高8位地址數(shù)據(jù)。在訪問8 位地址的外部數(shù)據(jù)存儲器(如執(zhí)行movxri 指令)時(shí),p2 口線上的內(nèi)容(也即特殊功能寄存器(sfr)區(qū)中r2寄存器的內(nèi)容),在整個(gè)訪問期間不改變。flash編程或校驗(yàn)時(shí),p2亦接收高位地址和其它控制信號。p3口:p3口是一組帶有內(nèi)部上拉電阻的8 位雙向io 口。p3 口輸出緩沖級可驅(qū)動(dòng)(吸收或輸出電流)4 個(gè)ttl邏輯門電路。對p3 口寫入“1”時(shí),它們被內(nèi)部上拉電阻拉高并可作為輸入端口。作輸入端時(shí),被外部拉低的p3 口將用上拉電阻輸出電流(iil)。p3口除了作為一般的
53、io口線外,更重要的用途是它的第二功能,如下表所示:p3口還接收一些用于flash閃速存儲器編程和程序校驗(yàn)的控制信號。rst:復(fù)位輸入。當(dāng)振蕩器工作時(shí),rst引腳出現(xiàn)兩個(gè)機(jī)器周期以上高電平將使單片機(jī)復(fù)位。aleprog: 當(dāng)訪問外部程序存儲器或數(shù)據(jù)存儲器時(shí),ale(地址鎖存允許)輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問外部存儲器,ale 仍以時(shí)鐘振蕩頻率的l6 輸出固定的正脈沖信號,因此它可對外輸出時(shí)鐘或用于定時(shí)目的。要注意的是:每當(dāng)訪問外部數(shù)據(jù)存儲器時(shí)將跳過一個(gè)ale脈沖。對flash存儲器編程期間,該引腳還用于輸入編程脈沖(prog)。如有必要,可通過對特殊功能寄存器(sfr)區(qū)中的8
54、eh單元的do 位置位,可禁止ale 操作。該位置位后,只有一條movx和movc指令ale才會被激活。此外,該引腳會被微弱拉高,單片機(jī)執(zhí)行外部程序時(shí),應(yīng)設(shè)置ale無效。psen:程序儲存允許(psen)輸出是外部程序存儲器的讀選通信號,當(dāng)at89c51 由外部程序存儲器取指令(或數(shù)據(jù))時(shí),每個(gè)機(jī)器周期兩次psen有效,即輸出兩個(gè)脈沖。在此期間,當(dāng)訪問外部數(shù)據(jù)存儲器,這兩次有效的psen信號不出現(xiàn)。eavpp:外部訪問允許。欲使cpu僅訪問外部程序存儲器(地址為0000hffffh),ea端必須保持低電平(接地)。需注意的是:如果加密位lb1被編程,復(fù)位時(shí)內(nèi)部會鎖存ea端狀態(tài)。如ea端為高電平
55、(接vcc端),cpu則執(zhí)行內(nèi)部程序存儲器中的指令。flash存儲器編程時(shí),該引腳加上+12v的編程允許電源vpp,當(dāng)然這必須是該器件是使用12v編程電壓vpp。xtal1:振蕩器反相放大器的及內(nèi)部時(shí)鐘發(fā)生器的輸入端。xtal2:振蕩器反相放大器的輸出端。時(shí)鐘振蕩器:at89c5l 中有一個(gè)用于構(gòu)成內(nèi)部振蕩器的高增益反相放大器,引腳xtal1 和xtal2 分別是該放大器的輸入端和輸出端。這個(gè)放大器與作為反饋元件的片外石英晶體或陶瓷諧振器一起構(gòu)成自激振蕩器,振蕩電路參見圖5。外接石英晶體(或陶瓷諧振器)及電容c1、c2接在放大器的反饋回路中構(gòu)成并聯(lián)振蕩電路。對外接電容c1、c2雖然沒有十分嚴(yán)格
56、的要求,但電容容量的大小會輕微影響振蕩頻率的高低、振蕩器工作的穩(wěn)定性、起振的難易程序及溫度穩(wěn)定性,如果使用石英晶體,我們推薦電容使用30pf10pf,而如使用陶瓷諧振器建議選擇40pf10f。用戶也可以采用外部時(shí)鐘。采用外部時(shí)鐘的電路如圖5右圖所示。這種情況下,外部時(shí)鐘脈沖接到xtal1端,即內(nèi)部時(shí)鐘發(fā)生器的輸入端,xtal2則懸空。由于外部時(shí)鐘信號是通過一個(gè)2分頻觸發(fā)器后作為內(nèi)部時(shí)鐘信號的,所以對外部時(shí)鐘信號的占空比沒有特殊要求,但最小高電平持續(xù)時(shí)間和最大的低電平持續(xù)時(shí)間應(yīng)符合產(chǎn)品技術(shù)條件的要求。空閑節(jié)電模式:at89c51 有兩種可用軟件編程的省電模式,它們是空閑模式和掉電工作模式。這兩種
57、方式是控制專用寄存器pcon(即電源控制寄存器)中的pd(pcon.1)和idl(pcon.0)位來實(shí)現(xiàn)的。pd 是掉電模式,當(dāng)pd=1 時(shí),激活掉電工作模式,單片機(jī)進(jìn)入掉電工作狀態(tài)。idl是空閑等待方式,當(dāng)idl=1,激活空閑工作模式,單片機(jī)進(jìn)入睡眠狀態(tài)。如需同時(shí)進(jìn)入兩種工作模式,即pd和idl同時(shí)為1,則先激活掉電模式。在空閑工作模式狀態(tài),cpu保持睡眠狀態(tài)而所有片內(nèi)的外設(shè)仍保持激活狀態(tài),這種方式由軟件產(chǎn)生。此時(shí),片內(nèi)ram和所有特殊功能寄存器的內(nèi)容保持不變??臻e模式可由任何允許的中斷請求或硬件復(fù)位終止。終止空閑工作模式的方法有兩種,其一是任何一條被允許中斷的事件被激活,idl(pcon.
58、0)被硬件清除,即刻終止空閑工作模式。程序會首先響應(yīng)中斷,進(jìn)入中斷服務(wù)程序,執(zhí)行完中斷服務(wù)程序并緊隨reti(中斷返回)指令后,下一條要執(zhí)行的指令就是使單片機(jī)進(jìn)入空閑模式那條指令后面的一條指令。其二是通過硬件復(fù)位也可將空閑工作模式終止。需要注意的是,當(dāng)由硬件復(fù)位來終止空閑工作模式時(shí),cpu 通常是從激活空閑模式那條指令的下一條指令開始繼續(xù)執(zhí)行程序的,要完成內(nèi)部復(fù)位操作,硬件復(fù)位脈沖要保持兩個(gè)機(jī)器周期(24個(gè)時(shí)鐘周期)有效,在這種情況下,內(nèi)部禁止cpu訪問片內(nèi)ram,而允許訪問其它端口。為了避免可能對端口產(chǎn)生意外寫入,激活空閑模式的那條指令后一條指令不應(yīng)是一條對端口或外部存儲器的寫入指令。掉電模式:在掉電模式下,振蕩器停止工作,
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