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1、P89LPC9521. 概述P89LPC952是一款單片封裝的微控制器，含有多種低成本的封裝形 式。它采用了高性能的處理器結構，指令執(zhí)行時間只需 2 到4 個時鐘 周期。6倍于標準80C51器件。P89LPC95集成了許多系統(tǒng)級的功能， 這樣可大大減少元件的數目和電路板面積并降低系統(tǒng)的成本。2. 特性2.1 主要特性8KB可擦除Flash程序存儲器，具有1KB扇區(qū)和64字節(jié)頁。單字節(jié) 擦除特性使得任何字節(jié)都可用于非易失性數據存儲。256字節(jié)RAM數據存儲器和256字節(jié)附加片內RAM具有window比較器的8輸入多路10位A/D轉換器，結果在允許范圍 以內或以外 都可產生中斷。 2 個模擬比較器

2、可選擇輸入和參考源。2 個16 位定時/計數器（每一個定時器均可設置為溢出時觸發(fā)相應端口輸出或作為PWM輸出），23位的系統(tǒng)定時器可用作實時時鐘 （RTC）。兩個增強型UART具有波特率發(fā)生器、間隔檢測、幀錯誤檢測和自動 地址檢測功能。 400kHz 字節(jié)寬度的 I2C 通信端口和 SPI 通信端口。片內高精度的 RC 振蕩器選項帶有時鐘倍頻器，無需外接振蕩器件。 可選擇RC振蕩器選項并且其頻率可進行很好的調節(jié)。內部 RC振蕩器 和任何振蕩器源之間的快速切換，提供低功耗有效模式的最佳支持， 可快速轉變?yōu)樽罡咝阅?。VDD操作電壓范圍為2.43.6V。I/O 口可承受5V （可上拉或驅動到 5.5

3、V）。44腳封裝，使用片內振蕩器和復位選項時，至少可獲得 40個I/O 口。P5的所有管腳可吸收/消耗高電流（20mA。其它所有的端口管腳都 有高消耗電流的能力（20mA。整個芯片指定了最大值的限制。頻器可從 8 個值中選擇。2.2 其它特性18MHz時，除乘法和除法指令外，高速80C51 CPU的指令執(zhí)行時間為111222n&同一時鐘頻率下，其速度為標準80C51器件的6 倍。只需要較低的時鐘頻率即可達到同樣的性能，這樣無疑降 低了功耗和 EMI。Flash在電路編程（ICP）可通過商用EPROMI程器實現簡單的 編程。Flash保密位可防止程序被讀出。Flash在系統(tǒng)編程（ISP）可實現已

4、固定在最終應用上的器件的 編程。Flash程序存儲器可實現在應用中編程（IAP ）。這允許在程序運行 時改變代碼。配置為一個中斷。電平中斷輸入喚醒）。典型的掉電電流為1卩A （比較器關閉時的完全掉電狀態(tài)）。要外接元件。復位計數器和復位干擾抑制電路可防止虛假和不完全的 復位。另外還提供軟件復位功能。P89LPC952只需連接電源和地。Flash 配置位進行 選擇。RC振蕩器選項支持的頻率范圍為20kHz18MHz用于振蕩器的失效檢測。I/O 口輸出模式：準雙向口，開漏輸出，推挽和僅為輸入功 能。P0 口管腳的值與一個可編程的模式 匹配或者不匹配時，可產生一個中斷。EMI,輸出最小跳變時間約為10

5、ns。4 個中斷優(yōu)先級。8 個鍵盤中斷輸入,另加 2 路外部中斷輸入。DPTR）。P89LPC952 Flash 存儲器1. 概述P89LPC952 Flash存儲器提供電路中的電擦除和編程。Flash可以字節(jié)為單位擦除、讀取或寫入。扇區(qū)和頁擦除功能可擦除任意的 Flash 扇區(qū) （1kB）或頁（64字節(jié)）。芯片擦除功能可實現整個程序存儲器的擦除。ICP 功能通過標準商用編程器來實現。另外， IAP 和字節(jié)擦除功能允許程 序存儲器用作非易失性數據存儲器。片內產生的擦除和寫入時序為用 戶提供了友好的編程接口。 P89LPC952 Flash 存儲器甚至在經過 100, 000 次擦除和編程周期后

6、仍然能可靠地保存存儲器的內容。存儲單元 的設計優(yōu)化了擦除和編程機制。P89LPC952使用VDD電壓來執(zhí)行編程 和擦除算法。2. 特性? 可在整個操作電壓范圍內執(zhí)行編程和擦除。? 字節(jié)擦除允許程序存儲器用于存儲數據。?使用 ISP/IAP/ICP 進行讀/編程/擦除。?內部固化的引導ROM，包含了可用于用戶程序的低級IAP子程序。? 默認的裝載程序可通過串口進行 ISP 編程。該程序位于用戶程序存儲 器空間的頂端。?Boot 向量允許用戶將 Flash 裝載代碼放入 Flash 存儲器內的任何位置。 這種配置為用戶提供了應用的靈活性。?任意Flash編程/擦除時間小于2ms。? 使用工業(yè)標準的

7、商用編程器進行編程。? 可對每一個 Flash 扇區(qū)進行編程加密。? 每個字節(jié)至少可執(zhí)行 100,000 次擦除/編程。? 數據至少可保存 10 年。3. Flash 的結構P89LPC952器件包含8個1KB扇區(qū)的Flash程序存儲器。每個扇區(qū)可進 一步分成 64 字節(jié)的頁。除了扇區(qū)擦除、頁擦除和字節(jié)擦除外，還包含 一個64 字節(jié)的頁寄存器，它可實現給定頁 1 到64 字節(jié)的同時編程， 這徹底降低了整個編程的時間。4. Flash 用作數據存儲器P89LPC952的Flash程序存儲器支持單個字節(jié)的擦除和編程。程序存 儲器的任何一個字節(jié)都可通過 MOVC指令來讀取，只要包含該字節(jié)的扇 區(qū)未加

8、密（MOVC指令不能讀取加密扇區(qū)的程序存儲器的內容）。因 此，非加密扇區(qū)的任何字節(jié)都可用來存儲非易失性數據。5. Flash 的編程和擦除有4 種方法可實現對 Flash 的編程或擦除。第一，在應用固件的控制 下，在最終用戶應用程序中(IAP)對Flash進行編程或擦除。第二， 使用 ICP 功能。通過系統(tǒng)提供的串行時鐘 / 串行數據接口來實現 ICP 編 程。第三，出廠時，器件的用戶代碼空間的高 512 字節(jié)包含一個串行 ISP 程序，調用該程序通過串口來實現在電路編程。第四，使用支持 該器件的商用EPROM編程器進行并行編程或擦除。該器件不提供對代碼內容的直接校驗。而是提供一個扇區(qū)或整個用

9、戶代碼區(qū)的32位CRC結果附外文原文：P89LPC9521. General descriptionThe P89LPC952 is a single-chip microcontroller, available in low cost packages, based ona high performance processor architecture that executes instructions in two to four clocks,six times the rate of standard 80C51 devices. Many system-level functio

10、ns have beenincorporated into the P89LPC952 in order to reduce component count, board space, and system cost.2. Features2.1 Principal features- 8 kB byte-erasable flash code memory organized into 1 kB sectors and 64- byte pages.Single-byte erasing allows any byte(s) to be used as non-volatile data s

11、torage.-256-byte RAM data memory and a 256-byte auxiliary on-chip RAM.- 8-input multiplexed 10-bit ADC with window comparator that can generate an interruptfor in or out of range results. Two analog comparators with selectable inputs andreference source.-Two 16-bit counter/timers (each may be config

12、ured to toggle a port output upon timeroverflow or to become a PWM output) and a 23-bit system timer that can also be usedas a RTC.- Two enhanced UARTs with a fractional baud rate generator, break detect, framingerror detection, and automatic address detection 400 kHz bytewide I2C-buscommunication p

13、ort and SPI communication port.- High-accuracy internal RC oscillator option, with clock doubler option, allows operationwithout external oscillator components. The RC oscillator option is selectable and finetunable. Fast switching between the internal RC oscillator and any oscillator sourceprovides

14、 optimal support of minimal power active mode with fast switching tomaximum performance.- 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up ordriven to 5.5 V).-44-pin packages with 40 I/O pins minimum while using on-chip oscillator and resetoptions.- Port 5 has high cur

15、rent sourcing/sinking (20 mA) for all Port 5 pins. All other port pinshave high sinking capability (20 mA). A maximum limit is specified for the entire chip.- Watchdog timer with separate on-chip oscillator, requiring no external components.The watchdog prescaler is selectable from eight valu.es 2.2

16、 Additional features- A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 nsfor all instructions except multiply and divide when executing at 18 MHz. This is sixtimes the performance of the standard 80C51 running at the same clock frequency. Alower clock frequency for the

17、same performance results in power savings and reducedEMI.-Serial flash In-Circuit Programming (ICP) allows simple production coding withcommercial EPROM programmers. Flash security bits prevent reading of sensitiveapplication programs.- Serial flash In-System Programming (ISP) allows coding while th

18、e device is mountedin the end application.- In-Application Programming (IAP) of the flash code memory. This allows changing thecode in a running application.- Low voltage (brownout) detect allows a graceful system shutdown when power fails.May optionally be configured as an interrupt.- Idle and two

19、different power-down reduced power modes. Improved wake-up fromPower-down mode (a LOW interrupt input starts execution). Typical power-downcurrent is 1 mA (total power-down with voltage comparators disabled).- Active-LOW reset input can be driven by any internal reset. On-chip power-on resetallows o

20、peration without external reset components. A reset counter and reset glitchsuppression circuitry prevent spurious and incomplete resets. A software resetfunction is also available.-Only power and ground connections are required to operate the P89LPC952 wheninternal reset option is selected.- Config

21、urable on-chip oscillator with frequency range options selected by userprogrammed flash configuration bits. Oscillator options support frequencies from20 kHz to the maximum operating frequency of 18 MHz.- Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillatorallowing it t

22、o perform an oscillator fail detect function.- Programmable port output configuration options: quasi-bidirectional, open drain,push-pull, input-only.- Port input pattern match detect. Port 0 may generautpet awnheinnterrthe value ofthe pins match or do not match a programmable pattern. -Controlled sl

23、ew rate port outputs to reduce EMI. Outputs have approximately 10 nsminimum ramp times.- Four interrupt priority levels.- Eight keypad interrupt inputs, plus two additional external interrupt inputs.- Schmitt trigger port inputs.-Second data pointer.-Extended temperature range.附外文原文：The P89LPC952 fl

24、ash memory General description-The P89LPC952 flash memory provides in-circuit electrical erasure and programming.-The flash can be erased, read, and written as bytes. The Sector and Page Erase functionscan erase any flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erasethe entir

25、e program memory. ICP using standard commercial programmers is available. Inaddition, IAP and byteerase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programminginterface. The P89LPC952 flash reliably stores memor

26、y contents even after100,000 erase and program cycles. The cell is designed to optimize the erase andprogramming mechanisms. The P89LPC952 uses VDD as the supply voltage to performthe Program/Erase algorithms. Features?Programming and erase over the full operating voltage range. ?Byte erase allows c

27、ode memory to be used for data storage. ?Read/Programming/Erase using ISP/IAP/ICP.?Internal fixed boot ROM, containing low-level IAP routines available to user code.?Default loader providing ISP via the serial port, located in upper end of user programmemory.?Boot vector allows user-provided flash l

28、oader code to reside anywhere in the flashmemory space, providing flexibility to the user.?Any flash program/erase operation in 2 ms.?Programming with industry-standard commercial programmers. ?Programmable security for the code in the flash for each sector.?100,000 typical erase/program cycles for

29、each byte.?10 year minimum data retention.Flash organization-The program memory consists of eight 1 kB sectors on the P89LPC952 devices. Eachsector can be further divided into 64-byte pages. In addition to sector erase, page erase,and byte erase, a 64-byte page register is included which allows from

30、 1 to 64 bytes of agiven page to be programmed at the same time, substantially reducing overallprogramming time.Using flash as data storage-The flash code memory array of this device supports individual byte erasing andprogramming. Any byte in the code memory array may be read using the MOVCinstruction, provided that the sector containing the