MSP430G2553學習筆記(數(shù)據(jù)手冊)

1、MSP430G2553學習筆記（數(shù)據(jù)手冊）MSP430G2553性能參數(shù)(DIP-20)工作電壓范圍：1.83.6V。5種低功耗模式。16位的RISC結構，62.5ns指令周期。超低功耗：運行模式-230A；待機模式-0.5A；關閉模式-0.1A；可以在不到1s的時間里超快速地從待機模式喚醒?；緯r鐘模塊配置：具有四種校準頻率并高達16MHz的內部頻率；內部超低功耗LF振蕩器；32.768KHz晶體；外部數(shù)字時鐘源。兩個16 位Timer_A，分別具有三個捕獲/比較寄存器。用于模擬信號比較功能或者斜率模數(shù)(A/D)轉換的片載比較器。帶內部基準、采樣與保持以及自動掃描功能的10位200-ksps

2、 模數(shù)(A/D)轉換器。16KB閃存，512B的RAM。16個I/O口。 注意：MSP430G2553無P3口！MSP430G2553的時鐘基本時鐘系統(tǒng)的寄存器DCOCTL-DCO控制寄存器DCOx DCO頻率選擇控制1MODxDCO頻率校正選擇，通常令MODx=0 注意：在MSP430G2553上電復位后，默認RSEL=7，DCO=3，通過數(shù)據(jù)手冊查得DCO頻率大概在0.81.5MHz之間。BCSCTL1-基本時鐘控制寄存器1XT2OFF 不用管，因為MSP430G2553內部沒有XT2提供的HF時鐘XTS 不用管，默認復位后的0值即可DIVAx設置ACLK的分頻數(shù)00/101/210/41

3、1/8RSELx DCO頻率選擇控制2BCSCTL2-基本時鐘控制寄存器2SELMxMCLK的選擇控制位00DCOCLK01DCOCLK10LFXT1CLK或者VLOCLK11LFXT1CLK或者VLOCLKDIVMx設置MCLK的分頻數(shù)00/101/210/411/8SELS SMCLK的選擇控制位 0DCOCLK 1LFXT1CLK或者VLOCLKDIVSx設置SMCLK的分頻數(shù)00/101/210/411/8DCOR DCO直流發(fā)生電阻選擇，此位一般設00內部電阻 1外部電阻BCSCTL3-基本時鐘控制寄存器3XT2Sx 不用管LFXT1Sx00LFXT1選為32.768KHz晶振01保

4、留10VLOCLK11外部數(shù)字時鐘源XCAPx LFXT1晶振諧振電容選擇001pF016pF1010pF1112.5pFmsp430g2553.h中基本時鐘系統(tǒng)的內容/* Basic Clock Module*/#define _MSP430_HAS_BC2_ /* Definition to show that Module is available */SFR_8BIT(DCOCTL); /* DCO Clock Frequency Control */SFR_8BIT(BCSCTL1); /* Basic Clock System Control 1 */SFR_8BIT(BCSCTL

5、2); /* Basic Clock System Control 2 */SFR_8BIT(BCSCTL3); /* Basic Clock System Control 3 */#define MOD0 (0x01) /* Modulation Bit 0 */#define MOD1 (0x02) /* Modulation Bit 1 */#define MOD2 (0x04) /* Modulation Bit 2 */#define MOD3 (0x08) /* Modulation Bit 3 */#define MOD4 (0x10) /* Modulation Bit 4 *

6、/#define DCO0 (0x20) /* DCO Select Bit 0 */#define DCO1 (0x40) /* DCO Select Bit 1 */#define DCO2 (0x80) /* DCO Select Bit 2 */#define RSEL0 (0x01) /* Range Select Bit 0 */#define RSEL1 (0x02) /* Range Select Bit 1 */#define RSEL2 (0x04) /* Range Select Bit 2 */#define RSEL3 (0x08) /* Range Select B

7、it 3 */#define DIVA0 (0x10) /* ACLK Divider 0 */#define DIVA1 (0x20) /* ACLK Divider 1 */#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */#define XT2OFF (0x80) /* Enable XT2CLK */#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */#define DIVA_2 (0x

8、20) /* ACLK Divider 2: /4 */#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */#define DIVS0 (0x02) /* SMCLK Divider 0 */#define DIVS1 (0x04) /* SMCLK Divider 1 */#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */#define DIVM0 (0x10) /* MCLK Divider 0 */#define DIVM1 (0x20) /* MCLK

9、 Divider 1 */#define SELM0 (0x40) /* MCLK Source Select 0 */#define SELM1 (0x80) /* MCLK Source Select 1 */#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */#defi

10、ne DIVM_0 (0x00) /* MCLK Divider 0: /1 */#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */#define S

11、ELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */#define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */#define XT2OF (0x02) /* High frequency oscillator 2 fault flag */#define XCAP0 (0x04) /* XIN/XOUT Cap 0 */#define XCAP1

12、 (0x08) /* XIN/XOUT Cap 1 */#define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */#define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */#define XT2S0 (0x40) /* Mode 0 for XT2 */#define XT2S1 (0x80) /* Mode 1 for XT2 */#define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */#define XCAP_1 (0x04) /* XIN/XOUT

13、 Cap : 6 pF */#define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */#define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5 pF */#define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */#define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */#define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */#define LFXT1S

14、_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */#define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */#define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */#define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */#define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal */基本時鐘系統(tǒng)例程(DCO) M

15、SP430G2553在上電之后默認CPU執(zhí)行程序的時鐘MCLK來自于DCO時鐘。TI提供的Launch Pad上，P1.0和P1.6分別接了紅色和綠色的LED燈，下面寫一個程序讓它們交替閃爍；之后我們來改變DCO的頻率，進而使軟延時時間變化，可以看到LED閃爍間隔有變化。#include msp430g2553.hvoid main(void)WDTCTL = WDTPW + WDTHOLD;P1DIR |= BIT0 + BIT6;while(1)P1OUT = BIT0 + BIT6;_delay_cycles(100000);這段程序采用430上電后默認的DCO頻率，假設是1MHz的話，

16、則延時100000個DCO提供的MCLK大概是0.1s左右。下面一段程序，將DCOx設置為1，RSELx設置為1，通過數(shù)據(jù)手冊查得DCO頻率大概在0.060.14MHz之間，所以明顯MCLK要慢得多了，因此LED閃爍時間延長。#include msp430g2553.hvoid main(void)WDTCTL = WDTPW + WDTHOLD;DCOCTL |= DCO0;DCOCTL &=(DCO1 + DCO2);BCSCTL1 |= RSEL0;BCSCTL1 &= (RSEL1 + RSEL2 + RSEL3);P1DIR |= BIT0 + BIT6;while(1)P1OUT

17、= BIT0 + BIT6;_delay_cycles(100000);MSP430G2553的I/O口MSP430G2553共有2組數(shù)字I/O口：P1和P2，每組各有8個引腳，每個引腳都能夠響應中斷，接受外部輸入的上升沿或者下降中斷請求。所有I/O口均與單片機內部外設的特殊功能引腳復用，當我們選用I/O功能時，要作為通用I/O口來使用，這需要相應的寄存器來進行控制。I/O頭文件內容/* DIGITAL I/O Port1/2 Pull up / Pull down Resistors*/#define _MSP430_HAS_PORT1_R_ /* Definition to show th

18、at Module is available */#define _MSP430_HAS_PORT2_R_ /* Definition to show that Module is available */SFR_8BIT(P1IN); /* Port 1 Input */SFR_8BIT(P1OUT); /* Port 1 Output */SFR_8BIT(P1DIR); /* Port 1 Direction */SFR_8BIT(P1IFG); /* Port 1 Interrupt Flag */SFR_8BIT(P1IES); /* Port 1 Interrupt Edge Se

19、lect */SFR_8BIT(P1IE); /* Port 1 Interrupt Enable */SFR_8BIT(P1SEL); /* Port 1 Selection */SFR_8BIT(P1SEL2); /* Port 1 Selection 2 */SFR_8BIT(P1REN); /* Port 1 Resistor Enable */SFR_8BIT(P2IN); /* Port 2 Input */SFR_8BIT(P2OUT); /* Port 2 Output */SFR_8BIT(P2DIR); /* Port 2 Direction */SFR_8BIT(P2IF

20、G); /* Port 2 Interrupt Flag */SFR_8BIT(P2IES); /* Port 2 Interrupt Edge Select */SFR_8BIT(P2IE); /* Port 2 Interrupt Enable */SFR_8BIT(P2SEL); /* Port 2 Selection */SFR_8BIT(P2SEL2); /* Port 2 Selection 2 */SFR_8BIT(P2REN); /* Port 2 Resistor Enable */P1口P1.0、P1.1、P1.2P1.3P1.4P1.5、P1.6、P1.7P2.0、P2.

21、1、P2.2、P2.3、P2.4、P2.5P2.6P2.7P1DIR用來選擇I/O口是輸入還是輸出，0為輸入，1為輸出。P1IN為輸入寄存器，外部的電平輸入狀態(tài)可從此寄存器相應的位讀取。P1OUT為輸出寄存器，向外輸出的電平狀態(tài)可從此寄存器送出。P1SEL和P1SEL2為引腳功能選擇。MSP430G2553的Timer_ATimer_A的工作原理MSP430G2553內部有兩個Timer_A模塊，分別是Timer0_A3和Timer1_A3?！?”表示每個Timer_A模塊有3組“捕獲/比較”寄存器。Timer_A的主要特性包括：(1) 具有16位定時/計數(shù)功能，3種計數(shù)模式可選(2) 16位

22、定時計數(shù)器時鐘源可選(3) 可在CPU不介入的情況下，產生PWM波(4) 計數(shù)器溢出可產生中斷Timer_A又兩部分組成：主計數(shù)器和比較捕獲模塊。其中主計數(shù)器如下圖。TAR為16主計數(shù)器的當前計數(shù)值，可對TAR賦初值。主計數(shù)器計數(shù)時鐘有4種來源，通過TASSELx來進行選擇。IDx可對輸入時鐘進行分頻，TACLR為主計數(shù)器的清零控制位，MCx用來選擇主計數(shù)器的4種計數(shù)模式，TAIFG為主計數(shù)器中斷標志位。TASSELx：00=外部管腳時鐘輸入 01=ACLK 10=SMCLK 11=TACLK取反IDx：00=不分頻 01=2分頻 10=4分頻 11=8分頻TACLR：0=不清零 1=清零Ti

23、mer_A一共有三種計數(shù)模式，分別是：增計數(shù)、連續(xù)增計數(shù)和增減計數(shù)。增計數(shù)模式下，每個時鐘周期計數(shù)值TAR加1，當TAR值超過TACCR0時，TAR自動清零，并且置位TAIFG標志位。而后TAR從0值重新開始加1。改變TACCR0的值即可改變定時周期。連續(xù)增計數(shù)模式下，TAR從零加1，加到溢出值0xFFFF為止，之后自動歸零重新開始。通常我們利用該計數(shù)模式進行信號的捕捉，利用TACCRx寄存器存儲捕獲發(fā)生的時刻。增減計數(shù)模式下，TAR的值從零加到TACRR0，而后再減到零，如此循環(huán)。通常我們利用該計數(shù)模式產生對稱、可加死區(qū)延時的PWM波。Timer_A的另一重要組成部分，是捕獲/比較模塊，每個

24、Timer_A均有3個捕獲/比較模塊，它的作用主要有兩方面。一是在比較模式下，每個捕獲/比較模塊都拿自身捕獲/比較寄存器TACCRx的值與主計數(shù)器TAR的值比較，一旦相等，就自動的改變某個引腳的輸出電平，一共有8種電平變化規(guī)律可選，這樣可以在無CPU干預的情況下產生PWM波；二是在捕獲模式下，從某個指定引腳的輸入電平跳變可以觸發(fā)捕獲電路，并將此時主計數(shù)器的數(shù)值自動保存到相應的捕獲值寄存器TACCRx中，這個過程純硬件實現(xiàn)，無CPU干預，可以用來測量頻率、占空比等。捕獲/比較模塊結構圖如下：CAP用來切換選擇捕獲/比較工作模式；CCISx選擇捕獲輸入源；CMx選擇捕獲觸發(fā)沿狀態(tài)，COV為捕獲溢出

25、標志位，如果前一次的捕獲值未被讀取而新的捕獲已經產生，則溢出標志位會置位；捕獲引腳的電平狀態(tài)可以實時的通過CCI讀出；由于捕獲信號可能與時鐘信號不同步，從而產生數(shù)字電路競爭，我們可以置位SCS進行同步捕獲，假設實際信號的發(fā)生時刻值為N，那么同步捕捉到的值將為N+1，建議均采用同步捕捉。在比較模式下，我們可以通過程序填寫TACCRx的值，硬件會自動的將該值與TAR的值進行比較，一旦相等，即產生EQU信號，則通過輸出引腳產生電平變化，其中OUTMODEx可以選擇電平變化的8種方式，這樣就可以產生不同種類的PWM波。OUT可以控制引腳的輸出電平(高、低的選擇)。已Timer0_A3為例，其捕獲/比較

26、引腳均與I/O口復用，具體復用引腳參加數(shù)據(jù)手冊。在比較輸出模式0下，輸出引腳的狀態(tài)由OUT位控制。其余7種模式下，引腳電平的變化如下圖：增計數(shù)模式下連續(xù)增計數(shù)模式下增減計數(shù)模式下Timer_A頭文件內容/* Timer0_A3*/#define _MSP430_HAS_TA3_ /* Definition to show that Module is available */SFR_16BIT(TA0IV); /* Timer0_A3 Interrupt Vector Word */SFR_16BIT(TA0CTL); /* Timer0_A3 Control */SFR_16BIT(TA0C

27、CTL0); /* Timer0_A3 Capture/Compare Control 0 */SFR_16BIT(TA0CCTL1); /* Timer0_A3 Capture/Compare Control 1 */SFR_16BIT(TA0CCTL2); /* Timer0_A3 Capture/Compare Control 2 */SFR_16BIT(TA0R); /* Timer0_A3 */SFR_16BIT(TA0CCR0); /* Timer0_A3 Capture/Compare 0 */SFR_16BIT(TA0CCR1); /* Timer0_A3 Capture/Co

28、mpare 1 */SFR_16BIT(TA0CCR2); /* Timer0_A3 Capture/Compare 2 */* Alternate register names */#define TAIV TA0IV /* Timer A Interrupt Vector Word */#define TACTL TA0CTL /* Timer A Control */#define TACCTL0 TA0CCTL0 /* Timer A Capture/Compare Control 0 */#define TACCTL1 TA0CCTL1 /* Timer A Capture/Comp

29、are Control 1 */#define TACCTL2 TA0CCTL2 /* Timer A Capture/Compare Control 2 */#define TAR TA0R /* Timer A */#define TACCR0 TA0CCR0 /* Timer A Capture/Compare 0 */#define TACCR1 TA0CCR1 /* Timer A Capture/Compare 1 */#define TACCR2 TA0CCR2 /* Timer A Capture/Compare 2 */#define TAIV_ TA0IV_ /* Time

30、r A Interrupt Vector Word */#define TACTL_ TA0CTL_ /* Timer A Control */#define TACCTL0_ TA0CCTL0_ /* Timer A Capture/Compare Control 0 */#define TACCTL1_ TA0CCTL1_ /* Timer A Capture/Compare Control 1 */#define TACCTL2_ TA0CCTL2_ /* Timer A Capture/Compare Control 2 */#define TAR_ TA0R_ /* Timer A

31、*/#define TACCR0_ TA0CCR0_ /* Timer A Capture/Compare 0 */#define TACCR1_ TA0CCR1_ /* Timer A Capture/Compare 1 */#define TACCR2_ TA0CCR2_ /* Timer A Capture/Compare 2 */* Alternate register names 2 */#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */#define CCTL1 TACCTL1 /* Timer A Captu

32、re/Compare Control 1 */#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */

33、#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */#define TASSEL1

34、 (0x0200) /* Timer A clock source select 1 */#define TASSEL0 (0x0100) /* Timer A clock source select 0 */#define ID1 (0x0080) /* Timer A clock input divider 1 */#define ID0 (0x0040) /* Timer A clock input divider 0 */#define MC1 (0x0020) /* Timer A mode control 1 */#define MC0 (0x0010) /* Timer A mo

35、de control 0 */#define TACLR (0x0004) /* Timer A counter clear */#define TAIE (0x0002) /* Timer A counter interrupt enable */#define TAIFG (0x0001) /* Timer A counter interrupt flag */#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to

36、 CCR0 */#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */#define ID_2 (2*0x40u) /* Timer A input divider

37、: 2 - /4 */#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */#define TASSEL_3

38、 (3*0x100u) /* Timer A clock source select: 3 - INCLK */#define CM1 (0x8000) /* Capture mode 1 */#define CM0 (0x4000) /* Capture mode 0 */#define CCIS1 (0x2000) /* Capture input select 1 */#define CCIS0 (0x1000) /* Capture input select 0 */#define SCS (0x0800) /* Capture sychronize */#define SCCI (0

39、x0400) /* Latched capture signal (read) */#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */#define OUTMOD2 (0x0080) /* Output mode 2 */#define OUTMOD1 (0x0040) /* Output mode 1 */#define OUTMOD0 (0x0020) /* Output mode 0 */#define CCIE (0x0010) /* Capture/compare interrupt enable */#defin

40、e CCI (0x0008) /* Capture input signal (read) */#define OUT (0x0004) /* PWM Output signal if output mode 0 */#define COV (0x0002) /* Capture/compare overflow flag */#define CCIFG (0x0001) /* Capture/compare interrupt flag */#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */#defi