EDA技術(shù)與應(yīng)用作業(yè)版

1、EDA技術(shù)與應(yīng)用作業(yè)1.5什么叫“綜合”？一般綜合包含哪些過程？答：將多個模塊化設(shè)計文件合并為一個網(wǎng)表文件，并使層次設(shè)計平面化（即展平）；對 VHDL或 Verilog HDL進(jìn)行分析處理，并將其轉(zhuǎn)換成電路結(jié)構(gòu)或模塊，對實(shí)際現(xiàn)實(shí)目標(biāo)器件的結(jié)構(gòu)進(jìn)行優(yōu)化，并使之滿足各種條件約束，優(yōu)化關(guān)鍵路徑。2.10使用 Quartus II的 Mega Wizard Plug-In Manager宏功能模塊中的PLL 設(shè)計一個能實(shí)現(xiàn)圖題 2.10 波形的電路元件 ( 包括一個 VHDL文件和一個 *.bsf 原理圖圖標(biāo) ) 。其中：inclk0為電路的主頻輸入端，頻率為 50MHz；areset 為異步置位端，

2、 c2 和主頻 inclk0 同頻率。 c1 為主頻 inclk0 的倍頻輸出信號。 c0 為 c2 的反相信號。 Locked 為相位控制信號，也是輸出使能控制信號。解：LIBRARY IEEE;USE ieee.std_logic_1164.all;LIBRARY altera_mf;USE altera_mf.all;ENTITY whyy ISPORT(inclk0:IN STD_LOGIC := 0;pllena:IN STD_LOGIC := 1;c0:OUT STD_LOGIC ;c1:OUT STD_LOGIC ;c2:OUT STD_LOGIC ;locked:OUT STD

3、_LOGIC);END whyy;ARCHITECTURE SYN OF whyy ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (5 DOWNTO 0);SIGNAL sub_wire1: STD_LOGIC ;SIGNAL sub_wire2: STD_LOGIC ;SIGNAL sub_wire3: STD_LOGIC ;SIGNAL sub_wire4: STD_LOGIC ;SIGNAL sub_wire5: STD_LOGIC ;SIGNAL sub_wire6: STD_LOGIC_VECTOR (1 DOWNTO 0);SIGNAL sub_wire

4、7_bv : BIT_VECTOR (0 DOWNTO 0);SIGNAL sub_wire7: STD_LOGIC_VECTOR (0 DOWNTO 0);COMPONENT altpllGENERIC (clk0_divide_by: NATURAL;clk0_duty_cycle: NATURAL;clk0_multiply_by: NATURAL;clk0_phase_shift: STRING;clk1_divide_by: NATURAL;clk1_duty_cycle: NATURAL;clk1_multiply_by: NATURAL;clk1_phase_shift: STR

5、ING;clk2_divide_by: NATURAL;clk2_duty_cycle: NATURAL;clk2_multiply_by: NATURAL;clk2_phase_shift: STRING;compensate_clock: STRING;gate_lock_signal: STRING;inclk0_input_frequency: NATURAL;intended_device_family: STRING;invalid_lock_multiplier: NATURAL;lpm_hint: STRING;lpm_type: STRING;operation_mode:

6、STRING;port_activeclock: STRING;port_areset: STRING;port_clkbad0: STRING;port_clkbad1: STRING;port_clkloss: STRING;port_clkswitch: STRING;port_configupdate: STRING;port_fbin: STRING;port_inclk0: STRING;port_inclk1: STRING;port_locked: STRING;port_pfdena: STRING;port_phasecounterselect: STRING;port_p

7、hasedone: STRING;port_phasestep: STRING;port_phaseupdown: STRING;port_pllena: STRING;port_scanaclr: STRING;port_scanclk: STRING;port_scanclkena: STRING;port_scandata: STRING;port_scandataout: STRING;port_scandone: STRING;port_scanread: STRING;port_scanwrite: STRING;port_clk0: STRING;port_clk1: STRIN

8、G;port_clk2: STRING;port_clk3: STRING;port_clk4: STRING;port_clk5: STRING;port_clkena0: STRING;port_clkena1: STRING;port_clkena2: STRING;port_clkena3: STRING;port_clkena4: STRING;port_clkena5: STRING;port_extclk0: STRING;port_extclk1: STRING;port_extclk2: STRING;port_extclk3: STRING;valid_lock_multi

9、plier: NATURAL);PORT (clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);inclk: IN STD_LOGIC_VECTOR (1 DOWNTO 0);locked: OUT STD_LOGIC ;pllena: IN STD_LOGIC);END COMPONENT;BEGINsub_wire7_bv(0 DOWNTO 0) = 0;sub_wire7= To_stdlogicvector(sub_wire7_bv);sub_wire4= sub_wire0(2);sub_wire3= sub_wire0(0);sub_wire1= sub

10、_wire0(1);c1= sub_wire1;locked = sub_wire2;c0= sub_wire3;c2= sub_wire4;sub_wire5= inclk0;sub_wire6 1,clk0_duty_cycle = 50,clk0_multiply_by = 1,clk0_phase_shift = 10000,clk1_divide_by = 1,clk1_duty_cycle = 50,clk1_multiply_by = 2,clk1_phase_shift = 0,clk2_divide_by = 1,clk2_duty_cycle = 50,clk2_multi

11、ply_by = 1,clk2_phase_shift = 0,compensate_clock = CLK0,gate_lock_signal = NO,inclk0_input_frequency = 20000,intended_device_family = Cyclone II,invalid_lock_multiplier = 5,lpm_hint = CBX_MODULE_PREFIX=hsu_2014_ch2_pll_vhdl, lpm_type = altpll,operation_mode = NORMAL,port_activeclock = PORT_UNUSED,po

12、rt_areset = PORT_UNUSED,port_clkbad0 = PORT_UNUSED,port_clkbad1 = PORT_UNUSED,port_clkloss = PORT_UNUSED,port_clkswitch = PORT_UNUSED,port_configupdate = PORT_UNUSED,port_fbin = PORT_UNUSED,port_inclk0 = PORT_USED,port_inclk1 = PORT_UNUSED,port_locked = PORT_USED,port_pfdena = PORT_UNUSED,port_phase

13、counterselect = PORT_UNUSED,port_phasedone = PORT_UNUSED,port_phasestep = PORT_UNUSED,port_phaseupdown = PORT_UNUSED,port_pllena = PORT_USED,port_scanaclr = PORT_UNUSED,port_scanclk = PORT_UNUSED,port_scanclkena = PORT_UNUSED,port_scandata = PORT_UNUSED,port_scandataout = PORT_UNUSED,port_scandone =

14、 PORT_UNUSED,port_scanread = PORT_UNUSED,port_scanwrite = PORT_UNUSED,port_clk0 = PORT_USED,port_clk1 = PORT_USED,port_clk2 = PORT_USED,port_clk3 = PORT_UNUSED,port_clk4 = PORT_UNUSED,port_clk5 = PORT_UNUSED,port_clkena0 = PORT_UNUSED,port_clkena1 = PORT_UNUSED,port_clkena2 = PORT_UNUSED,port_clkena

15、3 = PORT_UNUSED,port_clkena4 = PORT_UNUSED,port_clkena5 = PORT_UNUSED,port_extclk0 = PORT_UNUSED,port_extclk1 = PORT_UNUSED,port_extclk2 = PORT_UNUSED,port_extclk3 = PORT_UNUSED,valid_lock_multiplier = 1)PORT MAP (inclk = sub_wire6,pllena = pllena,clk = sub_wire0,locked = sub_wire2);END SYN;3.20 試用

16、VHDL 語言設(shè)計一個曼徹斯特編碼器。已知有時鐘信號clk_d 、時鐘的倍頻信號clk及時鐘的反相信號clk_dn 。串行數(shù)據(jù)輸入為data_s, 編碼輸出為mcode_out, 輸出使能信號為 clk_lock_in,高電平有效。提示：曼徹斯特碼(Manchester Code)又稱為數(shù)字雙相碼或分相碼(Split-phase Code)。它的編碼規(guī)則是 : 用分別持續(xù)半個碼元周期的正（高）、負(fù)（低）電平組合表示信碼“1”; 用分別持續(xù)半個碼元周期的負(fù)（低）、正（高）電平組合表示信碼“0”。解：代碼LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY

17、 manchester ISPORT ( clk,clk_d,clk_dn: IN STD_LOGIC;data_s: IN STD_LOGIC;clk_lock_in: IN STD_LOGIC;mcode_out: OUT STD_LOGIC);END manchester;ARCHITECTURE code OF manchester ISSIGNAL temp_clk_d: STD_LOGIC;SIGNAL temp_clk_dn: STD_LOGIC;BEGINmcode_out= temp_clk_d OR temp_clk_dn ;p1:PROCESS(clk,clk_d,clk

18、_dn)BEGINIF ( clk event AND clk=1) THENIF (clk_lock_in=1) THENIF (data_s=1) THENtemp_clk_d= clk_d;ELSEtemp_clk_d= 0;END IF;END IF;END IF;END PROCESS p1;p2:PROCESS(clk,clk_d,clk_dn)BEGINIF ( clk event AND clk=1) THENIF (clk_lock_in=1) THENIF (data_s=0) THENtemp_clk_dn= clk_dn;elsetemp_clk_dn= 0;END I

19、F;END IF;END IF;END PROCESS p2;END code;3.21 試用 VHDL 語言設(shè)計一個求兩個數(shù)中最大值的程序， 要求用函數(shù)調(diào)用的方法設(shè)計。 其中： data 為輸入信號，位寬 8bit ， dataout 為最大值輸出，位寬 8bit 。Clk 為時鐘信號。設(shè)計一位控制信號 set ，當(dāng) set 為低電平時，輸出 data 和 peak 中的最大值。解：代碼LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE WORK.bpac.ALL;ENTITY compare ISPORT(data:IN STD_LOGIC_VECTO

20、R(7 DOWNTO 0);clk,set: IN STD_LOGIC;dataout: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END compare;ARCHITECTURE peakdetect OF compare ISSIGNAL peak: STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINdataout=peak;PROCESS(clk)BEGINIF(clkEVENT AND clk=1) THENIF (set=1 ) THENpeak=data;ELSEpeakb) THEN temp:=a;ELSEtemp:=b;END IF;

21、RETURN temp;END max;END bpac;3.21 試用 VHDL 語言設(shè)計一個5Hz 分頻器，要求：占空比為50%。（選做）解：代碼LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count ISPORT(clk:IN STD_LOGIC;clk_div:OUT STD_LOGIC);END count;ARCHITECTURE div OF count ISSIGNAL count: STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL clk_

22、temp : STD_LOGIC;BEGINPROCESS(clk, count)BEGINIF (clkevent AND clk=1) THENIF(count = 010) THENcount 0);clk_temp = NOT (clk_temp);ELSEcount = count+1;END IF ;END IF ;END PROCESS;clk_div=clk_temp;END div;3.22 試用 VHDL 語言設(shè)計一個 8 位二進(jìn)制加計數(shù)器。 其中：qout 為 8 位二進(jìn)制輸出， cout 為進(jìn)位輸出， clr 為同步清零端，當(dāng) clr 為高電平時清零、低電平時工作。 C

23、ipher 為 8 位密碼控制輸入端，其控制功能如下表所示： （ 2014am)cipher功能00001111加計數(shù)11110000減計數(shù)11001100停止計數(shù)11111111停止計數(shù)并且輸出BCD碼要求：1. 設(shè)計一個計數(shù)分頻器，輸入頻率clk為 50Mhz ，輸出頻率newclk為 1hz。 newclk為計數(shù)器的計數(shù)頻率。2. 編寫一個把二進(jìn)制轉(zhuǎn)換為整數(shù)的函數(shù)。3. 當(dāng)停止計數(shù)時，調(diào)用上述函數(shù)用整數(shù)除法把二進(jìn)制數(shù)轉(zhuǎn)換為BCD 碼。解：部分頂層文件LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.A

24、LL;USE WORK.hsu_2014am_binary_n_to_integer_fun.ALL;USE WORK.hsu_2014eda_cipher_cnt8bit_updpkg.ALL;ENTITY hsu_2014eda_cipher_cnt8bit_updownpkgtop ISPORT(clk,clr: IN STD_LOGIC;OUTY: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);COUT: OUT STD_LOGIC;cipher: INSTD_LOGIC_VECTOR(7 DOWNTO 0);hex2_102: OUT STD_LOGIC_VECT

25、OR(7 DOWNTO 0);hex1_101: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);hex0_100: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END hsu_2014eda_cipher_cnt8bit_updownpkgtop;ARCHITECTURE behave_cipher_cntn OF hsu_2014eda_cipher_cnt8bit_updownpkgtop IS SIGNAL m2: INTEGER RANGE 0 TO 9;SIGNAL m1: INTEGER RANGE 0 TO 9;SIGNAL m0: IN

26、TEGER RANGE 0 TO 9;SIGNAL cntn: STD_LOGIC_VECTOR(7 DOWNTO 0):=00000000; SIGNAL data: STD_LOGIC_VECTOR(7 DOWNTO 0):=00000000; SIGNAL flag1_2:STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL cipher_temp:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL clk_1hz_temp:STD_LOGIC;BEGINcipher_temp=cipher;P1: PROCESS(clk_1hz_temp,cl

27、r,flag1_2,clk)BEGINIF clr=1 THEN cntn=00000000;ELSIF clk_1hz_temp EVENT AND clk_1hz_temp=1 THENif (flag1_2=00) thenIF cntn11111111 THENcntn=cntn+ 1;ELSEcntn0 THENcntn=cntn- 1;ELSEcntn=11111111;END IF;end if;END IF;OUTY=cntn;data=cntn;IF (flag1_2=00) THENCOUT= NOT( cntn(7) AND cntn(6) AND cntn(5) AND

28、 cntn(4)AND cntn(3) AND cntn(2) AND cntn(1) AND cntn(0);ELSIF (flag1_2=01) THENCOUT= (cntn(7) OR cntn(6) OR cntn(5) OR cntn(4)OR cntn(3) OR cntn(2) OR cntn(1) OR cntn(0);END IF;END PROCESS P1;p2: Process(clk,cipher_temp)BEGINIF (clk EVENT AND clk=1) THENIF (cipher_temp=00001111) THENflag1_2=00;ELSIF

29、 (cipher_temp=11110000) THENflag1_2=01;ELSIF (cipher_temp=11001100) THENflag1_2=10;ELSIF (cipher_temp=11111111) THENflag1_2=11;elseNUll;END IF;END IF;END PROCESS p2;p3: Process(clk,flag1_2,cntn)BEGINIF (clk EVENT AND clk=1) THENIF ( flag1_2=10) THENcntn=cntn;END IF;END IF;END PROCESS p3;p4: Process(

30、clk,flag1_2,cntn,data)VARIABLE data_temp_va:STD_LOGIC_VECTOR(7 DOWNTO 0);VARIABLE mmn102: INTEGER RANGE 0 TO (2*8)-1);VARIABLE mm2: INTEGER RANGE 0 TO 9;VARIABLE mm1: INTEGER RANGE 0 TO 9;VARIABLE mm0: INTEGER RANGE 0 TO 9;VARIABLE mmn100: INTEGER RANGE 0 TO 9;VARIABLE mmn101: INTEGER RANGE 0 TO 99;

31、begindata_temp_va:=data;mmn102:=bin_n_to_int(data_temp_va,mmn102);IF (clk EVENT AND clk=1) THENIF ( flag1_2=11) THENcntn=cntn;mm2:=mmn102/(10*2);mmn101:=mmn102-mm2*(10*2);mm1:=mmn101/(10);mm0:=mmn101-mm1*10;m2=mm2;m1=mm1;m0m0,q_out=hex0_100);U1: hsu_2014am_seg7integer PORT MAP(data_in=m1,q_out=hex1_

32、101);U2: hsu_2014am_seg7integer PORT MAP(data_in=m2,q_out=hex2_102);U3:hsu_div_to_1hzGENERIC MAP(N=50000000)PORT MAP(clk=clk,outclk=clk_1hz_temp);END behave_cipher_cntn;將底層元件打包LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;PACKAGE updpkg ISCOMPONENT hz1GENERIC (N: INTEGER);PORT(clk : IN STD_LOGIC;outclk :

33、 OUT STD_LOGIC);END COMPONENT;COMPONENT integerPORT (data_in : IN INTEGER RANGE 0 TO 15;q_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END COMPONENT;END updqkg;編寫一個可把二進(jìn)制數(shù)轉(zhuǎn)換為整數(shù)的函數(shù)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;PACKAGE fun ISFUNCTION bin_n_to_int( bin_data: STD_LOGI

34、C_VECTOR;bin_mn_int: INTEGER)RETURN INTEGER ;END fun;PACKAGE BODY fun ISFUNCTION bin_n_to_int( bin_data: STD_LOGIC_VECTOR;bin_mn_int: integer)RETURN INTEGERISVARIABLE bin_data_temp: STD_LOGIC_VECTOR(bin_dataRANGE);VARIABLE bin_mn_int_temp: INTEGER ;VARIABLE bin_n_int_temp: INTEGER ;BEGINbin_data_tem

35、p:=bin_data;bin_mn_int_temp:=0;FOR n IN bin_dataLOW TO bin_dataHIGH LOOPIF (bin_data_temp(n)=1 THENbin_n_int_temp:=1;ELSEbin_n_int_temp:=0;END IF;bin_mn_int_temp:=bin_mn_int_temp+bin_n_int_temp*(2*n);END LOOP;RETURN bin_mn_int_temp;END bin_n_to_int;END fun;底層文件hz1.vhdLIBRARY IEEE;USE IEEE.STD_LOGIC_

36、1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY hz1 ISGENERIC (N:integer:=500000);PORT (clk:IN STD_LOGIC;outclk:OUT STD_LOGIC);END hz1;ARCHITECTURE rtl of hz1 isSIGNAL count:integer;BEGINPROCESS(clk)BEGINIF(clk event and clk=1) THENIF(count=N-1)THENcount=0;ELEScount=coun

37、t+1;IF count(N/2) THENoutclk=1;ELESoutclk=0;END IF;END IF;END IF;END PROCESS;END rtl;底層文件 :integer.vhdLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY integer ISPORT (data_in : IN INTEGER RANGE 0 TO 15;q_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END integer;ARCHITECTURE r

38、t1 OF integer ISSIGNAL temp_data_in: INTEGER RANGE 0 TO 15;BEGINdisplay_process: PROCESS(data_in)BEGINtemp_data_in q_out q_out q_out q_out q_out q_out q_out q_out q_out q_out q_out q_out q_out q_out q_out q_out q_out = 11111111;END CASE;END PROCESS display_process;END rt1;4.14 8 線 -3 線優(yōu)先編碼器CD4532功能表

39、如表4.1a 所示 , 試用 Verilog HDL語言實(shí)現(xiàn)該8線-3 線優(yōu)先編碼器。解：代碼module yimaqi83 (y,a);input7:0a;output2:0y;reg2:0y;always(a)beginif(a7)y=3b111;else if (a6) y=3b110;else if (a5) y=3b101;else if (a4) y=3b100;else if (a3) y=3b011;else if (a2) y=3b010;else if (a1) y=3b001;elsey=3b000;endendmodule4.15 把下列 VHDL程序改寫成Verilog HDL語言，并且用Quartus通過編譯。 (2014am)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY hsu_count6_updown ISPORT(CLK,RST,ENA:IN STD_LOGIC;OUTY:OUT STD_LOGIC_VECTOR(3DOWNTO 0);COUT:OUT STD_LOGIC;cipher: IN STD_LOGIC_VECTOR(7 DO