FPGA交通燈實驗報告

1、交通燈實驗報告實驗目的實現(xiàn)兩路信號燈交替亮起，并利用兩組數(shù)碼管分別 對兩路信號進展倒計時。兩路信號時間分別為：V:綠燈30SH:紅燈35S黃燈5s綠燈30S紅燈35S黃燈5S二，實驗步驟建立工程可在歡送界面點擊“ Creat a New Project 進入工程建立界 面，亦可關閉歡送界面，點擊菜單欄的“File ，點擊“ NewProject Wizard 進入建立工程界面。右側為建立工程界面，點擊 next。IniLroduiliunTb tawMtendlliiib耳 iojcreate airnivpTffct -Brid prBinaTPtJicd srttrgs, rdjcfrig

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3、#187;dUa3i bar n trid Si 阻昭酣 theproiBd!.J'RaXj 史S J b rf.l-_C_L.Ltl T1 爭 3 H&a*. f >、 Ersh ' Cnctf '( 血勺 :在此界面選定工程路徑，取好工程名，點擊“Next 。注意:路徑中不能有中文，工程名也不能有中文。一直點擊“ Next 進入器件設置界面，DE2-70開發(fā)工具采用的 Cyclone II 系列的 EP2C70F896C6N 點擊“ Finish ，完成工程建立1、 點擊“ File，點擊“ New 選擇“ Verilog HDL2,點擊主界面工具欄中

4、的選擇“ Verilog HDL3、寫入verilog代碼。QuiJw tufi IT iPrOjeCt(T Ee-ssgn Fi le-samdl rii*Bloc匕歸匚(Fil看EDIF FileQu ya SyutkMii Flit State Machine File SysteoiVeriloia HDL File Td script FieVHDL Fileilwj I1 MJL I曰 M«nr>or v FJs®HeKadecSrnal (In tel-Forme 町 FileB VrtfietlQfiRebupglng Niestn-svstwn &a

5、mp;SLjr»s and Probes 匚il芒 LogicIntrfwp 尸ilSinaTTLL l_口口ip Analyzer File Oil 任I Fil»AHDL iFKlLide File 色lock Symbol File Chain Deamp-lion Fite Syncbpsvs deagn ConstraHttis Fte 1 ej«.t FileI, QK | encdHelp代碼如下:module traffic(Clk_50M,Rst,LedR_ H, LedG_ H, LedY_ H, LedR_ V,L edG_ V,L edY_

6、V,Seg7_VH,Seg7_VL,Seg7_HH,Seg7_HL,led15);parameter S1= 2'b00; parameter S2=2'b01; parameter S3=2'b10; parameter S4=2'b11;input Clk_50M,Rst;output LedR_ H, LedG_ H,L edY_ H, LedR_ V, LedG_ V, LedY_V;output6:0 Seg7_VH,Seg7_VL,Seg7_HH,Seg7_HL;output led15;/div for 1Hzstart-reg Clk_1H z;

7、reg 31:0 t_1H z;always(posedge Clk_50M or negedge Rst) beginif(!Rst)begint_1Hz<=1;Clk_1Hz<=1;endelsebeginif(t_1Hz>=25000000)begint_1Hz<=1;Clk_1Hz<=Clk_1H z; end elset_1Hz<=t_1Hz + 1;endend/div for 1Hzendreg7:0 t30,tH,tV,tHH,tVV;reg7:0 tDis,tDiss;/30 counter and seg7-start-reg LedR_

8、 H, LedG_ H, LedY_ H, LedR_ V, LedG_ V,L edY_V; always(posedge Clk_1Hz)begincase(state)S1:beginif(t30>=30) t30<=1;elset30<=t30 + 1;endS2:beginif(t30>=5) t30<=1;elset30<=t30 + 1;endS3:beginif(t30>=30) t30<=1;elset30<=t30 + 1;endS4:beginif(t30>=5) t30<=1;elset30<=t3

9、0 + 1; end endcase endalways(posedge Clk_1Hz)begincase(stateV)S1:beginif(tV>=30) tV<=1;elsetV<=tV + 1;endS2:beginif(tV>=5) tV<=1;elsetV<=tV + 1;endS3:beginif(tV>=35) tV<=1;elsetV<=tV + 1;endendcaseend always(posedge Clk_1Hz) begincase(stateH)S1:beginif(tH>=35) tH<=1;

10、elsetH<=tH + 1;endS2:beginif(tH>=30) tH<=1;elsetH<=tH + 1;endS3:beginif(tH>=5) tH<=1;elsetH<=tH + 1;endendcaseendalways(negedge Clk_50M or negedge Rst)begincase(state)S1:tVV=30-tV;S2:tVV=5-tV;S3:tVV=35-tV;S4:tVV=35-tV;endcaseendalways(negedge Clk_50M or negedge Rst) begincase(st

11、ate)S1:tHH=35-tH;S2:tHH=35-tH;S3:tHH=30-tH;S4:tHH=5-tH;endcaseend16進制計數(shù)器轉換為用于顯示的10進制計數(shù)器always(posedge Clk_50M)beginif(tVV>29)begintDis7:4<=3;tDis3:0v=tVV - 30;endelse if(tVV>19)begintDis7:4<=2;tDis3:0v=tVV - 20;endelse if(tVV>9)begintDis7:4<=1;tDis3:0v=tVV - 10;endelsetDis<=tVV;

12、endSEG7_LUT hex4(Seg7_VL,tDis3:0);SEG7_LUT hex5(Seg7_VH,tDis7:4);always(posedge Clk_50M)beginif(tHH>29)begintDiss7:4<=3;tDiss3:0v=tHH - 30;endelse if(tHH>19)begintDiss7:4<=2;tDiss3:0v=tHH - 20;endelse if(tHH>9)begintDiss7:4<=1;tDiss3:0v=tHH - 10;endelsetDiss<=tHH;endSEG7_LUT hex

13、1(Seg7_HL,tDiss3:0);SEG7_LUT hex2(Seg7_HH,tDiss7:4);/30 counter and seg7endreg 1:0state,stateH,stateV;always(posedge Clk_1Hz) begincase(state)S1:if(t30>=30) begin state<=S2;endS2:if(t30>=5) begin state<=S3;endS3:if(t30>=30) begin state<=S4; endS4:if(t30>=5) begin state<=S1; e

14、nddefault: begin state<=S1; endendcaseend always(posedge Clk_1Hz) begincase(state)S1:begin stateH<=S1; stateV<=S1; endS2:begin stateH<=S1; stateV<=S2; endS3:begin stateH<=S2; stateV<=S3; endS4:begin stateH<=S3; stateV<=S3; endendcaseend always(posedge Clk_50M or negedge Rs

15、t) beginif(!Rst)beginLedR_H<=0;LedG_H<=0;LedY_H<=0;LedR_V<=0;LedG_V<=0;LedY_V<=0; end else begin case(state)S1:beginLedR_H<=1;LedG_H<=0;LedY_H<=0;LedR_V<=0;LedG_V<=1;LedY_V<=0;endS2:beginLedR_H<=1;LedG_H<=0;LedY_H<=0;LedR_V<=0;LedG_V<=0;LedY_V<=1

16、;endS3:beginLedR_H<=0;LedG_H<=1;LedY_H<=0;LedR_V<=1;LedG_V<=0;LedY_V<=0;endS4:beginLedR_H<=0;LedG_H<=0;LedY_H<=1;LedR_V<=1;LedG_V<=0;LedY_V<=0; enddefault:beginLedR_H<=0;LedG_H<=0;LedY_H<=0;LedR_V<=0;LedG_V<=0;LedY_V<=0; end endcase endend assign

17、 Ied15=state;oSEG,iDIG );endmodule module SEG7_LUT ( input 3:0 iDIG;output6:0 oSEG;reg6:0 oSEG;always (iDIG)begincase(iDIG)4'h1: oSEG = 7'b1111001;/ -t-4'h2: oSEG = 7'b0100100; |4'h3: oSEG = 7'b0110000;/ ltrt4'h4: oSEG = 7'b0011001;/ |4'h5: oSEG = 7'b0010010;/

18、 -m-4'h6: oSEG = 7'b0000010;/ |4'h7: oSEG = 7'b1111000;/ lbrb4'h8: oSEG = 7'b0000000;/ |4'h9: oSEG = 7'b0011000;4'ha: oSEG = 7'b0001000;4'hb: oSEG = 7'b0000011;4'hc: oSEG = 7'b1000110;4'hd: oSEG = 7'b0100001;4'he: oSEG = 7'b0000

19、110;/ -b-4'hf: oSEG = 7'b0001110;4'hO: oSEG = 7'b1000000; endcaseendendmodule編譯工程 保存文件，將文件放在所建工程所在路徑下點擊主界面工具欄中的圖標 也可點擊菜單欄中“ Processing"，點擊“ Start pilation分配關鍵如下:Clk_50MIn putPIN_AD15LedG_HOutputPIN_AD9LedG_VOutputPIN_AJ6LedR_HOutputPIN_AJ7 )LedR_VOutputPIN_AJ5 )LedY_HOutputPIN_AD8LedY_VOutputPIN_AK5Rst In putPIN_AA23Seg7_HH6OutputPIN_G1Seg7_HH5OutputPIN_H3Seg7_HH4OutputPIN_H2Seg7_HH3OutputPIN_H1Seg7_HH2OutputPIN_J2Seg7_HH1OutputPIN_J1Seg7_HH0OutputPIN_K3Seg7_HL 6OutputPIN_E4Seg7_HL 5OutputPIN_F4Seg