全自動(dòng)電梯控制電路

1、全自動(dòng)電梯控制電路1 選題目的隨著我國(guó)經(jīng)濟(jì)持續(xù)增長(zhǎng)、城鎮(zhèn)化建設(shè)的加速和房地產(chǎn)行業(yè)的進(jìn)一步發(fā)展，對(duì)電梯的需求越來(lái)越大。所以電梯控制器就需要大強(qiáng)度的發(fā)展，來(lái)滿足社會(huì)的需求。電梯的發(fā)展更加的智能化，節(jié)約化。對(duì)社會(huì)的發(fā)展，人民生活水平的提高具有很大的意義。所以加大對(duì)電梯控制器的發(fā)展，和技術(shù)上的研究是很重要的。隨著EDA技術(shù)發(fā)展和應(yīng)用領(lǐng)域的擴(kuò)大與深入，EDA技術(shù)在電子信息、通訊、自動(dòng)控制及計(jì)算機(jī)應(yīng)用等領(lǐng)域的重要性突出。隨著技術(shù)市場(chǎng)與人才市場(chǎng)對(duì)EDA的需求不斷提高，產(chǎn)品的市場(chǎng)需求和技術(shù)市場(chǎng)的要求也必然會(huì)反映到教學(xué)領(lǐng)域和科研領(lǐng)域中來(lái)。EDA技術(shù)的提高，促進(jìn)了電梯控制器的發(fā)展。電梯行業(yè)也隨著科技的發(fā)展，不斷地

2、出現(xiàn)在人們生活的各個(gè)場(chǎng)所，因此，對(duì)電梯控制器的設(shè)計(jì)是一個(gè)很實(shí)用的例子，對(duì)掌握EDA技術(shù)的應(yīng)用也有很大的幫助。二設(shè)計(jì)目標(biāo)掌握EDA設(shè)計(jì)的一般方法；熟悉Quartus 9.0軟件，利用其設(shè)計(jì)一個(gè)符合以下設(shè)計(jì)要求的全自動(dòng)電梯控制電路。 ·設(shè)計(jì)要求設(shè)計(jì)一個(gè)層樓房全自動(dòng)電梯控制電路，其功能如下： 每層樓電梯入口處設(shè)有上，下請(qǐng)求開(kāi)關(guān)各，電梯內(nèi)設(shè)有乘客到達(dá)層次的停站要求開(kāi)關(guān)。 有電梯所處位置指示裝置和電梯上行，下行狀態(tài)批示裝置。 電梯每秒升（降）一層樓。到達(dá)某一層樓時(shí)，指示該層次的燈發(fā)光，并一直保持到電梯到達(dá)新一層為止。 電梯到達(dá)有停站請(qǐng)求的樓層后，該層次的指示燈亮，經(jīng)過(guò).5S，電梯門(mén)自動(dòng)打開(kāi)，開(kāi)

3、門(mén)指示燈亮，開(kāi)門(mén)5S后，電梯門(mén)自動(dòng)關(guān)閉（開(kāi)門(mén)指示燈滅），電梯繼續(xù)運(yùn)行。 能記憶電梯內(nèi)外的所有請(qǐng)求信號(hào)，并按照電梯運(yùn)行規(guī)則次第響應(yīng)，每個(gè)請(qǐng)求信號(hào)保留至執(zhí)行后撤除。 電梯運(yùn)行規(guī)則，電梯處于上升模式時(shí)，只響應(yīng)比電梯所在位置高的層次的上樓請(qǐng)求信號(hào)，由下而上逐個(gè)執(zhí)行，直到最后一個(gè)請(qǐng)示執(zhí)行完畢。如更高層次有下樓請(qǐng)求，則直接升到有下樓請(qǐng)求的樓層接客，然后便進(jìn)入下降模式。電梯處于下降模式時(shí)與之相反，僅響應(yīng)比電梯所在位置低的樓層的下樓請(qǐng)求。電梯執(zhí)行完所有的請(qǐng)求后，應(yīng)停在最后所在的位置不變，等待新的請(qǐng)求。 開(kāi)機(jī)（接通電源）時(shí)，電梯應(yīng)停留在一樓，而各種上，下請(qǐng)求皆被清除。 3 實(shí)現(xiàn)方案3.1控制器的控制模塊控制器包

4、括主控制器、樓層選擇器、狀態(tài)顯示器、譯碼器和樓層顯示器等6個(gè)模塊。乘客在電梯中選擇所要到達(dá)的樓層，通過(guò)主控制器的處理，電梯開(kāi)始運(yùn)行，狀態(tài)顯示器顯示電梯的運(yùn)行狀態(tài)，電梯所在樓層數(shù)通過(guò)譯碼器譯碼從而在樓層顯示器中顯示。分控制器把有效的請(qǐng)求傳給主控制器進(jìn)行處理，同時(shí)顯示電梯的運(yùn)行狀態(tài)和電梯所在樓層數(shù)。 分控制器樓層選擇器狀態(tài)顯示器主控制器譯碼器樓層顯示器3.2 控制器的流程圖初始化外部按鍵否請(qǐng)求信號(hào)寄存器是否有請(qǐng)求？樓層檢測(cè)電梯運(yùn)行等待判定電梯運(yùn)行方向目標(biāo)層與本層是否同層？是狀態(tài)寄存器是內(nèi)部軟件執(zhí)行機(jī)構(gòu)否外部硬件執(zhí)行機(jī)構(gòu) 總流程圖否是否目標(biāo)層？是電梯停止開(kāi)門(mén)關(guān)門(mén)否是否停止運(yùn)行？是停止 電梯控制主流程

5、圖 3.3控制器的VHDL描述模塊流程四層電梯控制器的設(shè)計(jì)主要是對(duì)實(shí)體和結(jié)構(gòu)體的設(shè)計(jì)，它的VHDL描述模塊流程如圖：元件庫(kù)的說(shuō)明端口定義實(shí)體狀態(tài)機(jī)進(jìn)程結(jié)構(gòu)體按鍵信號(hào)燈信號(hào)燈控制進(jìn)程結(jié)束四層電梯控制器的VHDL描述模塊流程4 設(shè)計(jì)過(guò)程4.1設(shè)計(jì)程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yxh isport(clk:in std_logic; clkout:out std_logic);end yxh;architecture one of yxh issignal count

6、: std_logic_vector(8 downto 0);begin process beginwait until clk'event and clk='1' if count<500 then count<=count+1; clkout<='0' else count<=(others=>'0'); clkout<='1' end if;end process;end architecture one;Elevator模塊（控制器）：library ieee;use ieee.

7、std_logic_1164.all;use ieee.std_logic_unsigned.all; entity elevator is port( clk: in std_logic; up1,up2,up3,stop1,stop2,stop3,stop4,down4,down3,down2: in std_logic; ddelay,dclose: in std_logic; upled,downled: out std_logic; floorled,nowfloor: out std_logic_vector(3 downto 0); dopenled: out std_logic

8、_vector(5 downto 0);end elevator;architecture bhv of elevator is type state_type is (start,run,opendoor,dopenwait2,dopenwait3,dopenwait4,dopenwait5,dopenwait6,dopenwait7,dopenwait8,dopenwait9,dopenwait10,dclse,up,down,upwait1,upwait2,downwait1,downwait2,stop); signal state : state_type; signal upm,d

9、ownm,stopm,dat: std_logic_vector(3 downto 0); signal dclosem,ddelaym: std_logic;beginstate_trans:process (clk,up1,up2,up3,down4,down3,down2,stop1,stop2,stop3,stop4,upm,downm,stopm,dat,ddelay,dclose)variable position: integer range 0 to 4;begin if rising_edge(clk) then if up1='1' then upm(0)&

10、lt;='1' end if; if up2='1' then upm(1)<='1' end if; if up3='1' then upm(2)<='1' end if; upm(3)<='0' if down4='1' then downm(3)<='1' end if; if down3='1' then downm(2)<='1' end if; if down2='1' then

11、 downm(1)<='1' end if; downm(0)<='0' if stop1='1' then stopm(0)<='1' end if; if stop2='1' then stopm(1)<='1' end if; if stop3='1' then stopm(2)<='1' end if; if stop4='1' then stopm(3)<='1' end if; if dc

12、lose='1' then dclosem<='1' end if; if ddelay='1' then ddelaym<='1' end if; dat<= upm or downm or stopm; case state iswhen start => if dat="0000" then state <= start; elsif position= 0 then position:=position+1; state <= run; end if;when run

13、 => if stopm(0)='1' or upm(0)='1' then stopm(0)<='0' upm(0)<='0' state<= opendoor; elsif dat> "0001" then state<= up; end if; elsif position=2 then if stopm(1)='1' or upm(1)='1' or downm(1)='1' then stopm(1)<='

14、;0' upm(1)<='0' downm(1)<='0' state<= opendoor; elsif dat> "0011" then state<= up; elsif dat< "0010" then state<= down; end if; elsif position=3 then if stopm(2)='1' or upm(2)='1' or downm(2)='1' then stopm(2)<=&

15、#39;0' upm(2)<='0' downm(2)<='0' state<= opendoor; elsif dat> "0111" then state<= up; elsif dat< "0100" then state<= down; end if; elsif position=4 then if stopm(3)='1' or downm(3)='1' then stopm(3)<='0' downm(3)

16、<='0' state<= opendoor; elsif dat< "1000" then state<= down; end if; end if; when up => upled<='1' state<=upwait1; when upwait1=> state<= upwait2;when upwait2=> upled<='0' position:=position+1; if position=2 and (upm>"0011&qu

17、ot; or stopm>"0011") and stopm(1)='0' and upm(1)='0' then state<= up; elsif position=3 and dat>"0111" and stopm(2)='0' and upm(2)='0' then state<= up; else state<= opendoor; end if;when down=> downled<= '1' state<= d

18、ownwait1; when downwait1=> state<= downwait2;when downwait2=> downled<= '0' position:=position-1; if position=3 and (downm<"0100" or stopm<"0100") and stopm(2)='0' and downm(2)='0' then state<= down; elsif position=2 and dat<"0

19、010" and stopm(1)='0' and downm(1)='0' then state<= down; else state<= opendoor; end if;when opendoor=> if position=1 then stopm(0)<='0' upm(0)<='0' elsif position=2 then stopm(1)<='0' upm(1)<='0' downm(1)<='0' elsi

20、f position=3 then stopm(2)<='0' upm(2)<='0' downm(2)<='0' elsif position=4 then stopm(3)<='0' downm(3)<='0' end if; dopenled<="001100" if dclosem='1' then state<= dopenwait9; dclosem<='0' elsif ddelaym='1&#

21、39; then state<= opendoor; ddelaym<='0' else state<= dopenwait2; end if;when dopenwait2=> if dclosem='1' then state<= dopenwait9; dclosem<='0' elsif ddelaym='1' then state<= opendoor; ddelaym<='0' else state<= dopenwait3; end if;when

22、 dopenwait3=> dopenled<="011110" state<= dopenwait4; when dopenwait4=> if dclosem='1' then state<= dopenwait9; dclosem<='0' elsif ddelaym='1' then state<= opendoor; ddelaym<='0' else state<= dopenwait5; end if;when dopenwait5=>

23、dopenled<="111111" state<= dopenwait6; when dopenwait6=> if dclosem='1' then state<= dopenwait9; dclosem<='0' elsif ddelaym='1' then state<= opendoor; ddelaym<='0' else state<= dopenwait7; end if;when dopenwait7=> dopenled<=&quo

24、t;011110" state<= dopenwait8;when dopenwait8=> if dclosem='1' then state<= dopenwait9; dclosem<='0' elsif ddelaym='1' then state<= opendoor; ddelaym<='0' else state<= dopenwait9; end if;when dopenwait9=> dopenled<="001100" sta

25、te<= dopenwait10; when dopenwait10=> if dclosem='1' then state<= dopenwait9; dclosem<='0' elsif ddelaym='1' then state<= opendoor; ddelaym<='0' else state<= dclse; end if;when dclse=> dopenled<="000000" if dat>"0000" t

26、hen state<= run; else state<= stop; end if;when stop => if dat>"0000" then state<= run; elsif ddelaym='1' then state<= opendoor; ddelaym<='0' else state<= stop; end if; end case; end if;if position=1 then nowfloor<="0001" floorled<=&q

27、uot;0001" elsif position=2 then nowfloor<="0010" floorled<="0010" elsif position=3 then nowfloor<="0011" floorled<="0100" elsif position=4 then nowfloor<="0100" floorled<="1000" else nowfloor<="0000" floo

28、rled<="0000" end if; end process state_trans;end bhv;綜合實(shí)現(xiàn)模塊：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity finalctrol is port( clk: in std_logic; up1,up2,up3,stop1,stop2,stop3,stop4,down4,down3,down2: in std_logic; ddelay,dclose: in std_logic; upled,downled: out std_logic; floorled,nowfloor: out std_logic_vector(3 downto 0); dopenled: out std_logic_vector(5 downto 0);end finalctrol;