超大規(guī)模集成電路與系統(tǒng)導(dǎo)論(答案)

1、Solutions Manualto accompany the textIntroduction to VLSI Circuits and Systemsby John R UyemuraPreliminary DraftJune, 2001Note: This is the first draft of the Solutions Manual that was transcribed from tha author?s hand-scratched notes. It has hot been proofread, nor have the solutions been checked

2、for completeness or accuracy. While most of them are reasonably accurate, errors will be found. The final version of the Solutions Manual will be available in the near fiiture.JOHN WILEY & SONS, INC.NEW YORK CHICHESTER WEINHEIM BRISBANE SINGAPORE TORONTO1Chapter 1There are no problems in Chapter

3、 1.Chapter 22.1 The nFET can pass any voltage in the rangewhere(VG - V) withVc the voltage on the gate. With the stated values. Vrna>r 5-0.7=4.3 V. IfthenVout is restricted to However, the nFET passes any voltage This givesthe following answers.(a) 加2匕 =2V;(b) = 4.5 V. Vout = 4.3 V is limited;(c)

4、 %=3.5 V. % = 3.5 V;(d) V(n=0.7V, =0.7 V.The main idea is to show the effect of the threshold loss through an nFET.2.2 For < Vmax 9 then the input voltage is transmitted through the chain. If > Vmax > then a threshold drop occurs in the first transistor (only) and Vmax makes it to the outpu

5、t. With the stated values,3.3-0.55=2.75 V This gives the following answers(a) Vin= 2.9 V. V0llt 2.75 V (Hmited);(b) Vin= 3.0 V. Vout 2.75 V (limited);(C) Vin= 14V. %= 1.4 V;(d)心=3.1 V, Voat 2.75 V (limited).2.3 The output of the upper FET Ml (with Va applied) is used to control the gate voltage Vc o

6、f the lower transistor M2 (with applied). Both are susceptible to threshold voltageProblem 2.3#drops so that max(VG) = (VDD f) and max(Vout) = (Vc 爍).Using max(VG) = (3.3-0.6 )=2.7 V gives the following results(a) %=33 V, Vb= 3.3 V: VG= 2.7 V so Vout 2.7 0.6 = 2.1 V.(b) V = 0.5 V, 3 V: VG= 0.5 V so

7、M2-is in cutoff. This makes Voul an unknown value since the transistor is an open circuit. '(c) V=2 V, Vb= 2.5 V:VG= 2 V so 2 0.6 = 1.4 V.(d) %=33 V, Vb 1.8 V: VG=2.7 Vso Vout 1.8 V.2.4 NAND3 gate using an 8:1 MUX is shown in drawing below with Prob. 2.5 solution.2.5 NOR3 gate using an 8:1 MUX i

8、s shown in drawing below with Prob2.4 solution.° 8:112G鴉'w 0T 1T 2*1M *1 34丁一56oh7abcOmputProblem 2.4 NAND 3Problem 2.5 NOR 32.6 The drawings below illustrate the XOR2 and XNOR2 MUX-based designs. To implement the full-adder sum expression, we uses = (a b) c3which shows that s can be calcul

9、ated using 2 XOR gates This is shown in Figure (c) below.(a) XOR2(b) XNOR2<c)sum#Problem 2.62.7 Rewrite the function to readf = a- (b+ c)+ b - dto show that the function can be reduced to a simplified form The gate is shown in the drawing Problem 2.7#The final design depends on the algebraic form

10、 selected. One approach is to first expand the terms as5(a+ b )(a + c) = a + a b+a c+b c = a (1 + b) + a c +c.二=a-(l + c) + bc、=a + b cThenh = (a + b- c) (b+ d)=ab+ bc+a d+bdc=a - (b+ d) + bc(l +d)=a (b+ d) + b cThis form of the logic function gives the AOI gate shown. Note that there are variations

11、 possible.Problem 2.8b2.8 Writeg = x (y + z) + y = x y + x z + y = y (1 + x) + xz = y + x zThis gives the simplified logic diagrams, which are then used to design the logic gate as shown nFETszy2.10J WriteF = a+b c+a bc = a (1 + b c)+bc = a+ beAfter reducing we see that this is the same circuit as f

12、or Problem 2.4 with the inputs relabeled. This is shown for completenessnFETspFETs#Problem 2.10#72.11J The pFET logic diagram and resulting gate are shown.pFET Logic 丄 FdVDDProblem 2.112.12 Solution is shown(a) nFETs(b)pFETsVDDProblem 12.12#(2.13 The logic expression ish亍無(wú)(gz+w)二士 x (y + z+w)=無(wú)(y+ z

13、) w=x + (y + z) - wThis leads to the nFET array shown The circuit can be checked using series-parallel Structuring-Problem 2.13Xy#This example shows how the pFET logic equations can be used to describe a pFET network. The relationship to nFET equations is through the DeMorgan relations2.14 The 4:1 c

14、ircuit directly illustrates how TGs are used in switching.Problem 2.14SiSq2.15 The logic equation can be written asJ = a-s+ b swhere a and b are the inputs, and s. s are the controls An AOI22 gate would produce an output ofF = AX +so we assign a = A. b = X = £ and Y = s and add an inverter. It

15、is important to remember that the location of the ports define how the output function is formed.A X E y AOI 22AOI 22Primitive (ports locations define inputs)Wired as 2:1 MUX2.16J This can be designed by using two input 2:1 MUXes that are controlled by s0> and the MUXing the outputs by a 2:1 that

16、 is controlled by s】Problem 2.162-17 The period isrw= 476 ps9Why such an easy problem? To illustrate the time frame that logic gates in a high-speed digital system must operate As we will see in Part 2. fast circuits (short logic delays) can be difficult to design 218 The smallest clock frequency is

17、fmtn = = 2(0120) = 4HZ While this is very slow, it does show that the clock cannot be idled.Chapter 33.1 The resistance of the line is given by Riine = Rsn where the number of squares can be divided into normal" straight line contributions and corners Let nc be the contribution of a corner squa

18、re The number of square is given by tracing the line from A to B asn = 15+ nc+ 12 + nc+ 14 + nc +4+ nc +22+9 = 76 + 56nc = 79.125soR = 25(79.125) = l,978.125i232The line resistance is = Rsrt Fdor the polysilicon line 心 ne = 25(器卜 1375Q while the metal line is尸 0°8(鬻)=3.24Q which is the smallest

19、.3.3(a) The sheet resistance isRs =辛= Q = o.33Qt (1200x103(b) The number of squares is given by125n = 156.25 squaresO.oso that the line resistance is10Rllne = (0.33)(156.25) = 52.08Q3.4JWe have units of the RC product of RC = QF=気岳卜另=辛=sec sec-which shows that t has units of sec as stated 3.5 (a) Us

20、e the line resistance formula(b) The line capacitance is%(3l) = (39)(8854xl(r")(05xiy4)(40xloY)Tox1000x10®=6.906 fF(c) The line time constant ist = RlineCline = (2000)(6.906xl015) = 13.81 ps3.6 (a) For n-type material,nn0 = Nd = 4xio"cm y(b) The hole density isPn0 = S =爲(wèi))=525.6 cm(c)

21、The electron mobility iscc 1380-92小An = 92 +；八 o8i = 433 cm2/V-sec4xl017 )113x10】7丿while the hole mobility is= 47.7(92) + 495 - 47-7_ = 135.9 cm2/V-sec/57 4x10】J.6X1014,The mobility is then given by1 +a = q(gnn + gpp)«qgnnn = 27.71 (Q-cm since the majority electron concentration dominates.we3.7

22、 Na> N& so the material is p-type. The majority carrier density is Ppo = Nd-Nd = 5.98x10怡cm 7 and the minority carrier density is5 =訂篇:黑)=3523.8 (a) We have carrier densities of p2pp0 - Nd = 4xl014cm y Hpo25 = 5.26xl05cm "3PpO(b) The mobilities are gn = 1373-36 and = 485.6 cm2/V-sec so t

23、hat the conductivity is calculated froma = (1 -6x10*19)(5-26x105)( 1373.36) + (4xl014)(485.6)This givesa = 0.31 p 二(1/a) = 32.17Q-cm(c) The resistance is尺 JIOOXIO)(乎,17)亠 32.170 lxlO-83.9 (a) Start with(b) Differentiate:需=馳搭+M= _gn+如=oso we require(c) The last equation shows that the highest resisti

24、vely material is slightly p-type.#13-10 (a) This isCox = p5 =(b) k'n =畑 C“ = 214.86 pA/V2(c) Pn = k9n(w/u = 1.719 mA/V2(3.9) (8.85警0»)= 3 837xio.7 p=90xl(T”cm2#13= J 3)(澧骨=172.65gA/V23.11 pn = k9n (W/L) with10x10)(a) pn = k9n (W/L) = 172.65(10/0.5) = 3.453 x 10*7 A/V2. The resistance is Kn=

25、 111.39 Q (b) The resistance is reduced toRn = = 50.63Q(1.7265xlO6/|j(3.3 - 0.8)3.12 (a) kp = gp C“so we calculate"(39)(8854xlCT】4)、11.5x10-7=66.06J1A/V2The resistance is then given byRp = = 216.25。(66.06x10)(詢(3.3 一 0.8) 3.13 Srt withcox = 363xl(f7j oxcm(a) k9n = e Cox- 196.28 pA/V2 and k9p =

26、Pp C&= 79.97 pA/V2 With the aspect ratios we have Bn = 6.73 mA/V2 and Bp = 2.74 mA/V2 so that Rn = 56.1 Q and Rp = 142.48 Q using the formulas.(b) Rp = 0.8 Rn so£(3.3-0.65) = 44,8852orPp = 8.408x10-3 = 爲(wèi) which gives the value of W = 36.8 gm needed for the pFET.3.14 The function isOut = x z-

27、(y+ iv)This leads to the following circu辻.#VDDGnd#Problem 3.14143-15 The function isF = a b; c+ ad = a(b c+d)i.Problem 13.15#3«16 The OAI function isg = (a+ b) (c+ a) eThis is obtained from the CMOS circuit shown below The placement of the inputs has be chosen to facilitate the layout.b aVDDD V

28、DJ GndProblem 13.16) Circu辻3.17 Expanding givesg = (a+ b) *c + d) £=(ac+ dd+ b： c+ b：d) e=ac e + ad £+b ce+b d£The third line is an expanded AOI form, but uses excess transistors This can be seen in the circuit below Although we could do a somewhat messy layout, of the gate as-is, we

29、can see by inspection that the expanded AOI form is not an efficient implementation of the logic function.Problem 3.173.18 Yes. this is a functional gate. The function is as can be verified by tracing the circuit319 We start withg = a b c+dThe CMOS circuit and layout are drawn below.FT黃 A A A.：Probl

30、em 3-19Chapter 4There are no problems in Chapter 4.Chapter 5There are no problems in Chapter 5. However, the concepts can be illustrated by assigning layout problems using a CAD tool set. A suggested list of simple structures isan nFET and a pFET with a minimum aspect ratio; scaled FETs; series conn

31、ections that share drain/source regions for 2 FETs and 3 FETs: minimum size inverter; NAND2 and NOR2 gates with standard size transistors; a simple AOI and OAI gate.#Chapter 6:6.1 (a) The oxide capacitance per unit area isC°x =竺=(3.9)(§.8鬥0“4) = 3 45xl0-7 F = 3.45弋 匕l(fā)OOxlO*8cmp.m2(b) k 二片

32、C“ = 189.92 |1A/V2 and k9p 二如 C“ = 75.51 A/V26.2% = 110 (10/.35) = 3.143 mA/V2(a) sat= 2 -0.7 = 1.3 V > Vds= 1 V so the transistor is nonsaturated The current isID =- l2) = 2.51mA(b) Now Vsat = 2 07 = 1.3 V <VDS = 2 V so the transistor is saturated. The current is#16.3(a) Sot = 1 -0.76 = .24 V

33、 < VDS 1 V so the transistor is saturated. The current is0.242 = 6624"#Q)叫at = 1 24 V < VDS so the transistor is saturated with a currentID =(甥la?= .77mA(cWsat = 2.24 < Vds= 2.5 V so the transistor is saturated with2.242 = 5.77mA6.41(a)k' = (220)(3,9)(8,854g1014) = 126.61 xlO-6 &qu

34、ot;60x10V2耳=kp (W/L) = kp (12)=1.519 mA/V219The resistance is1Rd = = 254.7Q(l519xl()Y)(33-07)6.5 Start with(39)(8854xlOr120x082.878x10*7-2cm#(a) The body bias coefficient is calculated from2qEs(N aso丫 =血(11.8)(8.854xl0l)(8xKT巧=Q 0568yl -2.878X10"6.6rThe drawn channel length is L9 = 0.5jim, so t

35、hat electrical channel length is given by(a) We need2I0J = 2(0026)ln。®= 0.568V1 L = 0.5 - 2(0.05)二 0.4 jim. The area of the gate is Ac = L'W = (6)(0.5) gm2 = 3 gm2. The gate capacitance is therefore1.45X1OFor hand estimates, we takeThenTn = TOn + S3n )so using the equation with a body bias

36、of 2 V applied givesVT = 0.55 + (0.0568)(-568 - 70?568) = 0.598V(b) Now we haveVT = 0.55 + (0.0568)(73368 - 70368) = 0.614V so that V sot = 3-0.614 = 2.386 V < VDS The FET is saturated, so】d =2.3862 = 442.3 IgACgs = Cgd = Cg = 4.05 fFFor the n+ capacitance we have a zerob逗s value ofCn> = (0.86

37、)(2.05)(6) + (0.24)2(2.05 + 6 = 14.442fFwhere we have combined the bottom and sidewall contributions. The total capacitance at the drain or source isCD = CGD + CDB = 14.442 + 4.05 = 18.492fF = Csby adding the contributionsThe resistance is盼1(150X10*6(5-0.6)iom6.7JSPICE lisUng of the nFETnFET ModelM1

38、 20 10 0 0 nfet L=0.5U W=6U AD=18P PD=16U AS=18P PS=16U.MODEL nfet NMOS (KP=150U VTO=0.6TOX=1.28E-8 CJ= 8.6E-4 CJSW=2.4E-10)A nested DC command can be used to generate the I-V curve This requires that we add drain and gate voltages of the formVD 20 C 5voltsVG 10 Civolts DC VD0 5 0.1 VG 0 5 0.1VG 10C

39、 Ivolts6.8The poly resistance is estimated by including only the actual FET geometry asRpoiy =(26)磊=312Qwhile the n+ resistance isR” = (30)警=10.25QThis shows that is small, but Rgy can get large.21169。)卩50 = VGSVDSso the transistor is saturated(b) Compute/D = (1迎2詳)(5_o.65)2 = 45.4 mAThe resistance

40、at this point isRn =學(xué)=-.=110Qjd 45.4xlO'J(c) Using the linearized approximationRn 二 = 47.89Q(48xlCf3)(5-065)so that the LTI estimate is smaller than the actual value.6.10JWehavek-n(W/L)(VGS-VTn)so=4.051=1Vm) - (100x10)(950)(3.3-7)Chapter 77.1 The p-ratio isso that the midpoint voltage is33-08 +

41、yT7(07)1 + VL7=1.48V7.2 Computeso#Pn _ SW/5 = (W/L)nP； _ ©(W/L)p _(W7L)；The two aspect ratios are related by 二(W/L)p = 1.39(W/L)n7.3J (a) The transconductance ratio isPn 2.11.162The midpoint voltage is then=5-0.7+夕要(0.6) = 2.378V M 1 + VTT62(b) The resistances areRn =扌=108.23Q(2.1x10*3)(5-0.6)r

42、 = 2 = 129.2Q(1.8xl0)(5-0.7)(c) The high-to-low and low-to-high times without any external load aretHL = 2.2RnCout = 2.2( 108.23)(74x1()75) = 17.62ps tLH = 2.2RpCout = 2.2( 129.20)(74x10")= 2103ps(d) With the external load. Cout = 74 + 115 = 189 fF. ThentHL = 2.2RnCout = 2.2( 108.23)(189xl0&quo

43、t;15) = 45.0pstw = 2.2RpCout = 2.2( 129.20)( 189X10*15) = 53.72ps(e) In general, we can write the equations astHI = 17.62 + 0.238CltLH = 21.03+ 0.284Clwhere CL is in fF.7.4 The transconductance ratio isPn - 150(4) _ 1 25Pp_ 60(8) - 125The midpoint voltage is then=5-025(06) = 2.347V1 + VE25237.5 The

44、(electrical) channel length is L = 0.8 p.m» and the drawn channel length Is E =1.0 gm.(a) The input capacitance isC(n = (20)( 1)(8+ 4) = 32.4fF(b) The LTI resistances areRn = z = 303.03Q(150x10"6)(4/0.8)(5-0.6)= z =387.6Q(60x10“)(8/08)(5 - 0.7)(c) Cou£ = 0+ CL = 50.45+80= 130.45 fF. s

45、o the switching times arehl = 2.2RnCout = 87.04ps= 22RpCout = 111.24ps17.6 SPICE simulation7.7 (a) We writeso5-0.7 + (動(dòng)她0.6)=2.77V#(b) For a NOT gate with the same relative dimensions.5-07+“(06) = 2 13V1 + 727.8 The midpoint voltage for the simultaneous switch case is3.3-0.8 + 層(0.65：1.47V7.9J For a

46、 NAND3 gate, we follow the jgame treatment as in the text to write the KCL equationR (W vM-vTn V 卩卩_-Ifl丿Problem 7.10C°ut=63.16gA/V2120(4” 2.4-0.55 A29-U- 2.4-0.9；7.10 (a) The resistance of a FET isRn = J = 192.3m(2xl0)(3.3-0.7)The time constant for the output capacitor is obtained from the Elm

47、ore formula asTn = 3RnC°ur+2心。2 + RnG=Rn3Cout + 2C? + C】=192.311(3) 130 + (2)36 + 36xl0"15=95.77 ps(b) If we ignore C】and QTn = 3RnCout = 75 ps which gives a percentage error of% Error =障謬另7弓 x 100 % = 21.6 %257.11 The circu辻 and the relative device sizes are shown in the drawing.AUpFETs h

48、ave thesame sizeBp = 2 BpnFETs on the left are sized withnFETs on the right are sized with盼2 %Problem 17.127.12 The circuit and the relative device sizes are shown in the drawing.#Problem 7.1226Chapter 88.1 The general form of the rise time equation is =tr0 + aCiso the information gives the two equa

49、tions123.75xl012 = tr0 + a(100xl0"15) 138-6xl0-12 = tr0 + a(115xl0"15) (a) Subtracting the top equation from the bottom one gives 1485x10“2 = a(15xl0'15) so<a = 0.99x10s = 2.2“Thus. Rn = 450Q.(b) Use either equation to find 気123.75X10*12 = tr0 + a(100xl0"#15) = tr0 +990(1 OOxlO

50、"15)sotr0 = 2.475x10“ = 2.2RnCFET.This gives2.475X10"11990=25fFThus, we can write the general expressionstr = 24.75 + 0.99Cl ps =where CL is in units of fF.(c) With a scaling factor of 3.2x . tis tiie same but a is scaled to (.99/3.2)=0.309 This gives the expressiontr = tr= 24.75 + 0309Ci

51、ps8.2 The delay through the 3-stage chain isJ = 2tr +wheretr = 430 + 3.68(45) = 595.6 ps ty = 300 + 2.56(45) = 415.2 psso27td = 2(595.6) + 415.2 = 1.606 ns8.3 We estimate the delay by adding timesJ = tj, nof + nor2 + tj nand2 + r. not where we assume that a switch occurs at every gate. Using the for

52、mulas for the specified m-values givestd - t/o + anu(min)+(3tr0 + 2apu(4Cmin) + 3ty0 + 2anu(3Cm(n)+ S+昔Grouping,80td = At/o + 8anuCmm + 4久)+ 可 OtpuCmfn&4(a) The input capacitance isCin = COXLW( 1 + r) = Cox(0.4)(2.2)( 1 + 2.6) = 25.344 fF(b) The number of stages isInf 38X10 12 15 = 7.31V25.344xl

53、O15J#so we select N= 7.(c) The reference resistance is = 1725 Q so R2.2x= (1725/2.2) = 784.1 Q Since#the total delay isTd = NSzr = 7(2.85)(784.1)(25.344x1()75)= 396.45 ps for the simplified analysis8.5 We calculate the number of stages asIn.50X10*15；40xl0"12)=ln(800) = 6.68#so we select N= 6 The scaling factor is28so that we start with pj (known), and calculate the driver sizes as02 =83 = 9%. P4 = 27Pj B5 = 8101.佩=243仇8<GTbe line capacitance is