基于VHDL的實用CPU創(chuàng)新設(shè)計

1、第第9 9章章9.1 9.1 頂層系統(tǒng)設(shè)計頂層系統(tǒng)設(shè)計 9.1.1 169.1.1 16位位CPUCPU的組成結(jié)構(gòu)的組成結(jié)構(gòu) 圖圖9-1 16位位CPU結(jié)構(gòu)框圖結(jié)構(gòu)框圖 2. 2. 頂層文件的原理圖設(shè)計頂層文件的原理圖設(shè)計 圖圖9-2 CPU頂層結(jié)構(gòu)圖（詳細內(nèi)容瀏覽頂層結(jié)構(gòu)圖（詳細內(nèi)容瀏覽www.kx-） （1 1） 運算器運算器ALU ALU 運算器運算器ALU的功能的功能 9.2 9.2 基本硬件系統(tǒng)設(shè)計基本硬件系統(tǒng)設(shè)計Sel 輸入輸入操作操作說明說明0000C=A通過通過PASS0001C=A AND B與與0010C=A OR B或或0011C=NOT A非非0100C=A XOR B

2、異或異或0101C=A + B加法加法0110C=A B減法減法0111C=A + 1加加11000C=A 1減減11001C=0清清0（1 1） 運算器運算器ALU ALU 運算器運算器ALU結(jié)構(gòu)圖結(jié)構(gòu)圖 a15.0b15.0sel3.0c15.0aluinst9.2 9.2 基本硬件系統(tǒng)設(shè)計基本硬件系統(tǒng)設(shè)計6.2.1 6.2.1 運算器運算器ALU ALU 圖圖6-5 運算器運算器ALU結(jié)構(gòu)圖結(jié)構(gòu)圖 6.2 CPU6.2 CPU基本部件設(shè)計基本部件設(shè)計 library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.

3、all;use work.cpu_lib.all;entity alu isport( a, b : in bit16; sel : in t_alu; c : out bit16 );end alu;architecture rtl of alu isbeginaluproc: process(a, b, sel)begincase sel iswhen alupass= c c c c c c c c c c c= 0000000000000000 after 1 ns;end case;end process;end rtl; （1 1） 運算器運算器ALU ALU 運算器運算器ALU的

4、仿真波形的仿真波形 9.2 9.2 基本硬件系統(tǒng)設(shè)計基本硬件系統(tǒng)設(shè)計（2 2） 運算器運算器ALU ALU ALU運算仿真結(jié)果說明運算仿真結(jié)果說明 工作點波工作點波功能選功能選擇擇sel運算類型運算類型輸入數(shù)據(jù)輸入數(shù)據(jù)運算結(jié)果運算結(jié)果cab（1）0000通過通過PASS4567 C=A , C=4567（2）0001與與456723ACC=A AND B= 456723AC = 0124723AC = 0124（3）0010或或456723ACC=A OR B = 456723AC = 67EF723AC = 67EF（4）0011非非4567 C=NOT A = BA98（5）0100異或異

5、或4546723ACC=A XOR B = AB = 456723AC = 23AC = 66CB（6）0101加法加法456723ACC=A + B= 4567+23AC= 6913（7）0110減法減法456735ACC=A B = 4567-35AC =0FBB（8）0111加加14567 C=A + 1 = 4567+1= 4568（9）1000減減14567 C=A 1 = 4567-1 =4566（10）1001清清0 xxxxxxxxC=0000（11）10101111其它其它xxxxxxxxC=00009.2 9.2 基本硬件系統(tǒng)設(shè)計基本硬件系統(tǒng)設(shè)計（2 2） 比較器比較器CO

6、MP COMP 比較器的運算類型比較器的運算類型 t_comp比較類型比較類型操作說明操作說明000eq (等于等于)若若a=b，compout=1001neq (不等于不等于)若若ab，compout=1010gt (大于大于)若若ab，compout=1011gte (大于等于大于等于)若若a=b，compout=1100lt (小于小于)若若ab，compout=1101lte (小于等于小于等于)若若a if a = b then compout = 1 after 1 ns ；else compout if a /= b then compout = 1 after 1 ns;els

7、e compout if a b then compout = 1 after 1 ns;else compout if a = b then compout = 1after 1 ns；else compout if a b then compout = 1 after 1 ns ；else compout if a = b then compout = 1 after 1 ns ；else compout b，compout=0（3）1不等于不等于357A357Aa=b，compout=0（4）1不等于不等于357AEB7Cab，compout=1（5）2大于大于357A1200ab，co

8、mpout=1（6）2大于大于357A357Aa=b，compout=0（7）2大于大于357A4689ab，compout=1（9）3大于等于大于等于357A357Aa=b，compout=1（10）3大于等于大于等于357A4689aab，compout=0（12）4小于小于357A357Aa=b，compout=0（13）4小于小于357A4689ab，compout=0（15）5小于等于小于等于357A357Aa=b，compout=1（16）(17)67其他其他xxxxxxxxcompout=09.2 9.2 基本硬件系統(tǒng)設(shè)計基本硬件系統(tǒng)設(shè)計（2 2）比較器）比較器COMP COMP

9、 比較器比較器COMPCOMP的仿真波形圖的仿真波形圖 9.2 9.2 基本硬件系統(tǒng)設(shè)計基本硬件系統(tǒng)設(shè)計（3 3）控制器）控制器CONTROLCONTROL 控制器控制器CONTROL的實體結(jié)構(gòu)圖的實體結(jié)構(gòu)圖 9.2 9.2 基本硬件系統(tǒng)設(shè)計基本硬件系統(tǒng)設(shè)計library IEEE;use IEEE.std_logic_1164.all;use work.cpu_lib.all;entity control is port( clock，reset ，ready，compout: in std_logic; instrReg : in bit16; progCntrWr，progCntrRd

10、，addrRegWr，addrRegRd，outRegWr， outRegRd : out std_logic; shiftSel : out t_shift; aluSel : out t_alu; compSel : out t_comp; opRegRd，opRegWr，instrWr，regRd，regWr ，rw，vma: out std_logic; regSel : out t_reg ); end control;architecture rtl of control issignal current_state, next_state : state;begin （接下頁）（

11、接下頁）9.2 9.2 基本硬件系統(tǒng)設(shè)計基本硬件系統(tǒng)設(shè)計6.2 CPU6.2 CPU基本部件設(shè)計基本部件設(shè)計 nxtstateproc: process( current_state, instrReg, compout,ready)beginprogCntrWr = 0; progCntrRd = 0; addrRegWr = 0; outRegWr = 0;outRegRd = 0; shiftSel = shftpass; aluSel = alupass; compSel = eq;opRegRd = 0; opRegWr = 0; instrWr = 0; regSel = 000;

12、regRd = 0; regWr = 0; rw = 0; vma aluSel=zero after 1 ns; shiftSel=shftpass; next_state aluSel=zero; shiftSel=shftpass; outRegWr=1; next_state outRegRd=1; next_state outRegRd=1; addrRegRd=1; progCntrWr=1;addrRegWr=1; next_state vma=1; rw = 0; next_state vma=1; rw=0;if ready = 1 then instrWr=1; next_

13、state=execute;else next_state case instrReg(15 downto 11) iswhen 00000 = next_state regSel=instrReg(5 downto 3); regRd=1; next_state regSel=instrReg(2 downto 0); regRd=1; next_state regSel=instrReg(5 downto 3); regRd=1; aluSel=alupass;shiftSel=shftpass; next_state progcntrRd=1; alusel=inc; shiftsel=

14、shftpass; next_state progcntrRd=1; alusel=inc; shiftsel=shftpass; next_state regSel=instrReg(5 downto 3); regRd=1; next_state regSel=instrReg(2 downto 0); regRd=1; alusel=inc;shiftsel=shftpass; next_statenext_state regSel = instrReg(5 downto 3); regRd = 1;addrregWr = 1; next_state vma = 1; rw = 0; n

15、ext_state vma = 1; rw = 0; regSel = instrReg(2 downto 0);regWr = 1; next_state regSel = instrReg(2 downto 0); regRd = 1;addrregWr = 1; next_state regSel = instrReg(5 downto 3); regRd = 1; next_state regSel = instrReg(5 downto 3); regRd = 1; vma = 1;rw = 1; next_state regSel = instrReg(5 downto 3); r

16、egRd = 1;aluSel = alupass;shiftsel = shftpass; outRegWr = 1; next_state outRegRd = 1; next_state outRegRd = 1;regSel = instrReg(2 downto 0); regWr = 1; next_state progcntrRd = 1; alusel = inc; shiftsel = shftpass;outregWr = 1; next_state outregRd = 1; next_state outregRd = 1; progcntrWr=1; addrregWr

17、=1; next_state vma = 1; rw = 0; next_state vma = 1; rw = 0;if ready = 1 then regSel = instrReg(2 downto 0);regWr = 1; next_state = incPc;else next_state progcntrRd = 1; alusel = inc; shiftsel = shftpass;outregWr = 1; next_state outregRd = 1; next_state outregRd=1; progcntrWr=1; addrregWr=1; next_sta

18、te vma=1; rw=0; next_state vma = 1; rw = 0;if ready = 1 then progcntrWr = 1; next_state = loadPc;else next_state regSel = instrReg(5 downto 3); regRd = 1; （接下頁）（接下頁）6.2 CPU6.2 CPU基本部件設(shè)計基本部件設(shè)計 opRegWr = 1; next_state opRegRd = 1; regSel = instrReg(2 downto 0);regRd = 1; compsel = gt; next_state opReg

19、Rd = 1 after 1 ns; = 1; regSel = instrReg(2 downto 0); regRd = 1; compsel = gt;if compout = 1 then next_state = bgtI5;else next_state progcntrRd=1; alusel=inc; shiftSel=shftpass; next_state progcntrRd = 1; alusel = inc; shiftsel = shftpass;outregWr = 1; next_state outregRd = 1; next_state outregRd =

20、 1;progcntrWr = 1; addrregWr = 1; next_state vma = 1; rw = 0; next_state vma = 1; rw = 0;if ready = 1 then progcntrWr = 1; next_state = loadPc;（接下頁）（接下頁）6.2 CPU6.2 CPU基本部件設(shè)計基本部件設(shè)計 else next_state regSel = instrReg(2 downto 0); regRd = 1; alusel = inc;shiftsel = shftpass; outregWr = 1; next_state out

21、regRd = 1; next_state outregRd = 1; regsel = instrReg(2 downto 0);regWr = 1; next_state progcntrRd = 1; next_state progcntrRd = 1; addrRegWr = 1; next_state vma = 1; rw = 0; next_state vma = 1; rw = 0;if ready = 1 then instrWr = 1; next_state = execute;else next_state progcntrRd=1; alusel=inc; shift

22、sel=shftpass; next_state progcntrRd = 1; alusel = inc; shiftsel = shftpass;outregWr = 1; next_state outregRd = 1; next_state outregRd=1; progcntrWr=1; （接下頁）（接下頁） addrregWr=1; next_state vma = 1; rw = 0; next_state vma = 1; rw = 0;if ready = 1 then instrWr = 1; next_state = execute;else next_state ne

23、xt_state = incPc;end case;end process;controlffProc:process(clock, reset)begin if reset = 1 then current_state = reset1 after 1 ns;elsif clockevent and clock = 1 then current_state = next_state after 1 ns; end if;end process;end rtl; 9.2 9.2 基本硬件系統(tǒng)設(shè)計基本硬件系統(tǒng)設(shè)計（4 4）寄存器）寄存器寄存器寄存器REG的實體結(jié)構(gòu)和的實體結(jié)構(gòu)和RTL圖圖 寄存器

24、寄存器REG REG a15.0clkq15.0reginst49.2 9.2 基本硬件系統(tǒng)設(shè)計基本硬件系統(tǒng)設(shè)計6.2.4 6.2.4 寄存器與寄存器陣列寄存器與寄存器陣列 1 1寄存器寄存器REG REG library IEEE;use IEEE.std_logic_1164.all;use work.cpu_lib.all;entity reg isport( a : in bit16; clk : in std_logic; q : out bit16);end reg;architecture rtl of reg isbeginregproc: processbeginwait until clk event and clk = 1;q y y y y y y = 0000000000000000 af