串行掃描顯示電路設(shè)計(jì)---文本資料

1、輸入時(shí)鐘inlck為50Mhz ,經(jīng)分頻為1hz,再進(jìn)行0F范圍計(jì)數(shù)，計(jì)數(shù)的結(jié)果分 別在seg3-seg1睦8個(gè)串行數(shù)碼管顯示；8個(gè)數(shù)碼管受74138譯碼器的控制；189,190,191,192,193,195,196 , 197串行掃描顯示電路設(shè)計(jì)1 .實(shí)驗(yàn)?zāi)康? .通過用VHDL語(yǔ)言設(shè)計(jì)串形掃描顯示電路進(jìn)一步掌握使用VHDL方法。2 .熟悉使用CPLD/FPGA實(shí)驗(yàn)箱的數(shù)碼管進(jìn)行顯示。2 .實(shí)驗(yàn)儀器1. PC機(jī)一臺(tái)2 . KHF-1/KHF-2/KHF-3/KHF-4/KHF-5 CPLD/FPGA 實(shí)驗(yàn)開發(fā)系統(tǒng)一套。三、實(shí)驗(yàn)要求1 .預(yù)習(xí)串行掃描顯示的原理2 .復(fù)習(xí)教材相關(guān)內(nèi)容。3 .用

2、硬件描述語(yǔ)言進(jìn)行電路設(shè)計(jì)。四、實(shí)驗(yàn)內(nèi)容及實(shí)驗(yàn)步驟1 .串形掃描顯示電路設(shè)計(jì)原理a,b,c,d,e,f,g, p 段2 .編譯。3 .分配管腳。4 .編譯。5 .啟動(dòng)下載軟件進(jìn)行下載。五實(shí)驗(yàn)代碼library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity tcx isport(inclk:in std_logic;outb:out std_logic_vector(7 downto 0);outa:out std_logic_vector(2 downto 0);end tcx;architectu

3、re arch_tcx of tcx issignal ma:std_logic_vector(2 downto 0);signal mb:std_logic_vector(3 downto 0);signal fp:std_logic_vector(24 downto 0);signal f:std_logic;beginprocess(inclk)beginif(inclk'event and inclk='1')thenif fp=24999999 thenfp<="0000000000000000000000000"f<=not

4、f;elsefp<=fp+1;end if;end if;end process;process(f)beginif(f'event and f='1')thenma<=ma+1;mb<=mb+1;end if;end process;outa<=ma;with mb selectoutb<= "10110000"when"0001",-1"11101101"when"0010",-2"11111001"when"0011"

5、;,-3"10110011"when"0100",-4"11011011"when"0101",-5"11011111"when"0110",-6"11110000"when"0111",-7"11111111"when"1000",-8"11111011"when"1001",-9"11110111"when"1010",-A"10011111"when"1011",-B"11001110"when"1100",-C"10111101"when"1101",-D"11001111"when"1110",-E"11000111"when"1111",-F"11111110"when othe