基于VHDL語言的交通燈設(shè)計程序

1、library ieee; -分頻電路entity fen isport(clk:in std_logic;clk1:out std_logic; -實體端口聲明end fen;architecture fen_arc of fen is -結(jié)構(gòu)體描述開始beginprocess(clk -進程開始variable cnt:integer range 0 to 99;beginif clk'event and clk='1' then -高電平到if cnt=99 thencnt:=0; -0開始計數(shù)clk1<='1' -輸出高電平elsecnt:

2、=cnt+1; -加計數(shù)clk1<='0' -輸出低電平end if;end if;end process; -進程描述結(jié)束end fen_arc; -結(jié)構(gòu)體描述結(jié)束-A路控制library ieee;entity Alu isport(clk:in std_logic;ar,ag,al,ay:out std_logic; -紅、綠、黃、左轉(zhuǎn)timas,timag:out std_logic_vector(3 downto 0; -十位、個位計數(shù)end Alu;architecture alu_arc of Alu istype rgly is(red,green,lef

3、t,yellow; -燈亮順序為紅、綠、左轉(zhuǎn)、黃beginprocess(clkvariable a:std_logic; -變量聲明variable ts,tg:std_logic_vector(3 downto 0;variable state:rgly;beginif clk'event and clk='1' then -高電平case state iswhen green=>if a='0' then -綠燈狀態(tài)ts:="0010" -十位計2tg:="0100" -個位計4a:='1

4、9;ag<='0'ar<='1'elseif not(ts="0000" and tg="0001" then -若計數(shù)值不為1if tg="0000" then -若個位為1tg:="1001" -個位置9ts:=ts-1; -十位自減1 elsetg:=tg-1; -個位自減1 end if;elsets:="0000"tg:="0000"a:='0'state:=left; -轉(zhuǎn)為左轉(zhuǎn)燈狀態(tài)end if;end

5、 if;when left=>if a='0' then -左轉(zhuǎn)燈ts:="0000" -十位置0tg:="1001" -個位置9a:='1'aL<='0'ag<='1'elseif not (ts="0000" and tg="0001"thenif tg="0000" thentg:="1001"ts:=ts-1;elsetg:=tg-1;end if;elsets:="0000&

6、quot;tg:="0000"a:='0'state:=yellow;-轉(zhuǎn)為黃燈狀態(tài)end if;end if;when yellow=>if a='0' then -黃燈狀態(tài)ts:="0000" -十位置0tg:="0100" -個位置9a:='1'ay<='0'aL<='1'elseif not(ts="0000" and tg="0001" thenif tg="0000"

7、 thentg:="1001"ts:=ts-1;elsetg:=tg-1;end if;elsets:="0000"tg:="0000"a:='0'state:=red;end if;end if;when red=>if a='0' then -紅燈狀態(tài)ts:="0011" -十位置3tg:="1001" -個位置9a:='1'ar<='0'ay<='1'elseif not(ts="0

8、000" and tg="0001" thenif tg="0000" thentg:="1001"ts:=ts-1 ;elsetg:=tg-1;end if;elsets:="0000"tg:="0000"a:='0'state:=green;end if;end if;end case;timas<=ts;timag<=tg;end if;end process;end alu_arc;-B路燈控制程序。與A路相似。library ieee;entity

9、 blu isport(clk:in std_logic;br,bg,bl,by:out std_logic;timbs,timbg:out std_logic_vector(3 downto 0;end blu;architecture blu_arc of blu istype rgly is(green,left,yellow,red; -燈亮順序為綠、左轉(zhuǎn)、黃、紅beginprocess(clkvariable a:std_logic;variable ts,tg:std_logic_vector(3 downto 0;variable state:rgly;beginif clk&#

10、39;event and clk='1' thencase state iswhen green=>if a='0' thents:="0010"tg:="0100"a:='1'bg<='0'br<='1'elseif not(ts="0000" and tg="0001" thenif tg="0000" thentg:="1001"ts:=ts-1;elsetg:=tg-1;

11、end if;elsets:="0000"tg:="0000"a:='0'state:=left;end if;end if;when left=>if a='0' thents:="0000"tg:="1001"a:='1'bL<='0'bg<='1'elseif not (ts="0000" and tg="0001"thenif tg="0000" th

12、entg:="1001"ts:=ts-1;elsetg:=tg-1;end if;elsets:="0000"tg:="0000"a:='0'state:=yellow;end if;end if;when yellow=>if a='0' thents:="0000"tg:="0100"a:='1'by<='0'bL<='1'elseif not(ts="0000" and t

13、g="0001" then if tg="0000" thentg:="1001"ts:=ts-1;elsetg:=tg-1;end if;q:out std_logic_vector(6 downto 0; end dispa; architecture xuan_arc of dispa is signal d:std_logic_vector(3 downto 0; signal sel:std_logic_vector(2 downto 0; begin pi:process(clk variable tmp:std_logi

14、c_vector(2 downto 0; begin if clk'event and clk='1' then if tmp="000"then tmp:="001" elsif tmp="001" then tmp:="100" elsif tmp="100" then tmp:="101" elsif tmp="101" then tmp:="000" end if; end if; sel<=tmp

15、; end process pi; po:process(sel begin case sel is when "000"=>z<="1110"d<=d0; -B 路個位計數(shù) when "001"=>z<="1101"d<=d1; -B 路十位計數(shù) when "100"=>z<="1011"d<=d2; -A 路個位計數(shù) when others=>z<="0111"d<=d3; -A

16、路十位計數(shù) end case; end process po; p1:process(d begin case d is when "0000" =>q<="1000000" when "0001" =>q<="1111001" when "0010" =>q<="0100100" when "0011" =>q<="0110000" when "0100" =>q<="0011001"