出租車計費器設計(部分)

1、頁眉.出租車計費器出租車的出現(xiàn)給人們的生活帶來了極大的便利，日漸成為城市交通工具中重要的成員之一。本實驗以日常所見的出租車計費器為設計目標，實現(xiàn)其計程、計時、預置、計費等功能。一、系統(tǒng)設計要求設計一個滿足日常生活所需功能的出租車計費器。該計費器能實現(xiàn)計費功能。車起步開始計費，首先顯示起步價，起步費為 3.00 元，車在行駛 3KM 以內(nèi)，只收起步價。車行駛超過 3KM 之后，沒 KM2 元，車費依次累加。當總費用達到或超過 40 元時，每 KM 收費 4 元。當遇到紅燈或客戶需要停車等待時，則按時間計費，計費單價為每 20s 收費 1 元。實現(xiàn)計費器預置功能， 能夠預置起步費、 每公里收費、

2、車行加費里程、 計時收費等。可以模擬汽車行駛、停止、暫停等狀態(tài)，并根據(jù)不同狀態(tài)進行計費。以十進制顯示出租車行駛路程與車費。二、系統(tǒng)設計方案分析系統(tǒng)設計要求不難得知，整個出租車計費系統(tǒng)按功能主要分為速度模塊、計程模塊、計時模塊和計費模塊。速度模塊：通過對速度信號sp 的判斷，決定變量kinside 的值。 kinside 即是進行100m 所需要的時鐘周期數(shù)，然后每行進100m，則產(chǎn)生一個脈沖clkout 。計程模塊：由于一個 clkout 信號代表行進 100m，故通過對 clkout 計數(shù)，可以獲得共行進的距離 kmcount。計時模塊：在汽車啟動后，當遇到顧客等人或紅燈時， 出租車采用計時

3、收費的方式。通過對速度信號 sp 的判斷決定是否開始記錄時間。當 sp=0 時，開始記錄時間。當時間達到足夠長時則產(chǎn)生timecount 脈沖，并重新計時。一個timecount 脈沖相當于等待的時間達到了時間計費的長度。這里選擇系統(tǒng)時鐘頻率為500HZ， 20s 即計數(shù)值為 1000。計費模塊由兩個進程組成。其中，一個進程根據(jù)條件對enable 和 price 賦值：當記錄的距離達到 3 公里后 enable 變?yōu)?1，開始進行每公里收費，當總費用大于40 元，則單價 price 由原來的 2 元每公里變?yōu)?4 元每公里；第二個進程在每個時鐘周期判斷 timecount 和 clkout 的

4、值。當其為 1 時，則在總費用上加上相應的費用。三、VHDL 編程速度模塊的 VHDL 代碼如下：Library IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;1 / 9頁眉.ENTITY speed ISPORT (clk : IN STD_LOGIC;reset : IN STD_LOGIC;start: IN STD_LOGIC;stop: IN STD_LOGIC;sp: IN STD_LOGIC_VECTOR(2 DOWNTO 0);clkout: OUT STD_LOGIC;);END speed;

5、ARCHITECTURE rtl OF speed ISBEGINPROCESS (clk, reset, stop, start, sp)TYPE state_type IS (s0,s1);VARIABLE s_state: state_type;VARIABLE cnt: integer range 0 to 28;VARIABLE kinside: integer range 0 to 30;BEGINCASE sp ISWHEN “000”=>kinside :=0;WHEN “001”=>kinside :=28;WHEN “010”=>kinside :=24;

6、WHEN “011”=>kinside :=20;WHEN “100”=>kinside :=16;WHEN “101”=>kinside :=12;WHEN “110”=>kinside :=8;WHEN “111”=>kinside :=4;END CASE;IF reset=1THENs_state:=s0;ELSIF (rising_edge(clk) thenCASE s_state isWHEN s0=>2 / 9頁眉.cnt:=0;clkout<= 0;IF start=1THEN s_state:=s1;ELSE s_state:=s0

7、;END IF;WHEN s1=>Clkout<= 0;IF (stop=1)THENs_state<=s0;ELSIF sp=”000”then s_state:=s1;ELSIF cnt=kinside thencnt:=0; clkout<= 1;s_state:=s1;ELSE cnt:=cnt+1;s_state:=s1;END IF;END CASE;END IF;END PROCESS;END rtl;計程模塊的 VHDL 代碼如下：Library IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UN

8、SIGNED.ALL;ENTITY kilometers ISPORT (clkout, reset : IN STD_LOGIC;kmcnt1,kmcnt2,kmcnt3: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END kilometers;ARCHITECTURE rtl OF kilometers ISBEGINPROCESS (clkout, reset)3 / 9頁眉.VARIABLE km_reg: STD_LOGIC_VECTOR(11 DOWNTO 0); BEGINIF reset=1THENkm_reg:=”000000000000”;ELSIF

9、 (rising_edge(clkout) thenIF km_reg(3 DOWNTO 0)= ”1001”THENkm_reg := km_reg +”0111”;ELSE km_reg(3 DOWNTO 0)= km_reg(3 DOWNTO 0)+ ”0001”; END IF;IF km_reg(7 DOWNTO 4)= ”1010”THENkm_reg := km_reg +”01100000”;END IF;END IF;kmcnt1<=km_reg(3 DOWNTO 0);kmcnt2<=km_reg(7 DOWNTO 4);kmcnt3<=km_reg(11

10、 DOWNTO 8);END PROCESS;END rtl;計時模塊的 VHDL 代碼如下：Library IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY times ISPORT (clk : IN STD_LOGIC;reset : IN STD_LOGIC;start: IN STD_LOGIC;stop: IN STD_LOGIC;sp: IN STD_LOGIC_VECTOR(2 DOWNTO 0);timecount: OUT STD_LOGIC;);END times;4 / 9頁眉

11、.ARCHITECTURE rtl OF times ISBEGINPROCESS (clk, reset, stop, start, sp)TYPE state_type IS (t0,t1,t2);VARIABLE t_state: state_type;VARIABLE cnt: integer range 0 to 28;VARIABLE waittime: integer range 0 to 1000;BEGINIF reset=1THENt_state:=t0;ELSIF (rising_edge(clk) thenCASE t_state isWHEN t0=>waitt

12、ime:=0;timecount<=0;IF start=1THEN t_state:=t1;ELSE t_state:=t0;END IF;WHEN t1=>IF (sp=”000”) THENt_state:=t2;ELSE waittime:=0;t_state:=t1;END IF;WHEN t2=>waittime:= waittime +1;timecount<=0;IF waittime <=1000 THENwaittime:=0;timecount<=1;ELSIF stop=1then t_state:=t0;ELSIF sp=”000”

13、thent_state:=t2;ELSE timecount<=0;5 / 9頁眉.t_state:=t1;END IF;END CASE;END IF;END PROCESS;END rtl;計費模塊的 VHDL 代碼如下：Library IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY kmmoney ISPORT (clk, reset, timecount, clkout: IN STD_LOGIC;kmcnt2, kmcnt3, count1, count2, count3: OUT

14、STD_LOGIC_VECTOR(3 DOWNTO 0);END kmmoney;ARCHITECTURE rtl OF kmmoney ISSIGNAL cash: STD_LOGIC_VECTOR(11 DOWNTO 0);SIGNAL price: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL enable: STD_LOGIC;BEGINkmmoney 1: PROCESS (cash,kmcnt2)BEGINIF reset=1THENcash<=”000000000011”;ELSIF (rising_edge(clk) thenIF timecou

15、nt=1THENreg2:<=cash;IF reg2(3 DOWNTO 0)+ ”0001”>”1001”THENreg2(7 DOWNTO 0) := reg2( 7 DOWNTO 0)+ ”00000111”; IF reg2(7 DOWNTO 4) > ”1001”THEN6 / 9頁眉.cash<=reg2+”000001100000”;ELSE cash<=reg2+”0001”;END IF;ELSIF (clkout= 1)and (enable=1)THENIF clkout_cnt=9 THENclkout_cnt:=0;reg2:=cash;

16、IF “0000”&reg2(3 DOWNTO 0)+price(3 DOWNTO 0)>”00001001” THEN reg2(7 DOWNTO 0):=reg2(7 DOWNTO 0)+ ”00000110”+price;IF reg2(7 DOWNTO 4) > ”1001”THEN cash<=reg2+”000001100000”;ELSEcash<=reg2;END IF;ELSEcash<=reg2+price;END IF;ELSEclkout_cnt:=clkout_cnt+1;END IF;END IF;END IF;END PROC

17、ESS;count1<=cash(3 DOWNTO 0);count2<=cash(7 DOWNTO 4);count3<=cash(11 DOWNTO 8);END rtl;頂層模塊的 VHDL 代碼如下：Library IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY top ISPORT (clk, reset, start, stop: IN STD_LOGIC;sp: IN STD_LOGIC_VECTOR(2 DOWNTO 0);7 / 9頁眉.kmcnt1,kmcnt2,kmcnt3,count1,count2,count3: OU

18、T STD_LOGIC_VECTOR(3 DOWNTO 0);END top;ARCHITECTURE rtl OF top ISComponent speed isPORT (clk : IN STD_LOGIC;reset : IN STD_LOGIC;start: IN STD_LOGIC;stop: IN STD_LOGIC;sp: IN STD_LOGIC_VECTOR(2 DOWNTO 0);clkout: OUT STD_LOGIC;);End Component speed;Component times isPORT (clk : IN STD_LOGIC;reset : I

19、N STD_LOGIC;start: IN STD_LOGIC;stop: IN STD_LOGIC;sp: IN STD_LOGIC_VECTOR(2 DOWNTO 0);timecount: OUT STD_LOGIC;);End Component times;Component kilometers isPORT (clkout, reset : IN STD_LOGIC;kmcnt1,kmcnt2,kmcnt3: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);End Component kilometers;Component kmmoney isPORT (clk, reset