《電子技術(shù)數(shù)字基礎(chǔ) Digital Fundamentals》雙語課件PPT-第08章 Counters (1)

1、1Chapter 8 Counters (and the Sequential Logic)2Contentsw Introductionw Analysis of the Sequential Logicw Countersw Design of Sequential Logics38-0 Introductionw The digital electronic logic is classified as the combinational logic and the sequential logic. w (數(shù)字電路分為：數(shù)字電路分為：組合邏輯電路及時(shí)序邏輯電路組合邏輯電路及時(shí)序邏輯電路

2、)w The sequential logic includes the combinational logic section and the memory section.48-0 Introduction The logic diagram for the general sequential logic輸出方程驅(qū)動(dòng)方程狀態(tài)方程58-0 Introductionw The sequential logic is classified as the asynchronous one and synchronous one (異步時(shí)序異步時(shí)序電路和同步時(shí)序電路）電路和同步時(shí)序電路）.w Th

3、e analysis and design of the sequential logic is discussed in this chapter. And the counter is the most useful device.68-2 Synchronous Counter Operation (同步計(jì)數(shù)器）& Analysis of the Sequential Logic（時(shí)序電路分析）w Synchronous (同步同步): Events that have a fixed time relationship with each other.w Synchronous

4、 counter: the counter whose flip-flop (FF) are clocked at the same time by a common clock pulse.78-2-1 Analysis of the Sequential Logicw Whats the function of the following logic diagram?How to analyze this diagram? 88-2-1 Analysis of the Sequential Logic -ProcedureProcedure: 1. Write down the clock

5、 and excitation expressions for each FF.2. Get their state expressions by replacing the logic expression for the FF with its excitation expression.1.1. 寫出每個(gè)觸發(fā)器的時(shí)鐘方程和驅(qū)動(dòng)方程；寫出每個(gè)觸發(fā)器的時(shí)鐘方程和驅(qū)動(dòng)方程；2. 2. 將驅(qū)動(dòng)方程代入觸發(fā)器的特性方程，得到狀態(tài)方程組；將驅(qū)動(dòng)方程代入觸發(fā)器的特性方程，得到狀態(tài)方程組；98-2-1 Analysis of the Sequential Logic -Procedure3. 3. 寫出

6、輸出方程；寫出輸出方程；5. 5. 說明電路的邏輯功能。說明電路的邏輯功能。4. 4. 依次假定依次假定初態(tài)初態(tài), ,計(jì)算計(jì)算次態(tài)次態(tài), ,畫出畫出狀態(tài)轉(zhuǎn)換圖狀態(tài)轉(zhuǎn)換圖( (表表) )或或 時(shí)序波形圖時(shí)序波形圖 。3. Write down the output expression;4. Assume the present state, and analyze the next state, and draw its state diagram (狀態(tài)轉(zhuǎn)換圖狀態(tài)轉(zhuǎn)換圖) /state sequence table(狀態(tài)轉(zhuǎn)換表狀態(tài)轉(zhuǎn)換表)or its timing diagram （時(shí)序圖）

7、（時(shí)序圖）.5. Determine the logic function of the logic diagram.108-2-1 Analysis of the Sequential Logic Example1w Ex.1 Determine the logic function.01100101)(. 1QKJKJCLKCPCPSynchronous Sequential Logic1. Write down the clock and excitation expressions for each FF.Toggle at the positive edge.nnnQKQJQ1. 2

8、)()(. 2101011010CLKQQQQQCLKQQnnnnnnnT FFJ=K=1118-2-1 Analysis of the Sequential Logic Example14. Assume the present sate, and analyze the next state, and draw its state diagram / state sequence table or its timing diagram.)()(. 2101011010CLKQQQQQCLKQQnnnnnnn128-2-1 1 Analysis of the Sequential Logic

9、 State Sequence Table (狀態(tài)轉(zhuǎn)換表)1001QQ1101QQ0001QQ0101QQ)()(. 2101011010CLKQQQQQCLKQQnnCPQ1Q0000101210311400State Sequence Table138-2-1 Analysis of the Sequential Logic State Diagram (狀態(tài)轉(zhuǎn)換圖)CPQ1Q0000101210311400State Sequence TableState Diagram148-2-1 Analysis of the Sequential Logic Timing Diagram (時(shí)序

10、圖)Timing Diagram158-2-2 A 2-Bit Synchronous Binary CounterA 2-bit synchronous binary counter(2位同步二進(jìn)制位同步二進(jìn)制/4進(jìn)制進(jìn)制 加法計(jì)數(shù)器）加法計(jì)數(shù)器）168-2-3 A 3-Bit Synchronous Binary Counterw Ex.2 Determine the logic function.178-2-3 A 3-Bit Synchronous Binary Counter188-2-3 A 3-Bit Synchronous Binary CounterA 3-bit synch

11、ronous binary counter(3位同步二進(jìn)制位同步二進(jìn)制/8進(jìn)制進(jìn)制 加法計(jì)數(shù)器）加法計(jì)數(shù)器）198-2-4 A 4-Bit Synchronous Decade Counter208-2-4 A 4-Bit Synchronous Decade Counter218-2-4 A 4-Bit Synchronous Decade CounterA 1-bit synchronous decade counter(同步十進(jìn)制加法計(jì)數(shù)器）同步十進(jìn)制加法計(jì)數(shù)器）228-1 Asynchronous Counter Operation (異步計(jì)數(shù)器異步計(jì)數(shù)器)w Asynchronous

12、: refers to events that do not have a fixed time relationship with each other and, generally, do not occur at the same time.w Asynchronous counter: counter in which the FF do not change states at exactly the same time because they do not have a common clock pulse.238-1-1 Analysis of Asynchronous Seq

13、uential Logicw Determine the logic function.Asynchronous Sequential Logic248-1-1 Analysis of Asynchronous Sequential Logic)()()()(exp. 103120100QCPQCPQCPcpCPressionsClock258-1-1 Analysis of Asynchronous Sequential Logic1,11,1)2(32132213100KQQJKJKQJKJnnnQKQJQ1. 2)()()()(. 20321131212013110010QQQQQQQQ

14、QQQQcpQQnnnn268-1-1 Analysis of Asynchronous Sequential Logic30. 3QQC 278-1-1 Analysis of Asynchronous Sequential Logic)()()()(. 20321131212013110010QQQQQQQQQQQQcpQQnnnn30. 3QQC 288-1-1 Analysis of Asynchronous Sequential LogicState Sequence TableState DiagramA asynchronous decade counter(異步十進(jìn)制加法計(jì)數(shù)器

15、）異步十進(jìn)制加法計(jì)數(shù)器）298-1-2 Some Useful Conceptsw Valid states (used states) (有效狀態(tài)) states used by the diagram in normal operation.w Invalid states (unused states)(無效狀態(tài)） states which arent used by the diagram in normal operation.308-1-2 Some Useful ConceptsValid StatesInvalid StatesValid CycleInvalid Cycle3

16、18-1-2 Some Useful Conceptsw Valid Cycle (有效循環(huán)) Cycle that includes the valid states.w Invalid Cycle(無效循環(huán)） Cycle that includes the invalid states.328-1-2 Some Useful Conceptsw Startup automatically (自啟動(dòng)功能) If a logic diagram doesnt have invalid cycle(無效循環(huán)), it can startup automatically. ( (電路進(jìn)入無效狀態(tài)之

17、后電路進(jìn)入無效狀態(tài)之后, ,在在CPCP脈沖作用下脈沖作用下, ,能自動(dòng)返回有能自動(dòng)返回有效循環(huán)效循環(huán), ,稱電路能夠自啟動(dòng)稱電路能夠自啟動(dòng), ,否則為不能自啟動(dòng)）否則為不能自啟動(dòng)）w Self-startup check (自啟動(dòng)檢查) Check if all the invalid states can enter the valid cycle automatically. 33State DiagramStartup automaticallySelf-startup check348-3 Counters 8-3-1 Categories of CountersOthers）(co

18、unter Up/Down ）( counter Down ）( counter Up可逆計(jì)數(shù)器減法計(jì)數(shù)器加法計(jì)數(shù)器The counter can be classified as the following categories:）( counter sSynchronou）( counter usAsynchrono同步計(jì)數(shù)器異步數(shù)器358-3-1 Categories of Counters）( counter Others）( counter Decade）( counter Binary 其他計(jì)數(shù)器十進(jìn)制計(jì)數(shù)器二進(jìn)制計(jì)數(shù)器Modulus-2 counter (2進(jìn)制）進(jìn)制）Modul

19、us-10 counter (10進(jìn)制）進(jìn)制）Modulus-60 counter (60進(jìn)制）進(jìn)制）Modulus-M counter (M進(jìn)制進(jìn)制,任意進(jìn)制）任意進(jìn)制）368-2-5 Synchronous Binary CountersQn+1=TQn+TQnC=Q0Q1Q2Q3Negative edge- triggered 378-2-5 Synchronous Binary Countersf01/2f01/4f01/8f01/16f01/16f0The counter is also called the frequency divider (分頻器分頻器).C=Q0Q1Q2Q3

20、388-2-5 Synchronous Binary Counters -74161 MSI modulus-16 counterCounter, Divider,Modulus-16(16進(jìn)制進(jìn)制)398-2-5 74161 MSI modulus-16 counterParallel data inputs( (并行輸入端）并行輸入端） Data outputs/States Clock PulseActive at the positive edgeENT,ENP: Enable Pins 408-2-5 74161 MSI modulus-16 counter418-2-5 74161

21、 MSI modulus-16 counterPreset input (Load)(預(yù)置端）預(yù)置端）(同步預(yù)置同步預(yù)置)Active-low, synchronously Clear input (清零端）清零端）(異步清零異步清零)Active-low, asynchronously 428-2-5 74161 MSI modulus-16 counterAt the terminal count of 15, RCO=1.Ripple clock output(進(jìn)位脈沖進(jìn)位脈沖)438-2-5 74161 MSI modulus-16 counterState DiagramTiming

22、 Diagram448-2-5 74161/74163 MSI modulus-16 counterCLRLOADENPENTLogic Function Table(功能表）功能表） for 74161/74163458-2-5 74161/74163 MSI modulus-16 counterClear input (清零端）清零端）(異步清零異步清零)Active-low, asynchronously 468-2-5 74161/74163 MSI modulus-16 counterPreset input (Load)(預(yù)置端）預(yù)置端）(同步預(yù)置同步預(yù)置)Active-low,

23、synchronously 478-2-5 74161/74163 MSI modulus-16 counterOnly when both of EP and ET are active, is the counter enabled (in counter operation).The outputs plus one at the positive-edge of CP 488-2-5 74161/74163 MSI modulus-16 counterOnly when both of EP and ET are active, is the counter enabled (in c

24、ounter operation).498-2-5 74160 MSI modulus-10 counter74160 synchronous BCD decade counter (CTR DIV 10 modulus-10, 10 states)508-2-5 74160 MSI modulus-10 counterClear asynchronously 異步清零異步清零The clear input is active-LOW.518-2-5 74160 MSI modulus-10 counterA timing diagram showing the counter being p

25、reset to count 7 (0111).Preset synchronously 同步預(yù)置同步預(yù)置When the preset input is nonactive, the parallel inputs have no use.The outputs are preset to the corresponding data input only at the active edge of CP.528-2-5 74160 MSI modulus-10 counterWhen the terminal count is 9 (TC=9), RCO=1538-2-5 74160 MS

26、I modulus-10 counterIf any of ENP and ENT is nonactive (LOW), the outputs are disabled, remain in present states548-3 Up/Down Synchronous Counters(可逆可逆/加減計(jì)數(shù)器加減計(jì)數(shù)器)w By the control of the up/down input, the counter, on one hand, can increase one by one; on the other hand, can also decrease one by one

27、.w This kind of counter is called up/down (加減加減) one, bidirectional （可逆）（可逆）counter, also.558-3 Up/Down Synchronous CountersA basic 3-bit up/down synchronous counter568-3 Up/Down Synchronous CountersUp/down sequence for a 3-bit binary counterState Sequence Table for a 3-bit binary counter578-3 Up/Do

28、wn Synchronous CountersState DiagramUp sequenceDown sequence588-3 Up/Down Synchronous Countersw Logic function table for MSI 74191- a synchronous modulus-16 up/down counterPreset Asynchronously 異步預(yù)置異步預(yù)置LOADCTEN598-3 Up/Down Synchronous Countersw Logic symbol for MSI 74190- a synchronous modulus-10 u

29、p/down counter608-3 Up/Down Synchronous CountersTiming Example For a 74190Preset Asynchronously 異步預(yù)置異步預(yù)置618-4 Design of Sequential Logics(時(shí)序電路設(shè)計(jì))Sequential logic designSSI Sequential logic design(小規(guī)模小規(guī)模)- Design sequential logic using flip-flops 用觸發(fā)器設(shè)計(jì)時(shí)序電路用觸發(fā)器設(shè)計(jì)時(shí)序電路MSI Sequential logic design(中規(guī)模中規(guī)模

30、)- Design modulus-M counter using MSI modulus-N counter用用N進(jìn)制中規(guī)模集成計(jì)數(shù)器設(shè)計(jì)任意進(jìn)制中規(guī)模集成計(jì)數(shù)器設(shè)計(jì)任意M進(jìn)制計(jì)進(jìn)制計(jì)數(shù)器數(shù)器628-4-1 SSI Sequential logic design- Sequential Logics Design using FFProcedure:w Step 1: Convert the given problem to a logic problem. Assume the input, output and state variables.w Step 2: Get its stat

31、e diagram.w Step 3: Get its state sequence table.w Step 4: According to the number of the states, draw a corresponding number-variable K-map. 638-4-1 Sequential Logics Design using FFw Step 5: Get the state expressions using K-map.w Step 6: Choose the needed flip-flop. w Step 7: Get the excitation e

32、xpressions according to the state expressions and logic expression for the corresponding flip-flop.w Step 8: Sketch the logic diagram.648-4-1 Sequential Logics Design using FFExample 1Ex.1: Design a modulus-13 counter with cascaded output.Step 1: Assume the input, output and state variables. Output:

33、 CState variables: S0,S1S12State diagram.658-4-1 Sequential Logics Design using FFExample 113 states: 4 flip-fops (13 =24)Step 2: State sequence table.668-4-1 Sequential Logics Design using FFExample 1w Step 3: next-state K-map.Present state:0000Next state: 0001 Output: 0Dont care conditions678-4-1

34、Sequential Logics Design using FFExample 1w Step 4: Get k-map for each state. (Optional)688-4-1 Sequential Logics Design using FFExample 1Step 5: Get the state expressions.698-4-1 Sequential Logics Design using FFExample 1Step 5: Get the output expression.C=Q3Q2Step 6: Choose the flip-flop: J-K flip

35、-flop.708-4-1 Sequential Logics Design using FFExample 1Step 7: Get the excitation expression.nnnQKQJQ113323210QQQQQQQn718-4-1 Sequential Logics Design using FFExample 1Step 8: Draw the logic diagram.C=Q3Q2728-4-1 Sequential Logics Design using FFExample 1w Step 9: Self-startup check (自啟動(dòng)檢查自啟動(dòng)檢查)It

36、can startup automatically.13323210QQ QQ Q Q Qn738-4-1 Sequential Logics Design using FFExample 2Ex. 2: Design a logic diagram that can check the series data. When there are three or more than three HIGH inputs in series, the output is 1; otherwise , the output is 0. 設(shè)計(jì)一個(gè)串行數(shù)據(jù)檢測器。當(dāng)連續(xù)輸入設(shè)計(jì)一個(gè)串行數(shù)據(jù)檢測器。當(dāng)連續(xù)輸

37、入3個(gè)或個(gè)或3個(gè)以上個(gè)以上1的時(shí)候，輸出為的時(shí)候，輸出為1；否則為；否則為0。 748-4-1 Sequential Logics Design using FFExample 2w Step 1: Analyze the problem, assume the input/output variables, and get its state diagram/state sequence table.Assume:X: the input variable;Y: the output variable;States: S0 the input is 0; S1 there is only o

38、ne HIGH input. S2 there is two HIGH inputs in series. S3 there is three or more than three HIGH inputs in series.758-4-1 Sequential Logics Design using FFExample 2w Step 2: State sequence tableEquivalent States(等價(jià)狀態(tài)等價(jià)狀態(tài))The input768-4-1 Sequential Logics Design using FFExample 2Step 3: K-map0001103

39、states: 2 flip-fops (3 N, more than one MSI device is needed.1088-4-3 Sequential Logics Design using MSI Counterw1. MNSkip N-M statesTwo methods:(1) Implement it using the CLEAR (RESET) input (generally the CLEAR input is asynchronous). (利用清零端，反饋歸零法)(2) Implement it using the PRESET input. (Some of

40、the PRESET input are asynchronous, and others are synchronous) (利用預(yù)置端，置數(shù)法)1098-4-3 Sequential Logics Design using MSI CounterMomentary/Astable state (瞬態(tài)), not included in the valid cycle.異步清零，瞬態(tài)不包括在有效循環(huán)中異步清零，瞬態(tài)不包括在有效循環(huán)中Preset the states at any state可在任意狀態(tài)下進(jìn)行預(yù)置可在任意狀態(tài)下進(jìn)行預(yù)置同步預(yù)置沒有瞬態(tài)，異頻預(yù)置有瞬態(tài)。同步預(yù)置沒有瞬態(tài)，異頻預(yù)

41、置有瞬態(tài)。1108-4-3 Sequential Logics Design using MSI CounterOnly when both of EP and ET are active, is the counter enabled (in counter operation).w Ex. 1 Implement a modulus-6 counter using 74160.w Logic Function Table for 74160Clear inputActive-low, asynchronously(異步清零) Preset input (Load)Active-low, synchronously(同步預(yù)置) 1118-4-3 Sequential Logics Design using MSI Coun