微機接口實驗報告

1、 . . . 微機接口實驗報告院系：計算機科學(xué)與技術(shù)完成時間：2012-6-1實驗一 IO地址譯碼器編程一、 實驗題目使用一片74LS00(4 X二輸入與非門),一片74LS30(八輸入與非門)和一片74LS138(3-8譯碼器)設(shè)計一個固定地址譯碼器.1)使用10位地址線(A0 A9)2)譯碼器對以下8個地址段產(chǎn)生CS信號:280H287H,288H28FH,290H297H,298H29FH 2A0H2A7H,2A8H2AFH,2B0H2B7H, 2B8H2BFH3)控制信號AEN, IOR, IOW(三個信號均為低電平有效)參與譯碼, 可實現(xiàn)對指定單元的讀寫.二、實驗要求1)所有地址段的

2、CS信號,都要經(jīng)過仿真驗證.2)驗證控制信號AEN, IOR, IOW的作用.三、實驗分析1、IO地址譯碼地址譯碼是指通過CPU發(fā)出的地址碼來識別和確認與之交換信息的端口。譯碼電路的具體功能是，將CPU發(fā)出的地址碼經(jīng)過譯碼產(chǎn)生選擇I/O接口的片選信號。只有當I/O端口所在的I/O接口與譯碼電路相連接的片選信號有效時，該接口電路上的I/O端口才能被CPU訪問，從而實現(xiàn)CPU和I/O設(shè)備之間的信息交換。PC機I/O端口地址譯碼器的設(shè)計遵循以下兩個設(shè)計原則：第一，正確識別I/O端口操作周期。由于PC機中I/O端口操作和DMA操作使用一樣的地址線、數(shù)據(jù)線和讀/寫控制信號。區(qū)別這兩種操作的信號是AEN。

3、在DMA操作周期時，AEN有效，為高電平；而在I/O端口操作時，AEN無效，為低電平。第二，減少譯碼電路器件的延時。在系統(tǒng)中，或者信號的有效僅比端口地址有效落后半個時鐘周期。如果譯碼電路過長將導(dǎo)致輸出無效信號等等后果，這種情況下可采用的方法是減少譯碼電路門級數(shù)或者高速門電路。固定式端口地址譯碼器可以采用集成譯碼器輔以門電路譯碼來獲得多個端口地址。最常用的3-8譯碼器74LS138，它有A，B，C共三個輸入端和共8個輸出端，其輸出端為低電平有效。3-8譯碼器的芯片引腳圖和真值表如圖1和表1.圖1中A，B和C為輸入端，和、為控制端，其他的Y為輸出端。真值表中，三個輸入端共有8種組合，每一種情況對應(yīng)

4、于一個輸出端為低電平，此外，還有三個控制端，只有G1為高電平，另兩個控制信號為低電平時有效。圖 1 3-8譯碼器CBA輸出1 0 01 0 01 0 01 0 01 0 01 0 01 0 01 0 00 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1僅為0僅為0僅為0僅為0僅為0僅為0僅為0僅為0其他狀態(tài)XXX全檢出1表 1 3-8譯碼器真值表2、固定地址譯碼器由74LS00和74LS30、74LS138組成的固定地址譯碼器的電路如圖2所示。輸出信號cs(0 to 7)由輸入端信號A3-A5和控制信號控制，其他的4個輸入信號A6-A9全為低時整個電路有效。當AE

5、N為低時，整個電路可以進行片選，對應(yīng)的輸入信號（A3-5）與輸出信號為0，1，1，1，1，1，1,1。讀信號為上升脈沖時有效，可進行譯碼。當AEN為高時，整個電路不可以進行譯碼，輸出信號均為111111111。圖 2固定地址譯碼器由上述邏輯電路，可以推導(dǎo)出以下邏輯表達式：=即=+·。因此，只有當片選信號AEN為低時可以進行譯碼。四、實驗步驟與截圖1、ISE新建工程（1）啟動ISE13.1軟件；（2）新建工程，路徑為file->new project，在彈出的窗口中輸入要新建工程的名字和地址，各個參數(shù)設(shè)置如下：family（Automotive Spartan3）device（X

6、A3S200）package（PQG208）speed（-4Q）Synthesis Tool（XST）Simulator（Isim）在Preferred Language中選擇VHDL一欄，點擊next可以查看工程信息，建立完畢；（3）給工程添加新的文件。右鍵單擊工程，然后添加需要添加的文件，這里應(yīng)該只需添加基本的文件和測試文件即可，或者先建立文件，再將代碼修改在基本文件中即可；（4）在Synthesize中選擇check進行編譯，出現(xiàn)綠色對勾即可；（5）添加測試文件。路徑為project->new source，選擇VHDL Test文件，然后編寫測試文件；（6）雙擊process窗口

7、的Simulator Behavior可以查看仿真圖形。2、實驗截圖。實驗代碼截圖：實驗測試文件截圖：實驗結(jié)果仿真截圖：五、實驗源代碼程序源代碼：- Company: - Engineer: - - Create Date: 13:21:58 04/17/2012- Design Name: - Module Name: ad - ad_Behavioral - Project Name: - Target Devices: - Tool versions: - Description: - Dependencies: - Revision: - Revision 0.01 - File Cr

8、eated- Additional Comments: -library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity ad is Port ( addr :

9、 in STD_LOGIC_VECTOR (3 to 9); aen, iow, ior : in STD_LOGIC; cs : out STD_LOGIC_VECTOR (7 downto 0);end ad;architecture ad_Behavioral of ad issignal en: std_logic;signal out_temp: std_logic_vector (7 downto 0);begin out_temp(7 downto 0) <="11111110" when addr (3 to 5) = "000"

10、else"11111101" when addr (3 to 5) = "100" else"11111011" when addr (3 to 5) = "010" else"11110111" when addr (3 to 5) = "110" else"11101111" when addr (3 to 5) = "001" else "11011111" when addr (3 to 5) = "

11、;101" else"10111111" when addr (3 to 5) = "011" else"01111111" when addr (3 to 5) = "111" ;process (addr, aen, iow,ior)begin en <= not (not addr(6) and addr(7) and (not addr(8) and addr(9) and (not aen) and (not (iow and ior);for i in 7 downto 0 loopcs

12、(i) <= out_temp(i) or en;end loop;end process;end architecture ad_Behavioral;測試文件源代碼:- Company: - Engineer:- Create Date: 19:15:02 05/29/2012- Design Name: - Module Name: D:/vhdl/abc/test.vhd- Project Name: abc- Target Device: - Tool versions: - Description: - - VHDL Test Bench Created by ISE for

13、 module: ad- - Dependencies:- - Revision:- Revision 0.01 - File Created- Additional Comments:- Notes: - This testbench has been automatically generated using types std_logic and- std_logic_vector for the ports of the unit under test. Xilinx recommends- that these types always be used for the top-lev

14、el I/O of a design in order- to guarantee that the testbench will bind correctly to the post-implementation - simulation model.-LIBRARY ieee;USE ieee.std_logic_1164.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-USE ieee.numeric_std.AL

15、L;ENTITY test ISEND test;ARCHITECTURE behavior OF test IS - Component Declaration for the Unit Under Test (UUT) COMPONENT ad PORT( addr : IN std_logic_vector(3 to 9); aen : IN std_logic; iow : IN std_logic; ior : IN std_logic; cs : OUT std_logic_vector(7 downto 0) ); END COMPONENT; -Inputs signal ad

16、dr : std_logic_vector(3 to 9) := (others => '0'); signal aen : std_logic := '0' signal iow : std_logic := '0' signal ior : std_logic := '0' -Outputs signal cs : std_logic_vector(7 downto 0); - No clocks detected in port list. Replace <clock> below with - appr

17、opriate port name BEGIN- Instantiate the Unit Under Test (UUT) uut: ad PORT MAP ( addr => addr, aen => aen, iow => iow, ior => ior, cs => cs ); - Clock process definitions - Stimulus process stim_proc: process begin - hold reset state for 100 ns. - insert stimulus here aen <='1

18、'iow <='1'addr (3 to 9) <= "0000101" ior<='0' wait for 1 ns; ior<='1'wait for 9 ns;addr (3 to 9) <= "1000101" ior<='0' wait for 1 ns; ior<='1'wait for 9 ns;addr (3 to 9) <= "0100101" ior<='0'

19、 wait for 1 ns; ior<='1'wait for 9 ns;addr (3 to 9) <= "1100101" ior<='0' wait for 1 ns; ior<='1'wait for 9 ns;addr (3 to 9) <= "0010101" ior<='0' wait for 1 ns; ior<='1'wait for 9 ns;addr (3 to 9) <= "1010101&q

20、uot; ior<='0' wait for 1 ns; ior<='1'wait for 9 ns;addr (3 to 9) <= "0110101" ior<='0' wait for 1 ns; ior<='1'wait for 9 ns;addr (3 to 9) <= "1110101" ior<='0' wait for 1 ns; ior<='1'wait for 9 ns;addr (3 to

21、9) <= "0000101" ior<='0' wait for 1 ns; ior<='1'wait for 9 ns; wait; end process;END;實驗二 簡易中斷優(yōu)先權(quán)分析器編程一、 實驗容與要求用VHDL語言設(shè)計一個簡易中斷優(yōu)先權(quán)分析器。1) 參考教材8259A優(yōu)先權(quán)分析器邏輯框圖.2) 不考慮IMR屏蔽功能, 8路中斷直接進入優(yōu)先權(quán)分析器.3) ISR的容以3位二進制編碼,從外部輸入比較器4) 不考慮多重中斷. 既假定每次只有一個中斷發(fā)生.要求仿真驗證優(yōu)先權(quán)分析器的實際效果。二、實驗分析1、中斷C

22、PU在正常運行程序時，由于部/外部事件或程序本身的原因等中斷正在運行的程序，轉(zhuǎn)到為中斷事件服務(wù)的程序中去執(zhí)行，而在服務(wù)完畢后再返回執(zhí)行源程序，這一過程稱為中斷?，F(xiàn)代微機的中斷有外部硬件中斷、非屏蔽中斷、軟件中斷和部中斷與異常四種類型。系統(tǒng)對于中斷按其優(yōu)先級的高低依次提供服務(wù)。每個中斷和異常都指定了一個類型號代表不同的優(yōu)先級，類型0代表最高優(yōu)先級的中斷，類型255代表最低優(yōu)先級的中斷。優(yōu)先級的重要性在于，如果已經(jīng)啟動了某些優(yōu)先級的中斷服務(wù)程序，那么只要更高優(yōu)先級的中斷請求才允許打斷該服務(wù)程序的運行。低優(yōu)先級的中斷請求將等待，直到當前中斷服務(wù)程序結(jié)束。出于這個原因，用戶通常將不能經(jīng)常被打斷的任務(wù)指

23、定較高優(yōu)先級，而可以被打斷的則指定較低優(yōu)先級。IMR是中斷屏蔽寄存器，它對中斷請求IR起屏蔽作用，這里忽略它的影響。ISR是中斷服務(wù)寄存器，在中斷響應(yīng)之后，第一個獲準中斷請求的中斷級在相應(yīng)的ISR中置1。ISR用來存放正在被服務(wù)的中斷，包括尚未服務(wù)完而被優(yōu)先級更高的中斷打斷的中斷。2、中斷優(yōu)先權(quán)分析器8路中斷直接進入優(yōu)先權(quán)分析器，設(shè)定ISR值，如果進入優(yōu)先權(quán)分析器的中斷級別比ISR高，則將結(jié)果INT置為1，否則將INT置為0。例如，8路中斷為0001100，ISR設(shè)置為011，顯然不能發(fā)生中斷響應(yīng)，即INT的值為0；如果8路中斷為00000010，那么優(yōu)先級比ISR高，就會發(fā)生中斷響應(yīng)，同等優(yōu)

24、先級不能發(fā)生中斷響應(yīng)。三、實驗截圖四、實驗代碼1主程序源代碼- Company: - Engineer: - - Create Date: 20:37:30 05/22/2012 - Design Name: - Module Name: MY8259A - Behavioral - Project Name: - Target Devices: - Tool versions: - Description: - Dependencies: - Revision: - Revision 0.01 - File Created- Additional Comments: -library IEE

25、E;use IEEE.STD_LOGIC_1164.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponent

26、s.all;entity MY8259A is Port ( IR0 : in STD_LOGIC; IR1 : in STD_LOGIC; IR2 : in STD_LOGIC; IR3 : in STD_LOGIC; IR4 : in STD_LOGIC; IR5 : in STD_LOGIC; IR6 : in STD_LOGIC; IR7 : in STD_LOGIC; ISR : in STD_LOGIC_VECTOR (2 downto 0); INT : out STD_LOGIC);end MY8259A;architecture Behavioral of MY8259A i

27、sSIGNAL BIG, MORE1 :STD_LOGIC;begin PROCESS(IR0,IR1,IR2,IR3,IR4,IR5,IR6,IR7) VARIABLE A :STD_LOGIC_VECTOR (2 downto 0); BEGIN IF (IR0 = '1') then A := "000" ; MORE1 <= '1' ELSIF (IR1 = '1') then A := "001" ; MORE1 <= '1' ELSIF (IR2 = '1&#

28、39;) then A := "010" ; MORE1 <= '1' ELSIF (IR3 = '1') then A := "011" ; MORE1 <= '1' ELSIF (IR4 = '1') then A := "100" ; MORE1 <= '1' ELSIF (IR5 = '1') then A := "101" ; MORE1 <= '1' ELSIF (IR

29、6 = '1') then A := "110" ; MORE1 <= '1' ELSIF (IR7 = '1') then A := "111" ; MORE1 <= '1' ELSE A := "111" MORE1 <= '0' END IF; IF(A < ISR) then BIG <= '1' ELSEBIG <= '0'END IF; end PROCESS;INT <

30、= BIG AND MORE1;end Behavioral;2、Test代碼- Company: - Engineer:- Create Date: 21:24:55 05/22/2012- Design Name: - Module Name: E:/PROJ2/test.vhd- Project Name: PROJ2- Target Device: - Tool versions: - Description: - - VHDL Test Bench Created by ISE for module: MY8259A- - Dependencies:- - Revision:- Re

31、vision 0.01 - File Created- Additional Comments:- Notes: - This testbench has been automatically generated using types std_logic and- std_logic_vector for the ports of the unit under test. Xilinx recommends- that these types always be used for the top-level I/O of a design in order- to guarantee tha

32、t the testbench will bind correctly to the post-implementation - simulation model.-LIBRARY ieee;USE ieee.std_logic_1164.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signed or Unsigned values-USE ieee.numeric_std.ALL;ENTITY test ISEND test;ARCHITECTURE behavio

33、r OF test IS - Component Declaration for the Unit Under Test (UUT) COMPONENT MY8259A PORT( IR0 : IN std_logic; IR1 : IN std_logic; IR2 : IN std_logic; IR3 : IN std_logic; IR4 : IN std_logic; IR5 : IN std_logic; IR6 : IN std_logic; IR7 : IN std_logic; ISR : IN std_logic_vector(2 downto 0); INT : OUT

34、std_logic ); END COMPONENT; -Inputs signal IR0 : std_logic := '0' signal IR1 : std_logic := '0' signal IR2 : std_logic := '0' signal IR3 : std_logic := '0' signal IR4 : std_logic := '0' signal IR5 : std_logic := '0' signal IR6 : std_logic := '0'

35、; signal IR7 : std_logic := '0' signal ISR : std_logic_vector(2 downto 0) := (others => '0'); -Outputs signal INT : std_logic; - No clocks detected in port list. Replace <clock> below with - appropriate port name BEGIN- Instantiate the Unit Under Test (UUT) uut: MY8259A PORT MAP ( IR0 => IR0, IR1 => IR1, IR2 => IR2, IR3 => IR3, IR4 => IR4, IR5 => IR5, IR6 => IR6, IR7 => IR7, ISR => ISR, INT => INT ); - Stimulus process stim_proc: process begin - hold reset state f