鍵盤(pán)掃描輸入實(shí)驗(yàn)

1、4.1.1 實(shí)驗(yàn)?zāi)康?1.學(xué)習(xí)復(fù)雜數(shù)字系統(tǒng)的設(shè)計(jì)方法； 2.掌握矩陣式鍵盤(pán)輸入列陣的設(shè)計(jì)方法。4.1.2 實(shí)驗(yàn)設(shè)備 PC微機(jī)一臺(tái)，TD-EDA試驗(yàn)箱一臺(tái)，SOPC開(kāi)發(fā)板一塊。4.103 實(shí)驗(yàn)內(nèi)容在電子，控制，信息處理等各種系統(tǒng)中，操作人員經(jīng)常需要想系統(tǒng)輸入數(shù)據(jù)和命令，以實(shí)現(xiàn)人機(jī)通信。實(shí)現(xiàn)人機(jī)通信最常用的輸入設(shè)備是鍵盤(pán)。在EDA技術(shù)的綜合應(yīng)用設(shè)計(jì)中，常用的鍵盤(pán)輸入電路獨(dú)立式鍵盤(pán)輸入電路、矩陣式鍵盤(pán)輸入電路和“虛擬式”鍵盤(pán)輸入電路。所謂矩陣是鍵盤(pán)輸入電路，就是將水平鍵盤(pán)掃描線(xiàn)和垂直輸入譯碼線(xiàn)信號(hào)的不同組合編碼轉(zhuǎn)換成一個(gè)特定的輸入信號(hào)值或輸入信號(hào)編碼，利用這種行列矩陣結(jié)構(gòu)的鍵盤(pán)，只需N個(gè)行線(xiàn)和M個(gè)列

2、線(xiàn)即可組成NXM按鍵，矩陣式鍵盤(pán)輸入電路的優(yōu)點(diǎn)是需要鍵數(shù)太多時(shí)，可以節(jié)省I/O口線(xiàn)；缺點(diǎn)是編程相對(duì)困難。本實(shí)驗(yàn)使用TD-EDA實(shí)驗(yàn)系統(tǒng)的鍵盤(pán)單元設(shè)計(jì)一個(gè)4x4的矩陣鍵盤(pán)的掃描譯碼電路。此設(shè)計(jì)包括鍵盤(pán)掃描模塊和掃描碼鎖存模塊，原理如圖4-1-1。每按下鍵盤(pán)列陣的一個(gè)按鍵立即在七段數(shù)碼管上顯示相應(yīng)的數(shù)據(jù)。4.1.1 實(shí)驗(yàn)步驟 1. 運(yùn)行Quartus II 軟件，分別建立新工程，選擇File->New菜單，創(chuàng)建VHDL描述語(yǔ)言設(shè)計(jì)文件，分別編寫(xiě)、REG.VHD. 2.掃描碼鎖存模塊REG的VHDL源程序如下；-輸入鎖存器VHDL源程序:REGVHDL LIBRARY IEEE;USB IEE

3、E.STD-LOGIC-1164.ALL; ENTITY REG ISPORT ( RCLK : IN STD-LOGIC; -掃描時(shí)鐘YXD : IN STD-LOGIC-VECTOR(3 DOWNTO 0); -Y 列消抖輸入 DATA : IN STD-LOGIC-VECTOR(7 DOWNTO 0); -輸入數(shù)據(jù) LED : OUT STD-LOGIC-VECTOR(7 DOWNTO 0); -鎖存數(shù)據(jù)輸出END ENTITY REG;ARCHITECTURE BEHV OF REG IS SIGNAL RST : STD-LOGIC; -鎖存器復(fù)位清零 SIGNAL OLDDATA

4、:STD-LOGIC-VECTOR(7 DOWNTO 0); -鎖存器舊數(shù)據(jù) SIGNAL NEWDATA :STD-LOGIC-VECTOR(7 DOWNTO 0); -鎖存器新數(shù)據(jù) BEGIN PROCESS(RCLK) BEGIN IF RCLKEVENT AND RCLK=1THEN RST<=YXD(3)AND YXD(2)AND YXD(1)AND YXD(0); -判斷是否有按鍵 END IF; END PROCESS; PROCESS(RST) IS BEGIN IF(RST=1)THEN -RST=1沒(méi)有按鍵按下 NEWDATA<=OLDDATA; ELSE OL

5、DDATA<=DATA; -RST=0有按鍵按下打入新?lián)?END IF; LED<=NEWDATA; END PORCESS; END ARCHIECTUBE BEHV;3. 鍵盤(pán)掃描模塊JPSCAN的VHDL源程序如下； -鍵盤(pán)掃描電路的VHDL源程序；LIBRARY IEEE;USB IEEE-STD-LOGIC-1164-ALL;USB IEEE-STD-LOGIC-ARITH-ALL;USB IEEE-STD-LOGIC-UNSIGNED-ALL;ENTITY JPSCAN ISPORT(SCLK : IN STD-LOGIC -系統(tǒng)時(shí)鐘：1KHZ YLINE : IN S

6、TD-LOGIC-VECTOR(4 DOWN 1); -Y列按鍵輸入 RCLK : OUT STD-LOGIC; -X行鍵盤(pán)掃描時(shí)鐘 YXD : OUT STD-LOGIC-VECTOR(3 DOWN 0); -Y列消抖輸出 DATA : OUT STD-LOGIC-VECTOR(7 DOWN 0); -數(shù)字輸出 XROW : OUT STD-LOGIC-VECTOR(4 DOWN 1); -X行鍵盤(pán)掃描END ENTITY JPSCAN;ARCHITECTURE BEHV OF JPSCAN IS COMPONENT JPXD IS -控制電路工作時(shí)鐘：512Hz SIGNAL KEY-SC

7、AN:STD-LOGIC-VECTOR(1 DOWNTO 0); -鍵盤(pán)掃描時(shí)鐘信號(hào) -“00-01-10-11” SIGNAL CLK-JPXD : STD-LOGIC; -去抖電路工作時(shí)鐘 SIGNAL Y-XD : STD-LOGIC-VECTOR(3 DOWNTO 0); -鍵盤(pán)列輸入去抖后的寄存器 SIGNAL X-SCAN : STD-LOGIC-VECTOR(3 DOWNTO 0) -鍵盤(pán)行掃描輸出寄存器 -1110-1101-1011-0111 SIGNAL VALUE : STD-LOGIC-VECTOR(7 DOWNTO 0); -按鍵譯碼數(shù)值寄存器 BEGIN DATA&

8、lt;=VALUE; COUNTER:BLOCK IS -信息掃描發(fā)生器 SIGNAL Q :STD-LOGIC-VECTOR(6 DOWNTO 0); -計(jì)數(shù)器實(shí)現(xiàn)分頻 BEGIN PROCESS(SCLK)IS BEGIN IF SCLKEVENT AND SCLK=THEN Q<=Q+1; END IF; CLK<=Q(0);-控制電路工作時(shí)鐘：512Hz，系統(tǒng)時(shí)鐘的二分頻 CLK-JPXD<=Q(2); -去抖時(shí)鐘信號(hào)，大約128Hz KEY-SCAN<=Q(6 DOWNTO 5); -產(chǎn)生鍵盤(pán)掃描信號(hào)00-01-10-11，大約16Hz END PROCESS

9、; X-SCAN<=”1110”WHEN KEY-SCAN=”00”ELSE”1101”WHEN KEY-SCAN=”01”ELSE”1011”WHEN KEY-SCAN=”10”ELSE”0111”WHEN KEY-SCAN=”11”ELSE“1111” XROW(4 DOWNTO 1)<=X-SCAN(3 DOWNTO 0); -X行掃描 END BLOCK COUNTER; JPXDMK:BLOCK IS -鍵盤(pán)去抖模塊 BEGIN U1：JPXD PORT MAP(D-IN=>YLINE(1),D-OUT=>Y-XD(0),CLK=>CLK-JPXD);U

10、2：JPXD PORT MAP(D-IN=>YLINE(2),D-OUT=>Y-XD(1),CLK=>CLK-JPXD);U3：JPXD PORT MAP(D-IN=>YLINE(3),D-OUT=>Y-XD(2),CLK=>CLK-JPXD);U4：JPXD PORT MAP(D-IN=>YLINE(4),D-OUT=>Y-XD(3),CLK=>CLK-JPXD); YXD(3 DOWNTO 0)<=Y-XD(3 DOWNTO 0); RCLK<=CLK; -鍵盤(pán)掃描時(shí)鐘等于控制電路工作時(shí)鐘：512Hz END BLOCK J

11、PXDMK; KEY-DECODER : BLOCK IS -鍵盤(pán)譯碼模塊 SIGNAL Z:STD-LOGIC-VECTOR(5 DOWNTO 0); BEGIN PORCESS(CLK) BEGIN Z<=KEY-SCAN&Y-XD; IF CLKEVENT AND CLK=1THEN CASE Z IS WHEN”001110”=>VALUE<=”00111111”; -0 WHEN”011110”=>VALUE<=”00000110”; -1 WHEN”101110”=>VALUE<=”01011011”; -2 WHEN”111110

12、”=>VALUE<=”01001111”; -3 WHEN”001101”=>VALUE<=”01100110”; -4 WHEN”011101”=>VALUE<=”01101101”; -5 WHEN”101101”=>VALUE<=”01111101”; -6 WHEN”111101”=>VALUE<=”00000111”; -7 WHEN”001001”=>VALUE<=”01111111”; -8 WHEN”011011”=>VALUE<=”01101111”; -9 WHEN”101011”=>

13、VALUE<=”01110111”; -A WHEN”111011”=>VALUE<=”01111100”; -B WHEN”000111”=>VALUE<=”00111001”; -C WHEN”010111”=>VALUE<=”01011110”; -D WHEN”100111”=>VALUE<=”01111001”; -E WHEN”110111”=>VALUE<=”01110001”; -F WHEN OTHERS => VALUS<=”00000000”; -OTHER END CASE; END IF;

14、END PROCESS; END BLOCK KEY-DECODER;END ARCHITECTURE BEHV;4. 上述程序中鍵盤(pán)消抖模塊JPXD的VHDL源程序如下： -鍵盤(pán)輸入消抖電路的VHDL源程序。JPXD,VHDLIBRARY IEEE; USB IEEESTD-LOGIC-1164ALL; ENTITY JPXD IS PORT(D-IN : IN STD-LOGIC; CLK :IN STD-LOGIC; D-OUT:OUT STD-LOGIC); END ENTITY JPXD;ARCHITECTURE BEHV OF JPXD ISCOMPONENT DCFQ IS PO

15、RT(CLK: IN STD-LOGIC; -時(shí)鐘信號(hào) CLRN: IN STD-LOGIC: -清零信號(hào) PRN: IN STD-LOGIC; -預(yù)置信號(hào) D: IN STD-LOGIC; Q: OUT STD-LOGIC);END COMPONENT DCFQ; SIGNAL VCC,INV-D:STD-LOGIC; SIGNAL Q0,Q1：STD-LOGIC; SIGNAL D1,D0：STD-LOGIC; BEGIN VCC<=1; INV-D<=NOT D-IN;UMN1:DCFQ PORT MAP(CLK=>CLK,CLRN=>INV-DVCRN=>

16、VCC,D=>VCC,Q=>Q0);UMN2:DCFQ PORT MAP(CLK=>CLK,CLRN=>Q0，PRN=>VCC,D=>VCC,Q=>Q1); PROCESS(CLK) BEGIN IF CLKEVENT AND CLK=THEN D0<=NOT Q1; D1<=D0; END IF;END PROCESS; D-OUT<=NOT(D1 AND NOT D0);END ARCHITECTURE BEHV;5. 編譯源文件，編譯無(wú)誤后分別對(duì)上述VHDL文件進(jìn)行仿真，驗(yàn)證其邏輯功能正確后，選擇File->Create/Update ->Create Symbol File for Current File菜單，分別生成符號(hào)文件.BSF。6. 建立新工程，工程名稱(chēng)及頂層文件名稱(chēng)為JIAPAN，選擇File->New菜單，創(chuàng)建圖形設(shè)計(jì)文件。如圖4-1-1所示，完成鍵盤(pán)掃描輸入電路的設(shè)計(jì)。將創(chuàng)建的圖形設(shè)計(jì)文件保留存為作為整個(gè)設(shè)計(jì)的頂層文件。7. 選擇Tools->Compiler Tool菜單，編譯文件。8. 選擇Assignments->Assignment Editor菜