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1、1 .Generic decoder. library ieee; use ieee.std_logic_l 164.all; entity s isgeneric( n:integer :=8); port(sel:in integer range 0 to n-1; ena:in std_logic;x:out std_logic_vector(n-1 downto 0); end s;architecture s of s is beginprocess(ena,sel)variable t2:std_logic_vector(x*high downto 0); begint2:=(ot

2、hers=>'r ); if(ena=T) then t2(sel):='0 ; end if; x<=t2; end process; end s;2. Generic parity detecto 匸 library ieee;use ieee.std_logic_l 164.all; entity s isgeneric( n:integer :=8);port(input:in std_logic_vector(n downto 0); output:out std_logic);end s; architecture s of s is begin pro

3、cess(input) variable t:std_logic; begint=0 ；for i in input'range loopt:=t xor input(i); end loop; output<=t; end process;end s;3. Generic parity generator library ieee;use ieee.std_logic_l 164.all; entity s isgeneric( n:integer :=8);port(input:in std_logic_vector(n-1 downto 0); output:out std

4、_logic_vector(n downto 0); end s; architecture s of s isbegin process (input)variable t:std_logic;variable tl :std_logic_vector(output'high downto 0) begin t:=O;for i in input'range loop t:=t xor input(i); tl:=t&input; end loop; output<=tl; end process; end s ;4 .Simple multiplexer. l

5、ibrary ieee;use ieee.std_logic_l 164.all; entity s isport(a,b,c,d:in std_logic; s:in std_logic_vector( 1 downto 0); y:out std_logic);end s; architecture s of s is beginwith s select y<=a when "00", bwhen n01n, c when "10 ，” d when others;end s;5. 帶 q 和 qbar 的 DFF. library ieee;use

6、ieee.std_logic_l 164.all; entity s isport(d,clk:in std_logic; q: buffer std_logic; qbar:out std_logic);end s ; architecture s of s iS begin process(clk)beginif(clk'event and elk-F) then q<=d；end if; end process;qbar<=not q;end s;6. Tri-state buffer. library ieee;use ieee.std_logic_l 164.al

7、l; entity s isport(input:IN std_logic_vector(7 downto 0); ena:IN std_logic;output:out std_logic_vector(7 downto 0); end s;architecture s of s is beginoutput<=input when(ena='O') else” zzzzzzzz； ” end s;7. Adder.std_logic_vector(8 downto 0): signal t:tt;begin tK9 & a;t2<=*0' &am

8、p; b;t3<='0' & conv_signed(a,8);t4<='0' & conv_signed(b,8); cin0<="ll" when cin-1' else "00" cinl<="ll" when cin-1* else "00" s 1 <=t l+t2+cin0(0);s2<=tl-t2-cin0(l); s3<=t3+t4+cin 1 (0); s4<=t3-t4-cinl(l); t(

9、0)<=conv_std_logic_vector(s 1,9);t(l)<=conv_std_logic_vector(s2,9);t(2)<=conv_std_logic_vector(s3,9); t(3)<=conv_std_logic_vector(s4,9);library ieee;use ieee.std_logic_l 164.all;use ieee.std_logic_arith.all;entity s isport(cint:in std_logic;a,b:in unsigned(7 downto 0); cout:out std_logic

10、;sum:out unsigned(7 downto 0); end s;architecture s of s issum<=t(0)(7 downto 0) when sel= n00" else t(2)(7 downto 0) when sel= n0r' else t(l)(7 downto 0) when sel=n10n else t(2)(7 downto 0) when sel="ll"cout<=t(0)(8) when sel="00 n else t(2)(8) when sei 二” 01" els

11、e t(l)(8) when sei 二"10" else t(2)(8) when sel=" 11"end cp;9. Binary-to-Gray code converter, library ieee;use ieee.std_logic_l 164.all;entity s isgeneric (n: integer: =4);port(input:in std_logic_vector(n-1 downto 0); output:signal la,lb,ls,lc:unsigned(8 downto 0); begin la<= !

12、0&a;lbv='O &b;lc<= n00000000n&cint;ls<=la+lb+lc;sum<=ls(7 downto 0);cout<=ls(8);end s;&有符號，無符號數(shù)加法器減法器out std_logic_vector(n-1 downto 0); end s;architecture s of s isbeginoutput(n-1 )<=input(n-1);output(n-2 downto 0)<=input(n-1 downto input(n-2 downto 0);end s ;1

13、0. Comparato 匚 library ieee;use ieee.std_logic_l 164.all;Library ieee;use ieee.std_logic_arith.all;Use ieee. std_logic_ 1164. all;entity s isUse ieee. std_logic_arith. all;port(a,b:in unsigned(7 downto 0);Entity s isport(a,b:in unsigned(7 downto 0);cin:in std_logic;sei:in std_logic_vector( 1 downto

14、0); sum:out std_logic_vector(7 downto 0); cout: out std_logic);End s;sei:in std_logic; xl,x2,x3: out std_logic);l)xorend s;architecture s of s issignal a_signed,b_signed: signed(7 downto 0);signal t:std_logic_vector( 1 to 6);begin a_signed<=conv_signed(a, 8);b_signed<=conv_signed(b,8);architec

15、ture cp of s issignal tl,t2:unsigned(8 downto 0);signal t3,t4:signed(8 downto 0);signal sl,s2:unsigned(8 downto 0);signal s3,s4:signed(8 downto 0);signal cin0:unsigned(l downto 0);signal cinl:signed(l downto 0); type tt is array(0 to 3)oft(l)<-1' when a>b else 'O' t(2)v=T when a=b

16、else O;t(3)<-1' when a<b else 'O't(4)v=T when a_signed>b_signed else 'O' t(5)<='l' when a_signed=b_signed else 'O' t(6)v=T when a_signed<b_signed else 'O' xl<=t(l) when sel=*O' else t(4); x2<=t(2) when sel=*O' else t(5); x3<

17、=t(3) when sel='O' else t(6);end s;11 .One-digit counter library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity s is port(clk,rst:in std_logic; digit:out std_logic_vector(6 downto 0); end s; architecture s of s isbegin process(clk) variable t:integer range 0 to 10; begi

18、nif(rst=*r )thent:二 0;elseif(clk'event and elk-1') then t:=t+l; if(t>=10) thent:二 0;end if; end if;end if; case t is when 0=>digit<= ,1111110 n ;when 1 二 digitviOllOOOO ；” when 2=>digit<= n110110r ,;when 3=>digitv=”ll 1100；1 wh”en4=>digit<="0110011"when 5=&g

19、t;digit<=" 1011011" when 6=>digit<=" 1011 111" when 7=>digit<="l 110000" when 8=>digit<= Hlllllir ,;when 9=>digitv=” 11110；11 w”henothers=>null;end case;end process;end s;12.Two-digit counter with SSD output.library ieee;use ieee.std_logic_116

20、4.all;entity s is port(clk,rst:in std_logic;digitl,digit2:out std_logic_vector(6 downto 0): end s ;architecture s of s is begin process(clk) variable tl,t2 :integer range 0 to 10; begin if(rst=*r ) thentl:=O;tl:=O;elsetl:=tl+l; if(tl=10) thentl:二 0;t2:=t2+l;if(t2=10) then t2:=0;end if;end if;end if;

21、end if; case tl iswhen 0 二 digitlv 二” 1111110"when l=>digitlv= ”0110000 ”when 2=>digitl<= n110110r ,;when 3=>digitl<=' ,111100r ,;when 4=>digitl<= n0110011"when 5=>digitl<="1011011"when 6=>digit 1 <=" 1011111"when 7=>digitl<= n

22、 1110000"when 8=>digit 1 <="lllllir*;when 9=>digit 1 v= ” 11110；11 when others=>null;end case;case t2 iswhen 0 二 digit2v= ” 1111110'*;when l=>digit2<=when 2=>digit2<=n0110000 n;n 1101101n;when 3=>digit2<= n 1111001"when 4=>digit2<= n01100ir ,;wh

23、en 5=>digit2<= H10110ir'when 6=>digit2<= n1011111H;when 7=>digit2<= H1110000 n;when 8=>digit2<= lllllirwhen9=>digit2<="1111011"if(clk'event and elk-T) thenend s;when others=>null; end case;end process; end s;13.Shift register. library ieee; use ieee

24、.std_logic_l 164.all;entity s isgeneric(n: integer:=4); port(rst,clk,d:in std_logic; q: out std_logic);end s; architecture s of s is begin process(clk)variable t: std_logic_vector(n-1 downto 0); begin if(rst 二 T) then t:=(others=>'0*);else if(clk*event and clk='r )then t:=d&t(n-l down

25、to 1); end if; end if;q<=t(O);end process; end s; 14.Simple barrel shifter. library ieee;use ieee.std_logic_l 164.all; entity s isgeneric(n: integer:=8);port(input:in std_logic_vector(n-1 downto 0); shift: in integer range 0 to 1;output:out std_logic_vector(n-1 downto 0); end s ; architecture s o

26、f s isbegin process(shift,input)begin if(shift=O) then output<=input; else output(0)<=*0'for i in 1 to input'high loop output(i)<=input(i-1); end loop;end if;end process;end s;15. Leading zeros. library ieee;use ieee.std_logic_l 164.all;entity s isport(data:in std_logic_vector(6 dow

27、nto 1);zeros:out integer range 0 to 6);end s; architecture s of s is beginprocess(data) variable t:integer range 0 to 6;begin t:=0;for i in data'range loop case data(i) is when '0->t:=t+l; when others=>exit; end case; end loop; zeros<=t;end process; end s;16. Count ones. library iee

28、e;use ieee.std_logic_l 164.all; entity s isport(data:in std_logic_vector(8 downto 1);ones:out integer range 0 to 8);end s; architecture s of s is beginprocess(data) variable t:integer range 0 to 8;begint:=0;for i in data'range loop if(data(i)=*r )then t:=t+l; end if;end loop; ones<=t;end proc

29、ess; end s;17. Event counter.library ieee;use ieee.std_logic_l 164.all;use ieee.std_logic_unsigned.all;entity s is port(clk:in std_logic;opt:out std_logic_vector(3 downto 0):library ieee;use ieee.std_logic_l 164.all;architecture s of s is signal tl ,t2:std_logic_vector(3 downto 0);begin process(clk)

30、 begin if(clk*event and clk='r )then tl<=tl+l;if(tl> ”1000” ) then tlv= ” 000；0 ” end if; end if;end process; process(clk) beginif(clk*event and clk='O') then t2<=t2+l; if(t2> ” 01)11th”en t2v= ” 00；00 e”nd if; end if;end process; opt<=tl+t2; end s;18. Priority encoder. li

31、brary ieee;use ieee.std_logic_l 164.all; entity s isgeneric(n: integer:=3);port(x:in std_logic_vector(2*3-1 downto 0); y:out std_logic_vector(n-1 downto 0); end s; architecture s of s is beginprocess(x) begin if(x(7)='l') then nny<= lH ; elsif(x(6)-1') then y<=n110n;elsif(x(5)-1

32、9;) then y<= ,'101n; elsif(x(4)-1') then y<= n100n;elsif(x(3)-T) then y<= n011"elsif(x(2)=*r ) then y<= n010n;elsif(x(l)='r )then nn y<= 001 ; else y<= n000n;end if;end process;end s;19. Generic frequency divider.entity s is generic(n:integer:=6); port(clk:in std_l

33、ogic;q: buffer std_logic); end s ;architecture s of s isbegin process(clk) variable t:integer range 0 to 255; beginif(clk'event and elk-F) then t:=t+l;if(t=n/2) then q<=not q;t:=0;end if;end if;end process;end s;20.Signal generato T. library ieee;use ieee.std_logic_l 164.all; entity s is port

34、(clk:in std_logic;wave:out std_logic);end s;architecture s of s istype states is(zero,one,two,three,four,five,six,seven) signal pr_state,nx_state: states;signal temp:std_logic; beginprocess(clk) begin if(clk'event and elk-1') then pr_state<=nx_state wave<=temp; end if;end process; proc

35、ess(pr_state) begin case pr_state is when zero=>temp<='0'nx_state<=one; when one=>temp< =,l'nx_state<=two;when two=>temp<=*0'nx_state<=three; when three=>temp<='l'nx_state<=four; when four=>temp< =, 1 *;nx_state<=five; when five=&g

36、t;temp<='l*;nx_state<=six; when six=>temp<='O'nx_state<=seven; when seven=>temp<='O'nx_state<=zero; when others=>null;end case; end process;end s;21 .Pulse-sequence detector library ieee; use ieee.std_logic_l 164.all;entity s is port(d,clk,rst:in bit;q:

37、out bit);end s; architecture s of s is type states is (one,two,three,four); signal pr_state,nx_state: states;begin process(rst,clk)beginif(rst 二 T) then pr_state<=one; elsif(clk'event and clk=T) then pr_state<=nx_state;end if;end process; process(d,pr_state) begin case pr_state is when one

38、=> q<=O; if(d=T) then nx_state<=two; else nx_state<=one;end if;when two=>q<=O; if(d=T) then nx_state<=three; else nx_state<=one;end if;when three=>q<=O; if(d=T) then nx_state<=four; else nx_state<=one;end if;when four=> q<=T； if(d=T) then nx_state<=fbur;e

39、lse nx_state<=one; end if;end case; end process;end s;22. Parallel/serial converter library ieee;use ieee.std_logic_l 164.all; entity s isport(d:in std_logic_vector(7 downto 0) load,clk:in std_logic; dout:out std_logic);end s;architecture s of s issignal t: std_logic_vector(7 downto 0); begin pro

40、cess(clk) beginif(clk'event and elk-F) then if(load='r )then t<=d;elset<=t(6 downto 0)&'0 ； end if;end if; end process; dout<=t(7);end s;24.Serial data receiver.library ieee;use ieee.std_logic_l 164.all;entity s isport(din,clk,rst: in bit;data: out bit_vector(6 downto 0); er

41、r,data_valid:out bit);end s;architecture s of s isbeginprocess(clk,rst)variable reg:bit_vector( 10 downto 0);variable count:integer range 0 to 10; variable temp:bit;beginif(rst='l') thencount:=0;reg :=(reg'range=>'0'); temp:='0*; err<=*0' data_valid<='0 ,;els

42、if(clk'event and elk-1') then if(reg(0)= ,0, and din=T) thenoutl<-O f; nx_statel <=three; when three=> outl<-O f; nx_state 1 <=zero; end case; end process; process(clk,rst) begin if(rst 二 T) then pr_state2<=zero; elsif(clk*event and elk-T) then pr_state2<=nx_state2; end

43、if;end process;process(pr_state2)begincase pr_state2 is when zero=>out2<= , l,; nx_state2<=one;when one=> out2<=not elk; nx_state2<=two;when two=> out2v='0 ； nx_state2<=three;when three=> out2v='0 ； nx_state2<=zero; end case; end process; end s;26.Sequence detec

44、tor library ieee; use ieee.std_logic_l 164.all;entity s isport(xi,clk:in std_logic; zo:out std_logic);end s;architecture s of s is type states is(zero,one,two,three,four); signal pr,nx:states;beginprocess(clk)beginif(clk'event and elk-F) thenpr<=nx;end if;end process; process(pr,xi)wg(O):=T ； elsif(reg(O)='r )then count :=count+l; if(count<10) then reg(count):=din; elsif(count=10) then temp:=(reg(l) xor reg(2) xor reg(3) xor reg(4) xor reg(5) xor reg(6) xor reg(7) xor reg(8)or not reg(9);err<=tem