輸入與非門、或非門版圖設(shè)計

1、課程名稱Course集成電路設(shè)計技術(shù)項目名稱Item二輸入與非門、或非門版圖設(shè)計與非門電路的版圖:惠冏:淳等溢) 一”=».、:l' R"II."».L 一*% ".<.、乙玄;:完案不片蜜三:!-m;-;-一二二w-r:?r<r:-；-:t:B-rllt-':d AKA、>ll-1-4 ;以 p:!ri:p:筋方始mm 蒙汶浸 ,:-/-.'.'''.'|"<,112 :<-:-"d- 也至0Z左右羽K符n:!-:j:fij!r:7-m&

2、#39;l.L'si?>，>1-X:工 二nVEVV 上 。盤.出七1;!FiW腐J域比J滋初慟一勰h-.aNFa T- r L h r % . . . .1 ,1. 11二.：二二：，.；二一 匕一'I匕 F、«.匕 nl/'Lrl- ”,4|.:-,.1|"'.二"'.,+|1'.'.I.11'.I.“1-.,.spc文件(瞬時分析)：* Circuit Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00 ;*

3、 TDB File: E:cmosyufeimen, Cell: Cell0* Extract Definition File: C:Program FilesTanner EDAL-Editsprmorbn20.ext* Extract Date and Time: 05/25/2011 - 10:03.include H:ml2_125.mdVPower VDD GND 5va A GND PULSE (0 5 0 5n 5n 100n 200n)vb B GND PULSE (0 5 0 5n 5n 50n 100n).tran 1n 400n.print tran v(A) v(B)

4、v(F) * WARNING: Layers with Unassigned AREA Capacitance.* <Poly Resistor* <Poly2 Resistor* <N Diff Resistor* <P Diff Resistor* <N Well Resistor* <P Base Resistor* WARNING: Layers with Unassigned FRINGE Capacitance.* <Pad Comment* <Poly Resistor* <Poly2 Resistor>* <N

5、Diff Resistor>* <P Diff Resistor>* <N Well Resistor>* <P Base Resistor>* <Poly1-Poly2 Capacitor* WARNING: Layers with Zero Resistance.* <Pad Comment* <Poly1-Poly2 Capacitor>* <NMOS Capacitor>* <PMOS Capacitor>* NODE NAME ALIASES* 1 = VDD (34,37)* 2 = A (2

6、9.5,6.5)* 3 = B (55.5,6.5)* 4 = F (42.5,6.5)* 6 = GND (25,-22)M1 VDD B F VDD PMOS L=2u W=9u AD=99p PD=58u AS=54p PS=30u* M1 DRAIN GATE SOURCE BULK (47.5 14.5 49.5 23.5)M2 F A VDD VDD PMOS L=2u W=9u AD=54p PD=30u AS=99p PS=58u* M2 DRAIN GATE SOURCE BULK (39.5 14.5 41.5 23.5)M3 F B 5 GND NMOS L=2u W=9

7、.5u AD=52.25p PD=30u AS=57p PS=31u* M3 DRAIN GATE SOURCE BULK (47.5-18 49.5 -8.5)M4 5 A GND GND NMOS L=2u W=9.5u AD=57p PD=31u AS=52.25p PS=30u* M4 DRAIN GATE SOURCE BULK (39.5 -18 41.5 -8.5)* Total Nodes: 6* Total Elements: 4* Extract Elapsed Time: 0 seconds.END與非門電路仿真波形圖（瞬時分析）11 i i 11111 u jTTw+r

8、+wH ILi JlIllii !+<+T+4+<ww4+i,wM444T+T<+rt4+1H444m«+H,i+44,H+,w4+i+M4+i+*T«44T+4wHiw«4+H,wM4+i+«4+t,r+44+4w+14w+t<4+tT»< 111 d . I Htmw+t+wJ 11 u i11 L . 1111 ifjcmosyu£eimen. cut I '2 口口 Timers).：0D£cmosyii£etmen. cut0到LOO1502002 切300洶Time

9、 (as) fkinosXyufeinien cut050：001502002503t»150Ttmp TnQ.spc文件(直流分析)：* Circuit Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00 ;* TDB File: E:cmosyufeimen, Cell: Cell0* Extract Definition File: C:Program FilesTanner EDAL-Editsprmorbn20.ext* Extract Date and Time: 05/25/2011 - 10:

10、03 .include H:ml2_125.mdVPower VDD GND 5va A GND 5vb B GND 5.dc va 0 5 0.02 vb 0 5 0.02.print dc v(F)* WARNING: Layers with Unassigned AREA Capacitance.* <Poly Resistor* <Poly2 Resistor* <N Diff Resistor* <P Diff Resistor>* <N Well Resistor>* <P Base Resistor>* WARNING: La

11、yers with Unassigned FRINGE Capacitance.* <Pad Comment* <Poly Resistor>* <Poly2 Resistor>* <N Diff Resistor>* <P Diff Resistor>* <N Well Resistor>* <P Base Resistor>* <Poly1-Poly2 Capacitor>* WARNING: Layers with Zero Resistance.* <Pad Comment* <Pol

12、y1-Poly2 Capacitor>* <NMOS Capacitor>* <PMOS Capacitor>* NODE NAME ALIASES* 1 = VDD (34,37)* 2 = A (29.5,6.5)* 3 =B (55.5,6.5)* 4 =F (42.5,6.5)* 6 =GND (25,-22)M1 VDD B F VDD PMOS L=2u W=9u AD=99p PD=58u AS=54p PS=30u* M1 DRAIN GATE SOURCE BULK (47.5 14.5 49.5 23.5)M2 F A VDD VDD PMOS

13、 L=2u W=9u AD=54p PD=30u AS=99p PS=58u* M2 DRAIN GATE SOURCE BULK (39.5 14.5 41.5 23.5)M3 F B 5 GND NMOS L=2u W=9.5u AD=52.25p PD=30u AS=57p PS=31u* M3 DRAIN GATE SOURCE BULK (47.5-18 49.5 -8.5)M4 5 A GND GND NMOS L=2u W=9.5u AD=57p PD=31u AS=52.25p PS=30u* M4 DRAIN GATE SOURCE BULK (39.5 -18 41.5 -

14、8.5)* Total Nodes: 6* Total Elements: 4* Extract Elapsed Time: 0 seconds .END與非門電路仿真波形圖（直流分析）或非門電路的版圖:一 一 1 l lalllll I- 一 二”二三二二-:>:S:EI7?7=:;,.:-上,:-*'-=:?-;之;?唁-:1:'-:-<“-:1?-:? SB 9.2 - - 9 - - - - -二二三:三2/沏司777%一9- 1T :!工行:匕 以 r 1>M'-.J>nm.:-)7/忘比宵七常.spc文件(瞬時分析)：* Circui

15、t Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00 ;* TDB File: E:cmoshuofeimen, Cell: Cell0* Extract Definition File: C:Program FilesTanner EDAL-Editsprmorbn20.ext* Extract Date and Time: 05/25/2011 - 10:04.include H:CMOSml2_125.mdVPower VDD GND 5va A GND PULSE (0 5 0 5n 5n 100n 200n

16、)vb B GND PULSE (0 5 0 5n 5n 50n 100n).tran 1n 400n.print tran v(A) v(B) v(F)* WARNING: Layers with Unassigned AREA Capacitance.* <Poly Resistor* <Poly2 Resistor* <N Diff Resistor* <P Diff Resistor>* <N Well Resistor>* <P Base Resistor>* WARNING: Layers with Unassigned FRI

17、NGE Capacitance.* <Poly Resistor>* <Poly2 Resistor>* <N Diff Resistor>* <P Diff Resistor* <N Well Resistor* <Pad Comment* <P Base Resistor* <Poly1-Poly2 Capacitor* WARNING: Layers with Zero Resistance.* <Pad Comment* <Poly1-Poly2 Capacitor* <NMOS Capacitor*

18、<PMOS Capacitor* NODE NAME ALIASES* 1=VDD (34,37)* 2=A (29.5,6.5)* 3=B (55.5,6)* 4=F (42.5,6.5)* 5=GND (25,-22)M1 6 A VDD VDD PMOS L=2u W=9u AD=54p PD=30u AS=49.5p PS=29u* M1 DRAIN GATE SOURCE BULK (39.5 14.5 41.5 23.5)M2 F B 6 VDD PMOS L=2u W=9u AD=49.5p PD=29u AS=54p PS=30u* M2 DRAIN GATE SOURC

19、E BULK (47.5 14.5 49.5 23.5)M3 F A GND GND NMOS L=2u W=9.5u AD=57p PD=31u AS=104.5p PS=60u* M3 DRAIN GATE SOURCE BULK (39.5 -18 41.5 -8.5)M4 GND B F GND NMOS L=2u W=9.5u AD=104.5p PD=60u AS=57p PS=31u* M4 DRAIN GATE SOURCE BULK (47.5-18 49.5 -8.5)* Total Nodes: 6* Total Elements: 4* Extract Elapsed

20、Time: 0 seconds .END或非門電路仿真波形圖(瞬時分析)e:Vmoshuofeiiaen. oxexmosmuofeunen. outTime (ns*,1 iX2002JQ300350Time (ns；e:cmoshuoBinien. oit.spc文件(直流分析)：* Circuit Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00 ;* TDB File: E:cmoshuofeimen, Cell: CellO* Extract Definition File: C:Program Files

21、Tanner EDAL-Editsprmorbn20.ext* Extract Date and Time: 05/25/2011 - 10:04.include H:CMOSml2_125.mdVPower VDD GND 5va A GND 5vb B GND 5.dc va 0 5 0.02 vb 0 5 0.02.print dc v(F)* WARNING: Layers with Unassigned AREA Capacitance.* <Poly Resistor* <Poly2 Resistor* <N Diff Resistor* <P Diff R

22、esistor* <N Well Resistor* <P Base Resistor>* WARNING: Layers with Unassigned FRINGE Capacitance.* <Poly Resistor>* <Poly2 Resistor>* <N Diff Resistor>* <P Diff Resistor>* <N Well Resistor>* <Pad Comment* <P Base Resistor>* <Poly1-Poly2 Capacitor* W

23、ARNING: Layers with Zero Resistance.* <Pad Comment* <Poly1-Poly2 Capacitor>* <NMOS Capacitor>* <PMOS Capacitor>* NODE NAME ALIASES* 1 = VDD (34,37)* 2 = A (29.5,6.5)* 3 = B (55.5,6)* 4 = F (42.5,6.5)* 5 = GND (25,-22)M1 6 A VDD VDD PMOS L=2u W=9u AD=54p PD=30u AS=49.5p PS=29u* M

24、1 DRAIN GATE SOURCE BULK (39.5 14.5 41.5 23.5)M2 F B 6 VDD PMOS L=2u W=9u AD=49.5p PD=29u AS=54p PS=30u* M2 DRAIN GATE SOURCE BULK (47.5 14.5 49.5 23.5)M3 F A GND GND NMOS L=2u W=9.5u AD=57p PD=31u AS=104.5p PS=60u* M3 DRAIN GATE SOURCE BULK (39.5 -18 41.5 -8.5)M4 GND B F GND NMOS L=2u W=9.5u AD=104

25、.5p PD=60u AS=57p PS=31u* M4 DRAIN GATE SOURCE BULK (47.5-18 49.5 -8.5)* Total Nodes: 6* Total Elements: 4* Extract Elapsed Time: 0 seconds.END或非門電路仿真波形圖(直流分析)：h: umos huulchnen de.out課程名稱Course集成電路設(shè)計技術(shù)項目名稱Item二輸入與非門、或非門 版圖設(shè)計目的Objective1 .掌握利用E-EDIT進彳T IC設(shè)計方法，設(shè)計二輸入與非門版圖并仿真2 .掌握利用L-EDIT進彳T IC設(shè)計方法，設(shè)計二輸入或非門版圖并仿真3 .領(lǐng)會并掌握版圖設(shè)計最優(yōu)化實現(xiàn)方法。內(nèi)容（