ZYNQ平臺架構(gòu)AXI總線協(xié)議

1、目錄一、 ZYNQ平臺的硬件架構(gòu)二、 AXI 協(xié)議三、 ZYNQ的部分可重構(gòu)配置背景簡介背景簡介ZYNQ7000系列ARM+FPGA結(jié)構(gòu) XILINX傳統(tǒng)FPGA的局限性？ZYNQ平臺的硬件架構(gòu)架構(gòu)：1、PS（處理器系統(tǒng)）（流程控制等串行設(shè)計） 2、PL（可編程邏輯）（并行算法設(shè)計）ZYNQ平臺的硬件架構(gòu)PS由四塊組成由四塊組成：1、APU(應(yīng)用處理單元)2、內(nèi)存接口3、IO外設(shè)（USB2.0、Ethernet、CAN、SPI、UART、IIC、SD/SDIO、GPIO）4、互連線（APU、IOP和內(nèi)存單元相互連接，并通過一個多層的AXI互連線與PL連接）ZYNQ平臺的硬件架構(gòu)APU結(jié)構(gòu)1、A

2、CP2、SCU3、Cortex-A9(x2)4、L1 32KB（I/D） 共享L2 512KBZYNQ平臺的硬件架構(gòu)內(nèi)存接口ZYNQ平臺的硬件架構(gòu)IO外設(shè) RGMII接口ZYNQ平臺的硬件架構(gòu)AXI總線架構(gòu)AXI_HP 用于PL的四個高性能、高帶寬主接口，位寬可配64/32，可訪問PS的DDR3控制器和PS的片上RAM資源AXI_GP四個通用接口（兩主兩從），每個位寬32，可訪問PS的DDR3控制器，PS片上RAM資源和其他從設(shè)備AXI_ACP用于PL的一個加速一致性主端口，提供快速訪問CPU，可選的L1或L2緩存一致性ZYNQ平臺的硬件架構(gòu)PL組成：1、可配置邏輯塊(CLB)2、36KB塊B

3、RAM3、數(shù)字信號處理DSP48E1 Slice4、可編程IO5、時鐘管理6、XADCZYNQ平臺的硬件架構(gòu)可編程IOZYNQ平臺的硬件架構(gòu)XADC模塊XADC模塊ZYNQ平臺的硬件架構(gòu)ZYNQ平臺的硬件架構(gòu)AXI協(xié)議AXI4.0是ARM公司提出的AMBA 3.0協(xié)議的升級版，是一種高性能、高帶寬、低延遲的片內(nèi)總線。AXI協(xié)議AXI協(xié)議具有如下特點(diǎn)：總線的地址/控制和數(shù)據(jù)通道是分離的；支持不對齊的數(shù)據(jù)傳輸；在突發(fā)傳輸中，只需要首地址；同時具有分離讀/寫數(shù)據(jù)通道；更加容易進(jìn)行時序收斂。通道介紹AXI接口具有5個獨(dú)立通道：寫地址通道（Write address channel，AW）；寫數(shù)據(jù)通道（

4、Write data channel，W）；寫響應(yīng)通道（Write response channel，B）；讀地址通道（Read address channel，AR）；讀數(shù)據(jù)通道（Read data channel，R）；每個通道都是一個獨(dú)立的AXI握手協(xié)議。READY/VALID握手機(jī)制每個通道都有一對VALID/READY信號發(fā)送方用VALID指示什么時候數(shù)據(jù)或控制信息是有效的；接收方用READY指示可以接收數(shù)據(jù)或控制信息。傳輸發(fā)生在VALID和READY信號同時為高的時候。通道之間的關(guān)系：各個通道都可以獨(dú)立握手，相互之間的關(guān)系是靈活的；讀數(shù)據(jù)必須總是跟在與其數(shù)據(jù)相關(guān)聯(lián)的地址之后；寫響應(yīng)

5、必須總是跟在與其相關(guān)聯(lián)的寫交易的最后出現(xiàn)。READY/VALID握手機(jī)制讀交易中的握手之間的依賴關(guān)系寫交易中的握手之間的依賴關(guān)系讀交易過程寫交易過程讀猝發(fā)交易讀猝發(fā)交易過程中典型信號的交互過程寫猝發(fā)交易寫猝發(fā)交易過程中典型信號的交互過程重疊猝發(fā)交易重疊猝發(fā)交易過程中典型信號的交互過程AXI 互聯(lián)AXI互聯(lián)結(jié)構(gòu)模型包括： 直通模式 只轉(zhuǎn)換模式 N-1 互聯(lián)模式 1-N 互聯(lián)模式 N-M 互聯(lián)模式互聯(lián)模式直通模式只轉(zhuǎn)換模式N-1互聯(lián)模式1-N互聯(lián)模式N-M互聯(lián)模式共享寫和讀地址仲裁結(jié)構(gòu)N-M互聯(lián)模式稀疏互聯(lián)寫和讀數(shù)據(jù)通道Partial Reconfiguration in ZynqBased on

6、 modulesBased on diversitiesPartial Reconfiguration in ZynqWhat Problems Does It Solve?System cost, size, and power constraints Multiplex hardware functions Evolving protocol and industry standards Reprogramability as standards evolve Mission critical uptime Update on the fly while system still runn

7、ing Long design implementation cycle times Accelerate development with focus on reconfigurable partitionSome TerminologyReconfigurable Partition (RP) The physical location of FPGA resources selected for partial reconfiguration Static logic Everything but the RP(s) The part of the design that doesnt

8、change Reconfigurable Module (RM) Logic that lives in the RP Defined by hardware interfaces and ports Functional variants for associated RP Different protocol, task, filter, etc. Design FlowStructure the design Separate functions into hierarchical blocks Identify functions to be made into partitions

9、 Identify set of signals that will become RP interfaceDesign Flow Synthesize Bottom-up Static “top” and RMs synthesized seperatelyDesign FlowAssemble static design with RM variants RMs replace black boxes in static “top”Design FlowFloorplan the RPs and run DRCs Define regions and logic resources to

10、be includedDesign FlowImplementation Configurations for static logic and all reconfigurable modules Repeat for all modulesDesign FlowVerify all configurations Ensure that static portions match identicallyDesign Considerations Vivado stores design data in checkpoints Save full design as a configurati

11、on checkpoint for bitstream creation RMs can also be stored as their own checkpoints Save static-only checkpoint to be reused across multiple configurations Routed static checkpoint can remain open in memory Results are locked at the routing level Design Considerations Design Considerations Partition Pins are junctions between static and reconfigured logic Interface wires can be broken at interconnect tile site Anchor mid-route between static and reconfigurable logic No overhead at reconfigurable partition interface Design Considerations Not Ev