電子設計自動化多路波形發(fā)生器的設計

1、電子設計自動化多路波形發(fā)生器 一、實驗題目要求 1、對輸入時鐘信號進行分頻，實現三路互差120的信號。 2、實現輸出信號的占空比控制 clk:輸入時鐘信號 resetb：同步復位信號（低電平有效）div:輸入分頻控制信號(注意：6n分頻) ctrl:占空比控制信號 ctrl=1時，占空比為1:1 ctrl=2時,占空比為1:2 ctrl=3時,占空比為2:1 A,B,C：三路輸出信號 二、設計思路及方案 1、多路發(fā)生器的基本原理分頻器而且是可調的。因此可以先設計多個子程序分別使得信號發(fā)生器的產生的占空比分別為1:1,1:2,2:1，因此先設div:integer range 1 to 4;，通

2、過信號賦值（tmp,tmp1,tmp2）賦給輸出信號A,B,C。通過n改變輸出頻率，定義各個變量。 2、當resetb=0時,countQ=0當resetb=1時，給脈沖時先定義分頻比如果countQ (6*div-1)時countQ = countQ 否則countQ為0。 3、 當ctrl=01時即H:L=1:1時 如果countQ 3*div時tmp=0;否則tmp=1 如果countQ (6*div-2)時tmp1= 1;否則tmp1=0; 如果countQ (4*div-1)時tmp2= 0; 否則 tmp2=1; A=tmp:B=tmp1:C=tmp2同理,當ctrl=10時即H:

3、L=1:2時 當ctrl=11時即H:L=2:1時。 其中,公式推導如下當div=1,ctrl=01時 當div=2,ctrl=01時 countQ6 countQ12 A:0 0 0 1 1 1 A:0 0 0 0 0 0 1 1 1 1 1 1 B:1 1 0 0 0 1 B:1 1 1 1 0 0 0 0 0 0 1 1 C:0 1 1 1 0 0 C:0 0 1 1 1 1 1 1 0 0 0 0 A:countQ3時tmp=0 A:countQ6時tmp=0 Else tmp=1 Else tmp=1 B:countQ4時tmp=1 B:countQ10,tmp=1 Else tmp

4、=0 Else tmp=0 C:countQ3時tmp=0 C: countQ7時tmp=0 Else tmp=1 Else tmp=1 同理ctrl=10ctrl=11. 當ctrl=01時 if(countQ 3*div) then tmp= 0;else tmp=1;if(countQ (6*div-2) then tmp1= 1;else tmp1=0; if(countQ (4*div-1) then tmp2= 0;else tmp2=1; 當ctrl=10時 if(countQ 4*div) then tmp= 0;else tmp=1; if(countQ 2*div ) th

5、en tmp1= 1;else tmp1=0; if(countQ (4*div-1) then tmp2= 0; else tmp2=1; 當ctrl=11時 if(countQ 2*div) then tmp= 0;else tmp=1; if(countQ (4*div-1) then tmp1= 1;else tmp1=0; if(countQ 4*div ) then tmp2= 1;else tmp2=0; 將信號tmp 賦給A; tmp1 賦給B;tmp2 賦給 C ;三、流程圖 Reset=0?10000是否有信號輸入tmp,tmp1，tmp2=0是否判定ctrl的值123tm

6、p=a tmp1=btmp2=c調用相應的子程序四、實驗程序及其波形 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fashengq is port ( clk:in std_logic; aclk:out std_logic; bclk:out std_logic; cclk:out std_logic; resetb:in std_logic; div:in std_logic_vector(1 downto 0

7、); ctrl:in std_logic_vector(1 downto 0) ); end fangshengq; architecture behave of fangshengq is signal tmp:std_logic; signal tmp1:std_logic; signal tmp2:std_logic; signal cnt0:integer range 0 to 5:=0; signal cnt1:integer range 0 to 11:=0; signal cnt2:integer range 0 to 17:=0; signal cnt3:integer ran

8、ge 0 to 23:=0; begin process(clk,resetb,div,ctrl) begin if clkevent and clk=1 then if resetb=0 then cnt0=0; cnt1=0; cnt2=0; cnt3=0; tmp=0; tmp1=0; tmp2=0; elsif resetb=1 then cnt0=cnt0+1; cnt1=cnt1+1; cnt2=cnt2+1; cnt3 case div is when 00= case cnt0 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;

9、tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2=0;cnt0 case cnt1 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt

10、1 case cnt2 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;

11、tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt2 case cnt3 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;

12、tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt3 case div is when 00= case cnt0 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tm

13、p=1;tmp1=0;tmp2=0;cnt0 case cnt1 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2=0;cnt1 case cnt2 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tm

14、p1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2=0;cnt2 case cnt3 i

15、s when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tm

16、p=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2=0;cnt3 case div is when 00= case cnt0 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt0 case cnt1 is when 0=tmp=

17、0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt1 case cnt2 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=

18、0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt2 case cnt3 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp