杭電計(jì)組實(shí)驗(yàn)5-存儲(chǔ)器設(shè)計(jì)實(shí)驗(yàn)

1、實(shí)驗(yàn)報(bào)告 2018 年 5 月 5 日 成績(jī)： 姓名陽(yáng)光男學(xué)號(hào)16041321班級(jí)16052317專(zhuān)業(yè)計(jì)算機(jī)科學(xué)與技術(shù)課程名稱(chēng)計(jì)算機(jī)組成原理與系統(tǒng)結(jié)構(gòu)試驗(yàn)任課老師張翔老師指導(dǎo)老師張翔老師機(jī)位號(hào)默認(rèn)實(shí)驗(yàn)序號(hào)5實(shí)驗(yàn)名稱(chēng)實(shí)驗(yàn)五 存儲(chǔ)器設(shè)計(jì)實(shí)驗(yàn)實(shí)驗(yàn)時(shí)間2018/5/12實(shí)驗(yàn)地點(diǎn)1教211實(shí)驗(yàn)設(shè)備號(hào)個(gè)人電腦、Nexys3開(kāi)發(fā)板 一、實(shí)驗(yàn)程序源代碼存儲(chǔ)器頂層電路代碼：module top_RAM_B(Mem_Addr,C,Mem_Write,Clk,LED);input 7:2Mem_Addr;/開(kāi)關(guān)的3、4、5、6、7、8位input Mem_Write,Clk;/clk為按鍵C9，讀寫(xiě)使能信號(hào)為按鍵C

2、4，0為讀，1為寫(xiě)input 1:0C;/選擇寫(xiě)入數(shù)據(jù)+讀操作時(shí)選擇顯示字節(jié),為開(kāi)關(guān)1、2位output reg 7:0LED;wire 31:0M_R_Data;/存在存儲(chǔ)器里的32位讀出數(shù)據(jù)reg 31:0M_W_Data;/寄存在暫存器的32位寫(xiě)入數(shù)據(jù)RAM_B test_ram ( .clka(Clk), /輸入時(shí)鐘信號(hào) .wea(Mem_Write), /輸入讀寫(xiě)信號(hào) .addra(Mem_Addr7:2), /輸入5位地址信號(hào) .dina(M_W_Data), /寫(xiě)入32位數(shù)據(jù) .douta(M_R_Data) /讀出32位數(shù)據(jù));always(*)begin LED=0;/初始化

3、 M_W_Data=0;/初始化 if(!Mem_Write)/讀操作 begin case(C) 2'b00:LED=M_R_Data7:0;/讀出數(shù)據(jù)的0-7位 2'b01:LED=M_R_Data15:8;/讀出數(shù)據(jù)的8-15位 2'b10:LED=M_R_Data23:16;/讀出數(shù)據(jù)的16-23位 2'b11:LED=M_R_Data31:24;/讀出數(shù)據(jù)的24-31位 endcase end else begin case(C) 2'b00:M_W_Data=32'h0055_7523;/寫(xiě)入第一個(gè)數(shù)據(jù)2'b01:M_W_Da

4、ta=32'h1234_5678;/寫(xiě)入第二個(gè)數(shù)據(jù)2'b10:M_W_Data=32'h8765_4321;/寫(xiě)入第三個(gè)數(shù)據(jù)2'b11:M_W_Data=32'hffff_ffff;/寫(xiě)入第四個(gè)數(shù)據(jù)endcase endendendmodule測(cè)試代碼：module test;/ Inputsreg clka;reg 0:0 wea;reg 5:0 addra;reg 31:0 dina;/ Outputswire 31:0 douta;/ Instantiate the Unit Under Test (UUT)RAM_B uut (.clka(clk

5、a), .wea(wea), .addra(addra), .dina(dina), .douta(douta);initial begin/ Initialize Inputsclka = 0;wea = 0;addra = 0;dina = 0;/ Wait 100 ns for global reset to finish#100; / Add stimulus hereclka = 1;wea = 0;addra = 6'b000001;dina = 32'h0000_0003;#100;clka = 0;wea = 0;addra = 6'b000001;di

6、na = 32'h0000_0607;#100;clka = 1;wea = 1;addra = 6'b000001;dina = 32'hFFFF_FFFF;#100;clka = 0;wea = 1;addra = 6'b000001;dina = 32'hFFFF_FFFF;end endmodule二、仿真波形三、電路圖 頂層電路模塊 頂層電路內(nèi)部結(jié)構(gòu)：四、引腳配置（約束文件）NET "Clk" LOC = C9;NET "LED4" LOC = M11;NET "LED3" LOC =

7、 V15;NET "LED2" LOC = U15;NET "LED1" LOC = V16;NET "LED0" LOC = U16;NET "Mem_Addr7" LOC = U8;NET "Mem_Addr6" LOC = N8;NET "Mem_Addr5" LOC = M8;NET "Mem_Addr4" LOC = V9;NET "Mem_Addr2" LOC = T10;NET "Mem_Write"

8、LOC = C4;NET "Mem_Addr3" LOC = T9;NET "C1" LOC = T5;NET "C0" LOC = V8;NET "LED7" LOC = T11;NET "LED5" LOC = N11;NET "LED6" LOC = R11;五、思考與探索(1)讀操作實(shí)驗(yàn)結(jié)果記錄表存儲(chǔ)器地址 初始化數(shù)據(jù) 讀出數(shù)據(jù) 寫(xiě)入新數(shù)據(jù) 讀出數(shù)據(jù)5b000000 32b00000000 32b00000000 32'h0055_7523 32'h0

9、055_75235b000001 32b00000001 32b00000001 32'h0055_7523 32'h0055_7523 5b000002 32b00000002 32b00000002 32'h0055_7523 32'h0055_7523 5b000003 32b00000003 32b00000003 32'h0055_7523 32'h0055_7523 5b000004 32b00000004 32b00000004 32'h0055_7523 32'h0055_7523 5b000005 32b00000005 32b00000005 32'h0055_7523 32'h0055_7523 5b000006 32b00000006 32