教案成果講稿

1、Terasic TechnologiesCompany IntroductionOutlineOutlinen DE1-SoC快速入門n SoC FPGA設(shè)計(jì)流程n DE1-SoC硬件實(shí)驗(yàn)n DE1-SoC軟件實(shí)驗(yàn)n DE1-SoC進(jìn)階應(yīng)用DemoDE1SoC快速入門開發(fā)設(shè)計(jì)軟件n Altera Quartusn Altera SoC Embedded Design Suite實(shí)驗(yàn)文件目錄內(nèi)容cdDE1-SoC開發(fā)板光盤.內(nèi)有原理圖,設(shè)計(jì)范例等lab本次實(shí)驗(yàn)課所使用到的設(shè)計(jì)范例tool實(shí)驗(yàn)中所需要的驅(qū)動(dòng),軟件工具(Quartus, EDS.etc.).DE1SoC Mode Select Sw

2、itchMSEL4:0設(shè)定模式描述10010ASFPGA configured from EPCQ (default)01010FPPx32FPGA configured from HPS software: Linux00000FPPx16FPGA configured from HPS software: U-Boot, with image stored on the SD card, like LXDE Desktop or console Linux with frame buffer edition.DE1SoC連接設(shè)定n USB Blaster IIn UART-to-USBn

3、Power Jack安裝USB Blaster II驅(qū)動(dòng)n USB Blaster II :FPGA code, Debug HPS / FPGA.sof入FPGA測(cè)試安裝UARTtoUSB驅(qū)動(dòng)設(shè)定串口終端工具n Speed : 115200n Serial Line :COMxn Connection : Serial在DE1SoC上運(yùn)行Linuxn 將MicroSD cardDE1-SoCSoC FPGA設(shè)計(jì)流程SoC FPGA系統(tǒng)開發(fā)流程SoC FPGA系統(tǒng)架構(gòu)n 處理器 4000 MIPs (up to 800Mhz per core) 雙核ARM Cortex-A9處理器處理引擎 N

4、EON 豐富的內(nèi)嵌設(shè)備 32-KB L1 Caches每核 512-KB L2 Cachen 硬核內(nèi)存器 支持DDR2, DDR3和LPDDR2 支持ECCn 高帶寬通道 HPS to FPGA FPGA to HPS FPGA to HPS SDRAMHPS IP Featuresn 雙核ARM Cortx-A9處理器器n SDRAMn DMA器n 2 Ethernet MACsn NAND, QSPI, SD和器MMC flashn Serial Interface器- 2 USB OTG- 2 SPI master- 2 SPI slave器器器器- 4 I2C- 2 CANn 2串口n

5、 GPIOSoC FPGA 設(shè)計(jì)理念n FPGA: 看起來(lái)像FPGA 用起來(lái)像FPGA 標(biāo)準(zhǔn)的FPGA開發(fā)流程 使用傳統(tǒng)的開發(fā)工具: Qurtus II, Qsys, Signal TabII ,System Console , ProgrammerARM HPS: 看起來(lái)像ARM處理器系統(tǒng) 用起來(lái)像ARM處理器系統(tǒng) 傳統(tǒng)的ARM處理器開發(fā)流程 使用傳統(tǒng)的ARM處理器開發(fā)工具:nARM Cortex-A9 cor/debuer JTAG toolsro ram traceSoC硬件設(shè)計(jì)流程創(chuàng)建Quartus IIQsys系統(tǒng)集成工具n 使用GUI接口來(lái)做系統(tǒng)設(shè)計(jì)n 簡(jiǎn)化系統(tǒng)開發(fā)的復(fù)雜性n 為I

6、P模塊間自動(dòng)生成內(nèi)部連接提供標(biāo)準(zhǔn)開發(fā)平臺(tái)IP integrationCustom IP authoring IP verificationn設(shè)計(jì)可再利用n為Qsys系統(tǒng)增添組件n 包括HPS,現(xiàn)有的IP和客制化IP組件都可以在Qsys的component Library 呼叫使用n 可使用搜尋功能來(lái)找尋IPn 鼠標(biāo)點(diǎn)擊IP組件便可加入系統(tǒng)創(chuàng)建一個(gè)新的Qsys系統(tǒng)HPS組件設(shè)定HPS組件設(shè)定頁(yè)面n FPGA Interfacesn Peripheral MultiplexingHPClocksn SDRAMAdd Custom Components to Qsysn 使用Component Ed

7、itorn 支持標(biāo)準(zhǔn)Interfaces Avalon-MM (memory mapped) Avalon-ST (streaming) ARM AXI 3.0 & 4.0 ARM APB ARM AHB建立元件間的連線n 透過(guò)鼠標(biāo)左鍵點(diǎn)擊拉線建立連結(jié)n 透過(guò)鼠標(biāo)右鍵選擇特定接口來(lái)建立連接Generate Completed SystemSystem Consolen Quick system-level debug of Qsys systems Interactive Tcl Console Debug over various communication channels JTAG, U

8、SB or TCP/IP Read form or write to memory mapped components No processor requiredOn Chip Component DebugSoC硬件實(shí)驗(yàn)硬件實(shí)驗(yàn)流程 了解DE1-SoC硬件系統(tǒng)架構(gòu) 檢視HPS系統(tǒng) 添加并配置LED和Button PIO組件 編譯生成Qsys系統(tǒng) 編輯并編譯Quartus II工程 驗(yàn)證硬件系統(tǒng)設(shè)計(jì)DE1SoC系統(tǒng)框圖定義硬件系統(tǒng)架構(gòu)Golden Hardware Reference Design (GHRD)n 提供DE1-SoC 完整的Quartus II 專案 基本的頂層top.v 文件

9、 Qsys : HPS (pin mux / ddr3 / clocketc.) , AXI-bridge, On-ChipRAM and basic FPGA component完整的 Pin assignment , SDC文檔n 可在 DE1-SoC CD內(nèi)取得GHRD Qsys組件一覽n Golden System Reference Design配置HPS系統(tǒng)(1)配置HPS系統(tǒng)(2)HPS組件設(shè)定通用選項(xiàng)與Bootn Events Event in and outt for event condition Wait for interrupt conditionn GIPOn De

10、bug interfacen Boot from FPGAFPGAHPS InterfacesHSP FPGA AXI BridgeAXI Bridgesn FPGA-to-HPS外設(shè)與內(nèi)存 4GB space Widths 32, 64, 128n HPS-to-FPGA 960 MB space Widths 32, 64, 128n Lightweight HPS-to-FPGA Low performance (32 bits) 可以對(duì)FPGA組件 2 MB space并狀態(tài)n 可以連接Avalon總線FPGAtoSDRAMFPGAtoHPS SDRAM Interfacesn AXI

11、-3 or Avanlon-MMn Select the number of interfacesn Data widths: 32, 64, 128, 256Other Interfaces to the HPSn Resets FPGA can control debug, warm or cold reset signals HPS can send cold and warm reset signals to FPGAn DMA requests Enable up to 8 from the FPGAn Interrupts 64 inputs from FPGA to HPS in

12、terrupt controller HPS peripheral interrupt output to FPGAHPS I/O Muxing OverviewPeripheral Pin Multiplexingn Enable peripheral interface and choose modesn Select I/O setHPS I/O管腳特性n 可使用的外設(shè)的數(shù)目多于HPS I/Osn 多數(shù)外設(shè)需要共享HPS I/OsPin Usage andsHPS Pin Assignmentsn HPS管腳設(shè)定會(huì)自定被Quartus compiler設(shè)定n SDRAM I/O需要執(zhí)行.

13、tcl來(lái)設(shè)定 執(zhí)行hps_sdram_po_pin_assigments.tclI/O StandardHPS Clock Block DiagramHPS Clockn Enable HPS clocks into the FPGAn Drive FPGA clocks into HPS PLLs Peripherals SDRAMSDRAMn 一至的SDRAM GUI Megafunction界面n 支持?jǐn)?shù)種內(nèi)存 DDR3 DDR2 LPDDR2n 設(shè)置clock以及初始設(shè)定設(shè)定SDRAM 的 Timing & SkewSoC EDS ContentsSoC Embedded Develo

14、pment Suite (SoCn Contains everything you need for firmware and application development on the Altera SoC hardware platform Board bring up Bare-mapplication development and debugging Device driver development Linux based application development and debugging Debug systems running symmetrical multipr

15、ocessing Debug software targeting sthat resides in the FfabricEDS ConntsComponentKey FeatureWeb EditionSubscription EditionEclipse IDEARM Development Studio 5(DS5) Altera Edition ToolkitDebugging over Ethernet (Linux)Debugging over USBBlaster II (JTAG)Automatic register viewsHardware crosstriggering

16、CPU/FPGA event correlationHardware/Software Interface ToolsPreloader Support Package GeneratorDevice Tree GeneratorCompiler ToolsLinaro Linux GCC tool chain (armlinux gnueabihf)Mentor CodeBench Lite BaremGCCtool chain(armnoneeabi)SoC Hardware LibrariesHWLibsSoC Programming ExamplesGolden Hardware Re

17、ference Design,Variety of software and Linux examplesARM DS5 Altera EditionSelectPerspectiveOutline ViewFile ViewerProjectTerminalWindowEmbedded Command ShellnCygwin base build environmentnSimilar to Nios Command ShellnembeddedEmbedded_Comannd_Sheel.batHard Ware to Software Handoff FilesGenerated Ha

18、ndoff Filesn Handoff for the preloader generator Contains information chosen during HPS component instantiation Preloader generator uses hand off to generate the preloader binary which used to setup the pin mux, SDRAM, clocks, etc.n System View Description file (CMSIS-SVD) XML file allows registers

19、of soft IP in FPGA to show within the DS-5n .sopcinfo Describes the FPGA system to Alteras device tree generator for uses in the linux envionment生成PreloaderApplication Class Processor Booting FlowBootROMStored in onchip ROMPreloaderStored in flash, runs from SDRAMUBootStored in flash, runs from SDRA

20、MSDRAMRunApplication生成Preloader 流程Handoff FolderHandoff FolderPreloader SourcePreloaderImageFileDescriptionuboot-socfpga/spl/u-boot-splPreloader ELF fileuboot-socfpga/spl/u-boot-spl.binPreloader binary file生成Device TreeLinux Device Tree生成Device Tree流程SOPC Info File.dts文件內(nèi)容生成Device Tree Flow可Boot Linux MicroSD Card內(nèi)容ARM DS5 Altera EdtionARM DS5 AlterEdtionn File editingn Project managementn Debugging Run control (Run, stop , breakpoints) Variables/Watch view HPS Register View FPGA and Soft IP Register Tracing Cross-Triggering Profiling(using CMSIS-SVD fil