最新數(shù)字電路英文版-第七單元-醫(yī)學(xué)課件

1、1ABEL ( 件描述語言的一種件描述語言的一種) Architecture ( 結(jié)構(gòu)體結(jié)構(gòu)體 )Array ( 陣列陣列 ) Buffer ( 緩沖器緩沖器 )Cell ( 單元單元 ) Compiler ( 編輯器編輯器 )Documentation file ( 使用說明文件使用說明文件 ) Fuse ( 熔絲熔絲 )E2CMOS ( 電可擦除的電可擦除的CMOS ) GAL ( 通用陣列邏輯器件通用陣列邏輯器件 )Input file ( 輸入文件輸入文件 ) Input/Output ( I/O ) ( 輸入輸入/輸出輸出 )2JEDEC file ( 標(biāo)準(zhǔn)數(shù)據(jù)格式文件標(biāo)準(zhǔn)數(shù)據(jù)格式文

2、件 ) OLMC (輸出邏輯宏單元輸出邏輯宏單元 )PAL ( 可編程陣列邏輯可編程陣列邏輯 ) PLA ( 可編程邏輯陣列可編程邏輯陣列)PLD ( 可編程邏輯器件可編程邏輯器件 ) Programmer ( 編程器編程器 )PROM ( 可編程只讀存儲器可編程只讀存儲器 ) Software ( 軟件軟件 )Synthesis ( 綜合綜合 ) Tristate output buffer ( 三態(tài)輸出緩沖器三態(tài)輸出緩沖器 )ZIF socked ( 不用力插座不用力插座 ) 3KEY TERMSABEL Advanced Bollean Expression Language. A so

3、ftware compiler language for PLD programming; a type of hardware description language (HDL).Architecture The internal functional arrangement of the elements that give a device its particular operating characteristics.4Array In a PLD, a matrix formed by rows of product-term lines and columns of input

4、 lines with a programmable cell at each junction.Buffer A circuit that prevents loading of an input or output.Cell A fused cross point of a row and columnn in a PLD.5Complier Software that translates from high-level language that uses words or symbols, such as HDL , into low-level machine language (

5、1s and 0s).Documentation file The information from a computer that documents the final design after the input file has been processed.6E2CMOS Electrically earsable CMOS ( EECMOS). The circuit technology used for the reprogrammable cells in GAL.Fuse The programmable element in certain types of PLDs;

6、also called a fusible link.GAL Generic array logic. A PLD with a reprogrammable AND array, a fixed OR array, and programmable output logic macrocells.7Input file The information entered in a computer that describes logic design using a PLD programming language such as HDL.Input/Output (I/O) A termin

7、al of a device that can be used as either an input or as an output.8OLMC Output logic marcocell. The programmable output logic in a GAL.PAL Programmable array logic. A PLD with a programmable AND array and a fixed OR array.PLA Programmable logic array. A PLD with a programmable AND and OR array.9PLD

8、 Programmable logic device.Programmer An instrument that programs PLD using a JEDEC file downloaded from a computer running HDL software.Software Computer programs; programs that instruct a computer what to do in order to carry out a given set of tasks.10Synthesis The software process of converting

9、a circuit description to a standard JEDEC file for PLD programming.Tristate output buffer A logic circuit having three output states: HIGH, LOW, and high impedance (open).11ZIF socket Zero insertion force socket. A type of socket used in most programmers that accepts a PLD package.12Programmable log

10、ic devices (PLDs) are used in many applications to replace SSI and MSI circuits; they save space and reduce the actual number and cost of devices in a given design. 213A PLD consist of a large array of AND gates and OR gates that can be programmed to achieve specified logic functions. Four types of

11、devices that are classified as PLDs are the programmable read-only memory (PROM), the programmable logic array (PLA), the programmable array logic (PAL), and the generic array logic (GAL).314Programmable ArraysThe OR ArrayAABBX1X2X3Fusible link415AABBX1 =A+BX2 =A+BX3 =A+B516The AND ArrayAABBX1X2X361

12、7AABBX1=ABX2=ABX3=AB718Classification of PLDsProgrammable Read-Only MemoryFixedAND arrayProgrammableOR arrayOutput 1Input 1Input 2Input nOutput 2Output m819Programmable Logic Array (PLA)ProgrammableAND arrayProgrammableOR arrayOutput 1Input 1Input 2Input nOutput 2Output m920Programmable Array Logic

13、(PAL)ProgrammableAND arrayFixed OR array andoutput logicOutput 1Input 1Input 2Input nOutput 2Output m1021Generic Logic Array (GAL)ProgrammableAND arrayFixed OR array andProgrammableoutput logicOutput 1Input 1Input 2Input nOutput 2Output m1122The PAL and the GAL are the most common PLDs used for logi

14、c implementation. As you learned in the last section, the PAL in its basic form is a PLD with a one-time programmable AND array and fixed OR array. In this section, you will learn how PALs are used to produce specified combinational logic functions and examine a specific PAL.1223PAL Operation ( SOP

15、)AABBX1324Implementing a Sum-of-Products Expression X = AB +AB +ABAABBX1425Simplified SymbolsAABBXAB4ABABAB15XXXXXX26Programmable Array Logic (PAL)ProgrammableAND arrayFixed OR arrayOutput 1Input 1Input 2Input nOutput 2Input 3Output mOutputlogicOutputlogicOutputlogic1627PAL Output Combination LogicO

16、utputFrom ANDGate arrayTristate control(a) Combination output (active-LOW).1728I/OFrom ANDGate arrayTristate control(b) Combination input/output (active-LOW).1829I/OFrom ANDGate arrayTristate control(c) Programmable polarity outputProgrammable fuse1930Standard PAL NumberingPAL 10L8Programmable array

17、 logicTen inputsEight outputsActive-LOW output2031The GAL in its basic form is a PLD with a reprogrammable AND array, a fixed OR array, and programmable output logic. In this section, basic concepts are introduced and Section 7-4 and 7-5 specific GALs are examined.GAL Operation electrically erasable

18、 CMOS (E2CMOS)2132AABBXE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOSE2CMOS2233AABBOffOnOffOffOffOffOffOffOffOffOffOffOffOffOffOffOffOffOffOnOnOnOnOnABABAB X=AB+AB+AB2334The GAL Block DiagramE2CMOSProgrammabl

19、eAND arrayI/O 1Input 1Input 2Input nI/O 2Input 3I/O mOLMCOLMCOLMC2435Standard GAL NumberingGAL 16V8Generic array logicSixteen inputsEight outputsVariable-output configuration2536The various GALs all have the same type of programmable array. The differ in the size of the array, in the type of OLMCs ,

20、 and in operating parameters such as speed and power dissipation. In this section, a popular generic array logic device, the GAL22V10, is discussed.2637Logic Diagram1-of-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1S0S1I/O2738The Output Logic Macrocells (OLMCs)As stated in the discussion of GALs , an

21、 OLMC contains programmable logic circuits that can be either for a combinational output or input or for a registered output.28391-of-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1S0S1I/O(a) Active-LOW output S1=1, S0=029401-of-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1S0S1I/O(b) Active-HIGH output

22、S1=1, S0=13041InputOutputTristate controlHIGHLOWHIGHActive stateLOW(a)HIGHLOWHIGHActive stateHigh-impedance state(b)3142Output or Input Selection1-of-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1S0S1HIGHOutput(a) Output32431-of-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1S0S1LOWInput(b) Input33441-of

23、-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1=1S0=1S1=1HIGHX=ABCD+ ABCD+ ABCD+ ABCD+ ABCD+XABCDABCDABCDABCDABCDABCDABCDActive HIGH45Related Problem Write the SOP expression for the output if S0=0, S1= 1( Active LOW )461-of-4multiplexer1-of-2multiplexerFlip-FlopOLMCS1=1S0=0S1=1HIGHX=ABCD+ ABCD+ ABCD+

24、 ABCD+ ABCD+ABCDXABCDABCDABCDABCDABCDABCD( Active LOW )47Example 7-6 Show how the following 6-variable SOP function is implemented with the AL22V10X=ABCDEF+ ABCDEF+ ABCDEF+ ABCDEF+ ABCDEF+ABCDEF+ ABCDEF480 3 4 7B BC CD DE EF F8 11 12 15 16 19 20 2340 43A1OHIGHS0=1S1=1OLMC49As you have learned, PLAs

25、are programmed by leaving specified fusible links intact and blowing open all others. GALs are programmed in a similar way except the E2CMOS cells are turned on or off. The logic functions to be implemented determines which cells are affected. 3450In order to program a PLA or GAL, the following item

26、s are required: a computer, programming software, and a PLD programmer.Computer: Any computer that meets the software and programmer specifications can be used.3551Software: The software packages for PLD programming are called logic compliers. The Programmer: The programmer has a software driver pro

27、gram that reads JEDEC file generated by the logic complier and converts it to instructions for applying required voltages to specified PLD pins to alter the specified cells in the array as directed by the fuse map.3652STARTDesign thelogic circuitEnter designinto computerSyntax orOther errors?Complie

28、rfile andDesignsimulationDesignflaw?processes inputminimizes logicDebugEditYesNoNoYes3753Complier createsJEDEC file (fuse map)Download toprogrammerProgrammer “burns”fuse map into PLDarrayComplier generates documentation file3854The Programming ProcessEntering the Design: The logic design is entered

29、into the computer by creating an input or source file. Running the Software: The software complier processes and translates the input file and minimizes the logic.3955Programming the Device: When the design is finalized, the compiler creates a fuse map (JEDEC file) and downloads it to the programmer

30、. 4056As mentioned earlier, there are several software packages for implementing logic designs in PLDs. ABEL is commonly used hardware description languages (HDLs).4157Introduction to ABEL: ABEL, which is the acronym for Advanced Boolean Expression Language, allows logic designs to be implemented in

31、 programmable in programmable logic devices.4258Logic Design Entry : ABEL provides three different formats for describing and entering a logic design from the from the computer keyboard: equations, truth tables, and state diagrams.4359Design Simulation : Once a logic circuit design has been entered,

32、 its operation can be simulated using test vectors to make sure there are no design errors.4460Logic Synthesis : The software process of converting a circuit description in the form of equations, truth tables, or state diagrams to a standard JEDEC file format required to actually implement the desig

33、n in a PLD is called logic synthesis .4561Boolean Operations:Logic Operation ABEL Symbol NOT ! AND & OR # XOR $4662Standard Boolean ABEL A !A AB A & B A + B A # B +A B A $ B4763EXAMPLE 7-7 Write each of the following logic expressions in ABEL:(a)X= ABC +ABC +AB + BC(b)Y= ( A + B + C + D )( A

34、 + B + C )Solution (a)X = A&!B&C#!A!B!C#A&B#!B&C(b)Y =(!A#B#!C#D)&(A#B#C)RP: W= X+Y,Where X=ABC, Y=A+B+C4864EXAMPLE 7-8MultiplexerA3A2A1A0B3B2B1B0Y3Y2Y1Y0C3C2C1C0S1S04965Select Input Data Output S1 S0 Y3 Y2 Y1 Y0 0 1 A3 A2 A1 A0 1 0 B3 B2 B1 B0 1 1 C3 C2 C1 C0 5066Solution: Y3=A3

35、S1S0+B3S1S0+C3S1S0 Y2=A2S1S0+B2S1S0+C2S1S0 Y1=A1S1S0+B1S1S0+C1S1S0 Y0=A0S1S0+B0S1S0+C0S1S0 Y3= A3&!S1&S0#B3S1&!S0#C3&S1&S0Y2= A2&!S1&S0#B2S1&!S0#C2&S1&S0Y1= A1&!S1&S0#B1S1&!S0#C1&S1&S0Y0= A0&!S1&S0#B0S1&!S0#C0&S1&S0The equations in ABEL format are51.67 Sets with the following declaration: A = A3, A2, A1, A0 ; B = B3, B2, B1, B0 ; C = C3, C2, C1, C0 ; Y =