下面程序是位十進(jìn)制計(jì)數(shù)器的VHDL描述

1、7W的是1位頊制成明勺VHDL才鰥，諭卜誑整。2.下郁4個(gè)多路遴!器的VHDL描述，*整。LIBRARYIEEE;USEIEEE.STD.LOGC_1164.ALL;USEIEEE.STDJ_OGC_UNSIGND.ALL;ENTTYCNT0ISPORTCLK:INSTD_OGC;LIBRARYIEEE;USEIEEE.STD_LOGC_1164.ALL;ENTTYbmixISPORTsel:INSTD_LOGC;A,B:INSTD_OGC_VECTOR7DOWNO0);Y:OUTSTD_OGC_VECTOR7DOWNO0);ENDbmix;ARCHECTIREbhvOFbmixISBEGNy

2、10THENQ10);-置零ELSEQ1=Q1+1;-力口1ENDIF;ENDIF;ENDPROCES;Q=Q1;ENDbhv;三、VHDL錯(cuò)仔細(xì)）回答問(wèn)題LIBRARYIEEE;-1USEIEEE.STD_LOGIC_1164.ALL;-2ENTITYLED7SE3IS-3PORT(A:INSTD_OGC_VECOR3DOWNTO);-4CLK:INSTD_LO(JC;-5LED75:OUTSTD_LDGC_ECOR(6DOWTO0);-6ENDLEDSEG;-7ARCHITCTUREoneOFLEE7SE3IS-8SIGNALTMPSTD_OGC;-9BEGIN-10SYNCPRE%(CL

3、K,A)-11BEGN-12IFCLKEVENTANDCLK=1THEN-13TMPLEDBLED7SLED7SLED7SLED7SLED7LEDBLEDBLED7SLED7SED7S=0000000;四、獻(xiàn)蝦列VHDL序，畫出康I圖（RTILIBRARYIEEE;USEIEEE.STD_OGIC_1164.ALL;ENTITYHADSPORTa:b:INSTLOGIC;INSTLOGIC;OUTSTD_LOGICOUTSTD_LOGIQ;c:d:ENDENTTYHAD;ARCHTECTIREfh1BEGINc=NOT(aNANDb);d0);ELSIFCLK=1ANDCLKEVENTTHEN

4、IFLOAD=1THENQ1:=DATAELSEIFEN=1THENQ1:=Q1+1;ENDIF;ENDIF;ENDIF;Q=Q1;ENDPRGCES;ENDONE;LIBRARYIEEE;USEIEEE.STD_LOGC_1164.ALL;ENTITYTRI_STATEISPORTE,A:INSTDLOGC;Y:INOUTSTD_LOC;B:OUTSTD_LOGIC;ENDTRI_STATE;ARCHITECTUEBEHVOFTRI_STATEISBEGINPROESS(E,A,Y)BEGNIFE=0THENB=Y;Y=Z;ELSEB=Z;Y=A;ENDIF;ENDPRODES;ENDBEH

5、AV;下個(gè)A/D采集系統(tǒng)的音階，要其中的FPG采集控制蟆，由三個(gè)勾成：控制器(ContrOl、(addrnt、內(nèi)X口RAM(adram?？刂破?contrOl個(gè)完成AD574翊空制，和adramB勺寫乍。Adiam個(gè)LPM_RAM_DP單元在wran為T時(shí)允許必?cái)?shù)據(jù)。劇刑回答問(wèn)題FPG架集控制7W列出了AD57雄制方郎口控制H拆圖CECSRCK12_8A0工作狀態(tài)0XXXX禁止X1XXX禁止100X0同12位車取100X1啟動(dòng)8幽專換1011X12位并彳榆出有效10100高8位并OIW有效10101低4位嘩隨4個(gè)0有效工作時(shí)序:中W瞰置AD574值表（X要醇12位車構(gòu)莫式,K12_8A0在bM

6、。1一_,.一AD5741.2.3.求AD574XK12_&?T,A0為0以一/試畫出contro的腿利的狀態(tài)3類似書也8-4迫對(duì)地田worn行VHDL才鰥口：clkinc討數(shù)脈沖輸出端口:rdaddrcntclr計(jì)麴|清RAM園地址，位寬10位libraryieee;useieee.std_logic_1164all;useieee.std_logic_unsigned.all;entityaddr_cntisport(clkinc,cntclr:instd_logic;wraddr:outstd_logic_vector(9downto0);endaddr_cnt;architecture

7、oneofaddr_cntissignaltmp:std_logic_vector(9downto0);beginprocess(clkinc,cntclr)beginifclkinceventandclkinc=1thenifcntclr=1thentmp0);elsetmp=tmp+1;endif;endif;endprocess;wraddr=tmp;endone;4.根據(jù)狀態(tài)圖，咨寸contol進(jìn)行VHDL描述libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycontrolisport

8、(addata:instd_logic_vector(11downto0);statcs,us,ce,clk:ina0,rc,kstd_logic;12_8,clkinc:outstd_.logic;rddata:outstd_logic_vector(11downto0);endcontrol;architecturetypecosignalsignalsignal!behavofcontrolisn_stis(s0,s1,s2,s3,cst,nst:con_st;lock:std_logic;reg12:std_logic_vectors4);(11downto0);begina0=0;k

9、12_8=1;ce=1;cs=0;REGPprocess(clk)beginifclkeventandclk=1thencstrc=1;lock=0;nstrc=0;lock=0;nstifstatus=1thennst=s3;endif;rc=1;lockrc=1;lock=1;nstrc=1;lock=0;nstnst=s0;endcase;endprocess;LOCR:process(lock)beginiflock=1andlockeventthenreg12=addata;endif;endprocess;rddata=reg12;clkinc=lock;-(為NOTLOCKJOB

10、MWW)endbehav;5,已知adranm勺端口指述如下ENTTYadramISPORT(data:INSTD_LOGC_VETO?(11DOWNT0);-寫/addata,status=status,clk=clk,cs=cs,ce=ce,a0=a0,rc=rc,k12_8=k12_8,clkinc=clkinc,rddata=rds);u2:addr_cntportmap(clkinc=clkinc,cntclr=cntclr,wraddr=wraddr);u3:adramportmap(data=rds,wraddress=wraddr,rdaddress=rdaddr,wren=1,q=rddata);endone;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYthreeISPORT(clk,d:INSTD