EDA課程設計——多功能數(shù)字鐘

1、哈爾濱工業(yè)大學(威海)電子學課程設計報告帶有整點報時的數(shù)字鐘設計與制作姓名:蔣棟棟班級:0802503學號:080250331指導教師:井巖目錄一、課程設計的性質(zhì)、目的和任務3二、課程設計基本要求3三、設計課題要求3四、課程設計所需要儀器4五、設計步驟4 1、整體設計框圖4 2、各個模塊的設計與仿真4 2.1分頻模塊4 2.2計數(shù)器模塊6 2.3控制模塊10 2.4數(shù)碼管分配13 2.5顯示模塊14 2.6報時模塊16六、調(diào)試中遇到的問題及解決的方法18七、心得體會18一、課程設計的性質(zhì)、目的和任務創(chuàng)新精神和實踐能力二者之中，實踐能力是基礎和根本。這是由于創(chuàng)新基于實踐、源于實踐，實踐出真知，實

2、踐檢驗真理。實踐活動是創(chuàng)新的源泉，也是人才成長的必由之路。通過課程設計的鍛煉，要求學生掌握電路的一般設計方法，具備初步的獨立設計能力，提高綜合運用所學的理論知識獨立分析和解決問題的能力，培養(yǎng)學生的創(chuàng)新精神。二、課程設計基本要求掌握現(xiàn)代大規(guī)模集成數(shù)字邏輯電路的應用設計方法，進一步掌握電子儀器的正確使用方法，以及掌握利用計算機進行電子設計自動化(EDA)的基本方法。三、設計課題要求（1）構(gòu)造一個24小時制的數(shù)字鐘。要求能顯示時、分、秒。（2）要求時、分、秒能各自獨立的進行調(diào)整。（3）能利用喇叭作整點報時。從59分50秒時開始報時，每隔一秒報時一秒，到達00分00秒時，整點報時。整點報時聲的頻率應與

3、其它的報時聲頻有明顯區(qū)別。#設計提示（僅供參考）：（1）對頻率輸入的考慮數(shù)字鐘內(nèi)所需的時鐘頻率有：基準時鐘應為周期一秒的標準信號。報時頻率可選用1KHz和2KHz左右(兩種頻率相差八度音，即頻率相差一倍)。另外，為防止按鍵反跳、抖動，微動開關輸入應采用寄存器輸入形式，其時鐘應為幾十赫茲。（2）計時部分計數(shù)器設計的考慮分、秒計數(shù)器均為模60計數(shù)器。小時計數(shù)為模24計數(shù)器，同理可建一個24進制計數(shù)器的模塊。（3）校時設計的考慮數(shù)字鐘校準有3個控制鍵：時校準、分校準和秒校準。微動開關不工作，計數(shù)器正常工作。按下微動開關后，計數(shù)器以8Hz頻率連續(xù)計數(shù)(若只按一下，則計數(shù)器增加一位)，可調(diào)用元件庫中的邏

4、輯門建一個控制按鍵的模塊，即建立開關去抖動電路(見書70頁)。（4）報時設計的考慮可以將高頻時鐘分頻得到約2KHz和1KHz的音頻，作為數(shù)字鐘的報時頻率。當電子鐘顯示XX：59：50時，數(shù)字鐘開始報時“DO"，持續(xù)一秒，而且每隔一秒報一下，直至顯示XX：00：00時報“DI"，持續(xù)一秒后停止。最后輸出至喇叭。應調(diào)用元件庫中的邏輯門建一個控制報時的模塊。（5）建一個七段譯碼的模塊因在系統(tǒng)可編程器件實驗箱上的數(shù)碼管沒有經(jīng)過譯碼，故要用AHDL語言寫一個七段譯碼的模塊，且應考慮數(shù)碼管為共陽極。數(shù)碼管上的點(D2、D4、D6)應置Vcc。四、課程設計所需要儀器1、計算機一臺2、qu

5、artus軟件3、FPGA開發(fā)板五、設計步驟1、模塊介紹（1） 分頻模塊：產(chǎn)生1Hz、1KHz、2KHz頻率（2） 計數(shù)器模塊：生成60進制、24進制計數(shù)器（3） 控制模塊：按鍵控制、按鍵消抖（4） 顯示模塊：7段數(shù)碼管顯示器，分別顯示小時、分鐘、秒（5） 報時模塊：進行整點報時2、各個模塊的設計與仿真2.1分頻模塊CLK晶振頻率50MHZ，分成2KHZ,1KHZ,1HZ的信號?；鶞?HZ信號作為時鐘計時的秒計數(shù)時鐘信號；分頻的1KHZ,2KHZ信號用于報時電路的不同聲訊。程序代碼：library ieee;use ieee.std_logic_1164.all;entity fre ispo

6、rt(clk ,sel: in std_logic;clk1hz,clk1khz,clk2khz:out std_logic);end fre;architecture beh of fre issignal data1khz,data2khz,data1hz : std_logic := '0'begin clk1hz <= data1hz; clk1khz <= data1khz; clk2khz <= data2khz; clk1khz_pro : process(clk) -產(chǎn)生1khz信號 variable cnt : integer range 0

7、 to 24999; begin if clk'event and clk='1' then if cnt = 24999 then cnt := 0 ; data1khz <= not data1khz; else cnt := cnt + 1; end if; end if; end process clk1khz_pro; clk2khz_pro : process(clk) -產(chǎn)生2khz信號 variable cnt : integer range 0 to 12499; begin if clk'event and clk='1'

8、; then if cnt = 12499 then cnt := 0 ; data2khz <= not data2khz; else cnt := cnt + 1; end if; end if; end process clk2khz_pro; clk1hz_pro : process(data1khz) -產(chǎn)生1hz 信號 variable cnt : integer range 0 to 499; begin if data1khz'event and data1khz='1' then if sel='0' then cnt:=0; e

9、lse if cnt = 499 then cnt := 0 ;data1hz <= not data1hz ; else cnt := cnt + 1; end if; end if; end if; end process clk1hz_pro; end beh;輸入模塊電路圖：2.2計數(shù)器模塊由秒計數(shù)器，分計數(shù)器，時計數(shù)器組成了最基本的數(shù)字鐘計時電路，兩個六十進制計數(shù)器與二十四進制計數(shù)器組合構(gòu)成。程序代碼：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use IEEE.STD_LOG

10、IC_ARITH.ALL;entity shuzizhong isport(clk_change : in std_logic;s_en,m_en,h_en:in std_logic;sel:in std_logic;secout,minout,hourout :out std_logic;sl,sh,ml,mh,hl,hh:out std_logic_vector(3 downto 0);a:out std_logic_vector(15downto 0);end shuzizhong;architecture behav of shuzizhong issignal low_rega,hi

11、gh_rega,low_regb,high_regb,low_regc,high_regc :std_logic_vector(3 downto 0):="0000"signal sout,mout,hout :std_logic :='0'begin-秒的60進制進制 counter_sec_l : process(clk_change,s_en) begin sl<=low_rega;sh<=high_rega;ml<=low_regb;mh<=high_regb;hl<=low_regc;hh<=high_regc;

12、 if clk_change'event and clk_change='1' then if s_en='1' then if low_rega="1001" then low_rega <= "0000" else low_rega <= low_rega+'1' end if; end if; end if; end process counter_sec_l; counter_sec_h : process(clk_change,s_en,low_rega) begin if c

13、lk_change'event and clk_change='1' then if s_en='1' then if low_rega="1001" then if high_rega ="0101"then high_rega <= "0000" else high_rega <= high_rega+'1' end if; end if; end if; end if; end process counter_sec_h; sout <= '1&#

14、39; when low_rega="1001" and high_rega="0101" else '0' -分鐘的60進制設置 counter_min_l : process(clk_change,m_en) begin if clk_change'event and clk_change='1' then if m_en='1' then if sout='1'or sel='0' then if low_regb="1001" then l

15、ow_regb <= "0000" else low_regb <= low_regb+'1' end if; end if; end if; end if; end process counter_min_l; counter_min_h : process(clk_change,m_en,low_regb) begin if clk_change'event and clk_change='1' then if sout='1'or sel='0' then if m_en='1

16、' then if low_regb="1001" then if high_regb ="0101"then high_regb <= "0000" else high_regb <= high_regb+'1' end if; end if; end if; end if; end if; end process counter_min_h; mout <= '1' when low_regb="1001" and high_regb="010

17、1"and sout='1' else '0' -小時的24進制設置counter_hour_l : process(clk_change,h_en) begin if clk_change'event and clk_change='1' then if h_en='1' then if mout='1'or sel='0' then if low_regc="1001"or hout='1' then low_regc <= "

18、;0000" else low_regc <= low_regc+'1' end if; end if; end if; end if; end process counter_hour_l; counter_hour_h : process(clk_change,h_en,hout) begin if clk_change'event and clk_change='1' then if mout='1'or sel='0' then if h_en='1' then if hout=&#

19、39;1' then high_regc<="0000" else if low_regc="1001" then high_regc <= high_regc+'1' end if; end if; end if; end if; end if; end process counter_hour_h; hout <= '1' when low_regc="0011" and high_regc="0010" else '0' secout&

20、lt;=sout;minout<=mout;hourout<=hout; a<=high_regb&low_regb&high_rega&low_rega ; end behav;輸入模塊電路圖：2.3控制模塊分五個狀態(tài)0狀態(tài)正常計時，按下按鍵進入下一狀態(tài)開始調(diào)時模式1，按下按鍵進入調(diào)秒模式2，按下按鍵進入調(diào)分模式3，按下按鍵進入調(diào)小時模式4.按下按鍵恢復正常計時模式。程序代碼：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity key_pres

21、s isport( set ,mode: in std_logic; clk1khz,clk1hz: in std_logic; secout,minout: in std_logic; clk_change,clk2hz_en:out std_logic ; sel,s_ce,m_ce,h_ce:out std_logic; s_en,m_en,h_en:out std_logic ); end key_press; architecture beh of key_press is signal key1,key2:std_logic; signal sce_reg, mce_reg ,hc

22、e_reg:std_logic ; signal ssl,ssen,mmen,hhen:std_logic; signal con : integer range 0 to 4 :=0; -按鍵按下（延時） begin key_press2 : process(set,clk1khz) variable cnt :integer range 0 to 999; begin if set='0' then if clk1khz'event and clk1khz='1'then if cnt=50 and set='0' then cnt

23、:=cnt+1; key2 <= '1' else cnt:=cnt+1;key2 <= '0' end if; end if; else cnt:=0; key2<='0' end if; end process key_press2; key_press1 : process(mode,clk1khz) variable cnt :integer range 0 to 999; begin if mode='0' then if clk1khz'event and clk1khz='1'

24、;then if cnt=50 and mode='0' then cnt :=cnt+1; key1 <= '1' else cnt:=cnt+1;key1 <= '0' end if; end if; else cnt:=0; key1<='0' end if; end process key_press1; count : process(key1,key2) begin if key1'event and key1='1' then if con=4 then con<=0;

25、 else con<=con+1; end if; end if; end process count; con_pro : process(con) begin case con is when 0 => ssl<='1' sce_reg <= '0'ssen <='1' mce_reg <= '0'mmen <='1' hce_reg <= '0'hhen <='1' clk2hz_en <='0' wh

26、en 1 => ssl<='0' sce_reg <= '0'ssen <='1' mce_reg <= '0'mmen <='1' hce_reg <= '0'hhen <='1' clk2hz_en <='1' when 2 => ssl<='0' sce_reg <= '1'ssen <='1' mce_reg <= '0&

27、#39;mmen <='0' hce_reg <= '0'hhen <='0' clk2hz_en <='1' when 3 => ssl<='0' sce_reg <= '0'ssen <='0' mce_reg <= '1'mmen <='1' hce_reg <= '0'hhen <='0' clk2hz_en <='1'

28、 when 4 => ssl<='0' sce_reg <= '0'ssen <='0' mce_reg <= '0'mmen <='0' hce_reg <= '1'hhen <='1' clk2hz_en <='1' when others => ssl<='0' sce_reg <= '0'ssen <='1' mce_reg <=

29、 '0'mmen <='1' hce_reg <= '0'hhen <='1' clk2hz_en <='0' end case; end process con_pro; sel_pro : process(ssl) begin case ssl is when '0'=> s_ce<=sce_reg; m_ce<=mce_reg; h_ce<=hce_reg; clk_change<=key2; when '1'=> s

30、_ce<=ssen; m_ce<=mmen; h_ce<=hhen; clk_change<=clk1hz; when others=> s_ce<=ssen; m_ce<=secout; h_ce<=minout; clk_change<=clk1hz; end case; end process sel_pro; sel<=ssl;s_en<=ssen;m_en<=mmen;h_en<=hhen; end beh;輸入模塊電路圖：2.4數(shù)碼管分配程序代碼：library ieee;use ieee.std_log

31、ic_1164.all;entity display isport(datain : in std_logic_vector(3 downto 0);dataout : out std_logic_vector(7 downto 0);end display;architecture duan of display isbegin process(datain) begin case datain is when "0000" => dataout <="11000000" -dp,g,f,e,d,c,b,a when "0001&

32、quot; => dataout <="11111001" when "0010" => dataout <="10100100" when "0011" => dataout <="10110000" when "0100" => dataout <="10011001" when "0101" => dataout <="10010010" when &

33、quot;0110" => dataout <="10000010" when "0111" => dataout <="11111000" when "1000" => dataout <="10000000" when "1001" => dataout <="10010000" when "1010" => dataout <="10111111&qu

34、ot; when "1011" => dataout <="10000011" when "1100" => dataout <="10100111" when "1101" => dataout <="10100001" when "1110" => dataout <="10000110" when "1111" => dataout <="1

35、0001110" when others => null; end case; end process; end ;輸入模塊電路圖：2.5顯示模塊使用七段數(shù)碼管顯示小時、分鐘與秒程序代碼：library ieee;use ieee.std_logic_1164.all;entity scan isport(clk1khz : in std_logic;sl,sh,ml,mh,hl,hh : in std_logic_vector(3 downto 0);clk2hz_en : in std_logic;s_ce,m_ce,h_ce : in std_logic;en_out :

36、 out std_logic_vector(7 downto 0);dataout : out std_logic_vector(3 downto 0);end scan;architecture beh of scan issignal cnt : integer range 0 to 7;signal en : std_logic_vector(7 downto 0);signal clk2hz : std_logic; signal h_ce_reg,m_ce_reg,s_ce_reg : std_logic;begin h_ce_reg <= not h_ce; m_ce_reg

37、 <= not m_ce; s_ce_reg <= not s_ce; cnt_pro : process(clk1khz) begin if clk1khz'event and clk1khz='1' then if cnt = 7 then cnt <= 0; else cnt <= cnt + 1; end if; end if; end process cnt_pro; clk2hz_pro :process(clk1khz) variable c : integer range 0 to 499 := 0; begin if clk1k

38、hz'event and clk1khz='1' then if clk2hz_en ='1' then if c =499 then c := 0 ; clk2hz <= not clk2hz; else c := c + 1; end if; else clk2hz <= '0' end if; end if; end process clk2hz_pro; scan_pro : process(cnt,sl,sh,ml,mh,hl,hh) begin case cnt is when 0 => dataout &l

39、t;= sl;en <= "11111110" when 1 => dataout <= sh;en <= "11111101" when 2 => dataout <= ml;en <= "11110111" when 3 => dataout <= mh;en <= "11101111" when 4 => dataout <= hl;en <= "10111111" when 5 => dataout &l

40、t;= hh;en <= "01111111" when 6 => dataout <= "1010"en <= "11111011" when 7 => dataout <= "1010"en <= "11011111" when others => null; end case; end process scan_pro; en_out <= en or (clk2hz & clk2hz) or (h_ce_reg & h_ce_reg) & clk2hz & (clk2hz & clk2hz) or (m_ce_reg & m_ce_reg) & clk2hz & (clk2hz & clk2hz) or (s_ce_reg & s_ce_reg); end beh;輸