數(shù)字集成電路英文課件：Chapter 1 Deep Submicron Digital IC Design

1、Chapter 1: Deep Submicron Digital IC Design Digital Integrated CircuitsFaculty of Materials and Energy, GDUT2OutlineKids Today! Engineer Tomorrow?IntroductionVLSI DesignThe Challenges AheadDigital Integrated CircuitsFaculty of Materials and Energy, GDUT31.0 Kids Today! Engineer Tomorrow?-1 ISSCC 200

2、9US Engineering DegreesDigital Integrated CircuitsFaculty of Materials and Energy, GDUT41.0 Kids Today! Engineer Tomorrow?-2 ISSCC 2009Do You Like to be an Engineer?Digital Integrated CircuitsFaculty of Materials and Energy, GDUT51.0 Kids Today! Engineer Tomorrow?-3 ISSCC 2009Percent. of Women Study

3、ing EngineerDigital Integrated CircuitsFaculty of Materials and Energy, GDUT61.0 Kids Today! Engineer Tomorrow?-4 ISSCC 2009Public Perception of EngineeringDigital Integrated CircuitsFaculty of Materials and Energy, GDUT71.0 Kids Today! Engineer Tomorrow?-5 ISSCC 2009New Engineer Messages:Live your

4、life, love what you do:Engineering will challenge you to turns dreams into realities while working with inspiring people.Creativity has its rewards:Engineering are respected, recognized and financially rewarded for their innovative thinking and creativity.Make a world of difference:Engineering are g

5、oing where there is the greatest need and making a lasting contribution.Create possibilities:Engineering opens all kinds of doors, from humanitarian work to international business.Digital Integrated CircuitsFaculty of Materials and Energy, GDUT81.1 Introduction-1 The First ComputerThe Babbage Differ

6、ence Engine 2500 parts (1832), at The London Science Museums difference engineFully operational difference engine No.2 at the Computer History Museum in Mountain View, CADigital Integrated CircuitsFaculty of Materials and Energy, GDUT91.1 Introduction-2 Mechanical Alternative to Electronics1989, Dor

7、on Swade “The calculating section of Difference Engine No. 2, has 4,000 moving parts (excluding the printing mechanism) and weighs 2.6 tons. It is 7 feet high, 11 feet long and 18 inches in depth”Digital Integrated CircuitsFaculty of Materials and Energy, GDUT101.1 Introduction-3 Why Integrated Circ

8、uitBreak this question into two questionsWhy electronicsWhy use ICs to build electronicsWhy use electronicsElectrons are easy to move / controlEasier to move/control electrons than real stuffMove information, not things (phone, fax, WWW, etc.)Takes much less energy and $Digital Integrated CircuitsFa

9、culty of Materials and Energy, GDUT111.1 Introduction-4 ENIACElectronic Numerical Integrator And ComputerFirst electronic computer 18000 vacuum tubes, 680 ft3 (63m2), 150kWDigital Integrated CircuitsFaculty of Materials and Energy, GDUT121.1 Introduction-5 From Tubes1946, ENIAC filled an entire room

10、!17,468 vacuum tubes,70,000 resistors,72,000 crystal diodes,10,000 capacitors,6,000 manual switches,5 million hand-soldered joints and many blinking lights!could add 5,000 numbers ina single secondDigital Integrated CircuitsFaculty of Materials and Energy, GDUT131.1 Introduction-6 To TransistorsDigi

11、tal Integrated CircuitsFaculty of Materials and Energy, GDUT141.1 Introduction-7 TX-0 (MIT) and the Transistor 11953, TX-0, Massachusetts Institute of Technology (MIT), Lincoln Labs.Circuit module from the TX-2Digital Integrated CircuitsFaculty of Materials and Energy, GDUT151.1 Introduction-8What i

12、s IC (Integrated Circuit) ?Definition：An IC, sometimes called a chip, is a piece of a semiconductor wafer (called a die) with package, on which many tiny resistors, capacitors, and transistors are fabricated.Number of process steps is independent of circuit complexitySuitable for mass production12 i

13、nch waferDigital Integrated CircuitsFaculty of Materials and Energy, GDUT161.1 Introduction-9: Integrated CircuitsA device with multiple electrical components and their interconnects manufactured on a single substrateClassificationAnalogDigitalMixed SignalDigital Integrated CircuitsFaculty of Materi

14、als and Energy, GDUT171.1 Introduction-10: First IC1952, the idea of the IC was conceived by W.A. Dummer, a radar scientist working for the Royal Radar Establishment of the British Ministry of Defense. But he unsuccessfully attempted to build such a circuit in 1956.1958, Jack Kilby, (2000 Nobile pri

15、ze), Texas Instruments, Kilbys chip was made of germanium& 1959, Robert Noyce, Fairchild Semiconductor, Noyces chip was made of siliconDigital Integrated CircuitsFaculty of Materials and Energy, GDUT181.1 Introduction-11: First Commercial IC1961, the First planar IC, Fairchild1967, the First IC made

16、 with computer-aided design, FairchildDigital Integrated CircuitsFaculty of Materials and Energy, GDUT191.1 Introduction-12: First Microprocessor19714-bit CPUIntel 40442300 MOS Trans.,1 MHz clock rateUS$ 400 on eBay on 2004Digital Integrated CircuitsFaculty of Materials and Energy, GDUT201.1 Introdu

17、ction-13: Intel 45nm Nehalem CPU20074-core CPU,731 millions MOS Trans.,3.6G Hz clock,US$300-1000Digital Integrated CircuitsFaculty of Materials and Energy, GDUT211.1 Introduction-14: Intel 32nm Westmere CPU2010,6-core CPU,1170 millionsMOS Trans.,3.33GHz clock,US$999Digital Integrated CircuitsFaculty

18、 of Materials and Energy, GDUT221.1 Introduction-15: Electronics & ICBuilding electronics:Started with tubes, then miniature tubesTransistors, then miniature transistorsComponents were getting cheaper, but:There is a minimum cost of a component (storage, handling )Total system cost was proportional

19、to complexity Integrated circuits changed that:Printed a circuit, like you print a pictureCreate components in parallelCost no longer depended on # of devicesWhat happens as resolution goes up?Digital Integrated CircuitsFaculty of Materials and Energy, GDUT231.1 Introduction-16: Moores LawIntels co-

20、founder Gordon Moore (Retired chairman and CEO of Intel Corporation, Net worth: $3.7 billion, 2008) notices in 1964# of transistors per chip doubled every 12 monthsSlow down in the 1980s to every 18 monthsDigital Integrated CircuitsFaculty of Materials and Energy, GDUT241.1 Introduction-17: Other Pr

21、oduct with Same TrendDSC pixelsPC hard disk capacityRAM Storage capacityNetwork capacityPower consumptionComputing performance per unit costDensity at minimum cost per transistorDigital Integrated CircuitsFaculty of Materials and Energy, GDUT251.1 Introduction-18: CPU Transistor # vs. Feature SizeTr

22、ansistor dimensions scale to improve performance, reduce power and reduce cost per transistorDigital Integrated CircuitsFaculty of Materials and Energy, GDUT261.1 Introduction-19: PC platform ComparisonModern microprocessors integrate many of the separate system components from past platformsDigital

23、 Integrated CircuitsFaculty of Materials and Energy, GDUT271.1 Introduction-20: Intel 386TM vs. NehalemTransistor Count:280 thousand731 millionFrequency:16MHz3.6GHz# Cores: 1 4Cache Size: None 8MBI/O Peak Bandwidth:64MB/sec50GB/secAdaptive Circuits: NoneSleep ModeTurbo ModePower GatingAdaptive Frequ

24、ency ClockingDigital Integrated CircuitsFaculty of Materials and Energy, GDUT281.1 Introduction-21: System Integration TrendSystem integration needed for performance, power, form factor Challenge is to integrate wider range of heterogeneous elementsDigital Integrated CircuitsFaculty of Materials and

25、 Energy, GDUT291.1 Introduction-22: The IC (1961) vs. IBM IC(1999)Digital Integrated CircuitsFaculty of Materials and Energy, GDUT301.1 Introduction-23: 1 wafer -1964 vs 12 wafer-2003Digital Integrated CircuitsFaculty of Materials and Energy, GDUT311.1 Introduction-24: Technology ScalingYearDimensio

26、ns scale down by 30%Doubles transistor densityOxide thickness scales downFaster transistor, high performanceVdd & Vt scalingLower active powerDigital Integrated CircuitsFaculty of Materials and Energy, GDUT321.1 Introduction-25: Technology ScalingTechnology shrinks by 0.7 per generationWith every ge

27、neration can integrate 2x more functions on a chip; chip cost does not increase significantlyCost of a function decreases by 2xBut How to design chips with more and more functions?Design engineering population does not double every two yearsHence, a need for more efficient design methodsExploit diff

28、erent levels of abstractionDigital Integrated CircuitsFaculty of Materials and Energy, GDUT331.1 Introduction-26: Energy per Logic OperationEnergy per logic operation scaling will slow downDigital Integrated CircuitsFaculty of Materials and Energy, GDUT341.1 Introduction-27: Moores Law in Microproce

29、ssorsTransistors on lead microprocessors double every 2 yearsDigital Integrated CircuitsFaculty of Materials and Energy, GDUT351.1 Introduction-28: Evolution in DRAM Chip CapacityDigital Integrated CircuitsFaculty of Materials and Energy, GDUT361.1 Introduction-29: Die Size GrowthDie size grows by 1

30、4% to satisfy Moores LawDigital Integrated CircuitsFaculty of Materials and Energy, GDUT371.1 Introduction-30: Clock FrequencyLead microprocessors frequency doubles every 2 yearsDigital Integrated CircuitsFaculty of Materials and Energy, GDUT381.1 Introduction-31: Power DissipationLead Microprocesso

31、rs power continues to increaseDigital Integrated CircuitsFaculty of Materials and Energy, GDUT391.1 Introduction-32: Power DensityPower density too high to keep junctions at low temperatureDigital Integrated CircuitsFaculty of Materials and Energy, GDUT401.1 Introduction-33: # of Transistors per Die

32、Source: ISSCC 2003 G. Moore “No exponential is forever, but forever can be delayed”Digital Integrated CircuitsFaculty of Materials and Energy, GDUT411.1 Introduction-34: Design Productivity TrendsComplexity outpaces design productivityDigital Integrated CircuitsFaculty of Materials and Energy, GDUT4

33、21.1 Introduction-35: Exponential CostsDigital Integrated CircuitsFaculty of Materials and Energy, GDUT431.1 Introduction-36: Average Transistor Price by YearDigital Integrated CircuitsFaculty of Materials and Energy, GDUT441.1 Introduction-37: Organic vs. Electronic EvolutionDigital Integrated Circ

34、uitsFaculty of Materials and Energy, GDUT451.1 Introduction-38: Organic vs. Electronic EvolutionDigital Integrated CircuitsFaculty of Materials and Energy, GDUT461.1 Introduction-39: More Moore & More than Moore2007, Seventh Framework Program (2007-2013) of the European Community, ICT:“More Moore” t

35、argets nanoelectronics devices beyond 32 nmSpecific issues are the increasing process variability and expected physical and reliability limitations of devices and interconnects as well as the need for new circuit architectures and characterization methods and techniques.More than Moore targets heter

36、ogeneous System-on-Chip (SOC)Integration and miniaturization technologiesDesign technologiesManufacturing technologiesDigital Integrated CircuitsFaculty of Materials and Energy, GDUT471.1 Introduction-40: The End of Scaling is Near?“Optical lithography will reach its limits in the range of 0.75-0.50

37、 microns”“Minimum geometries will saturate in the range of 0.3 to 0.5 microns”“X-ray lithography will be needed below 1 micron”“Minimum gate oxide thickness is limited to 2 nm”“Copper interconnects will never work”“Scaling will end in 10 years”Perceived barriers are meant to be surmounted, circumven

38、ted or tunneled throughDigital Integrated CircuitsFaculty of Materials and Energy, GDUT481.2 VLSI Design-1 Levels of Design AbstractionHave different levels of detailsTop Level is your goalInitially not executableOften becomes C+ codeThen create microArchRough hardware resourcesRough communicationCa

39、n be executableFunctional ModelDesign is never top down or bottom up. It is really iterations to match the constraints on both ends: hardware and spec.Digital Integrated CircuitsFaculty of Materials and Energy, GDUT491.2 VLSI Design-2 VLSI Design FlowAlmost all designs use a cell based design flowMo

40、st of the low level layout has been done alreadyLayout for logic gates/flops exists in std cellsMemories are also done by generatorsCan have larger functions completed as wellCan be laid out as a large cell (hard macro)Can be given to you as a collection of std cells (soft macro)Sometimes there is a

41、 need to create some custom cellsCreate std cell libraryCould be for some mixed signal (analog circuits)Or for some special function blocks that are criticalThese cells follow a “full custom flow”Digital Integrated CircuitsFaculty of Materials and Energy, GDUT501.2 VLSI Design-3 Full Custom Design F

42、lowGives the designer the most freedomLots of ropeCan be cleverCan hang yourselves tooFor a specific functionCan achieve best performanceSpeed, power, area, etcMost work/time per functionOptimizations are at a low levelCircuit better be importantThink assembler, only worseDigital Integrated Circuits

43、Faculty of Materials and Energy, GDUT511.2 VLSI Design-4 Schematic Capture/SimulationCircuit drawn many levelsTransistor, gate, and blockUses hierarchyBlocks inside other blocksAllows reuse of designsTool create simulation netlistsComponents and all connectionsDigital Integrated CircuitsFaculty of M

44、aterials and Energy, GDUT521.2 VLSI Design-5 LayoutDraw and place transistors for all devices in schematicRearrange transistors to minimize interconnect length Connect all devices with routing layers Possible to place blocks within other blocksLayout hierarchy should match schematic hierarchyDigital

45、 Integrated CircuitsFaculty of Materials and Energy, GDUT531.2 VLSI Design-6 Design Rule Checking (DRC)Fab has rules for the polygonsRequired for manufacturabilityDRC checker looks for errorsWidthSpaceEnclosureOverlapLots of complex stuff ( more later)Violations flagged for later fixupDigital Integr

46、ated CircuitsFaculty of Materials and Energy, GDUT541.2 VLSI Design-7 Layout versus Schematic (LVS)Extracts netlist from layout by analyzing polygon overlapsCompare extracted netlist with original schematic netlistWhen discrepancies occur, tries to narrow down locationDigital Integrated CircuitsFacu

47、lty of Materials and Energy, GDUT551.2 VLSI Design-8 Layout Parasitic Extraction (LPE)Estimates capacitance between structures in the layoutCalculates resistance of wiresOutput is either a simulation netlist or a file of interblock delaysDigital Integrated CircuitsFaculty of Materials and Energy, GD

48、UT561.2 VLSI Design-9 Cell Based Design Flow (ASIC Flow)Separate teams to design and verifyPhysical design is (semi-) automatedLoops to get device operating frequency correct can be troublingDigital Integrated CircuitsFaculty of Materials and Energy, GDUT571.2 VLSI Design-10 Logic synthesisChanges c

49、loud of combinational functionality into standard cells (gates) from fab-specific libraryChooses standard cell flip-flop/latches for timing statementsAttempts to minimize delay and area of resulting logicDigital Integrated CircuitsFaculty of Materials and Energy, GDUT581.2 VLSI Design-11 Standard Ce

50、ll Placement and RoutingPlace layout for each gate (cell) in design into blockRearrange cell layouts to minimize routingConnect up cellsDigital Integrated CircuitsFaculty of Materials and Energy, GDUT591.2 VLSI Design-12 Using Higher-Level FunctionsCan buy “Intellectual Property” (IP) from various v

51、endors“Soft IP”: RTL or gate level descriptionSynthesize and place and route for your processExamples: Ethernet MAC, USB“Hard IP”: Polygon level descriptionJust hook it upExamples: XAUI Backplane driver, embedded DRAMDigital Integrated CircuitsFaculty of Materials and Energy, GDUT601.2 VLSI Design-1

52、3 Chip AssemblyIntegrate blocks from previous stepsReal chips have different types of blocksCan resemble picture on rightKey is to have a early planAnd continue to update itNeed to have accurate floorplanEarly Floorplanning is keySets the specs for the componentsFunctional, physical, timingMost chip

53、s are constructed by correction; not correct by construction!Digital Integrated CircuitsFaculty of Materials and Energy, GDUT611.2 VLSI Design-14 Validation and Tape OutMaking a mistake is very expensiveHave a tool check all previous types of mistakesCheck all errors, sign off on false positives, fi

54、x errorsRun check tool againTape outUsed to write 9-track computer tapes for mask makingNow, transfer polygons to fabrication company via ftpYoure done! (Except for documentation, test vector generation, device bringup, skew lots, reliability tests, burnin)Digital Integrated CircuitsFaculty of Materials and Energy, GDUT621.3 The Challenges Ahead-1Channel L