《電子技術(shù)數(shù)字基礎(chǔ)-Digital-Fundam課件(PPT 121頁)

1、Chapter 8 Counters (and the Sequential Logic)1.第1頁，共121頁。ContentsIntroductionAnalysis of the Sequential LogicCountersDesign of Sequential Logics2.第2頁，共121頁。8-0 IntroductionThe digital electronic logic is classified as the combinational logic and the sequential logic. (數(shù)字電路分為：組合邏輯電路及時(shí)序邏輯電路)The sequen

2、tial logic includes the combinational logic section and the memory section.3.第3頁，共121頁。8-0 Introduction The logic diagram for the general sequential logicCom-bina-tional LogicMemoryx1xi y1yj q1ql z1zk X = (x1 ,x2 ,xi,)Y = (y1 ,y2 ,yj,)Q = (q1 ,q2 ,ql,)Z = (z1 ,z2 ,zk,)Y = FX,QZ = GX,QQn+1 = HZ,QnOut

3、put Exp.State Exp.Excitation Exp.輸出方程驅(qū)動方程狀態(tài)方程4.第4頁，共121頁。8-0 IntroductionThe sequential logic is classified as the asynchronous one and synchronous one (異步時(shí)序電路和同步時(shí)序電路）.The analysis and design of the sequential logic is discussed in this chapter. And the counter is the most useful device.5.第5頁，共121頁。

4、8-2 Synchronous Counter Operation (同步計(jì)數(shù)器）& Analysis of the Sequential Logic（時(shí)序電路分析）Synchronous (同步): Events that have a fixed time relationship with each other.Synchronous counter: the counter whose flip-flop (FF) are clocked at the same time by a common clock pulse.6.第6頁，共121頁。8-2-1 Analysis of the

5、 Sequential LogicWhats the function of the following logic diagram?How to analyze this diagram? 7.第7頁，共121頁。8-2-1 Analysis of the Sequential Logic -ProcedureProcedure: Write down the clock and excitation expressions for each FF.2. Get their state expressions by replacing the logic expression for the

6、 FF with its excitation expression.寫出每個(gè)觸發(fā)器的時(shí)鐘方程和驅(qū)動方程；2. 將驅(qū)動方程代入觸發(fā)器的特性方程，得到狀態(tài)方程組；8.第8頁，共121頁。8-2-1 Analysis of the Sequential Logic -Procedure3. 寫出輸出方程；5. 說明電路的邏輯功能。4. 依次假定初態(tài),計(jì)算次態(tài),畫出狀態(tài)轉(zhuǎn)換圖(表)或 時(shí)序波形圖 。3. Write down the output expression;4. Assume the present state, and analyze the next state, and draw

7、its state diagram (狀態(tài)轉(zhuǎn)換圖) /state sequence table(狀態(tài)轉(zhuǎn)換表)or its timing diagram （時(shí)序圖）.5. Determine the logic function of the logic diagram.9.第9頁，共121頁。8-2-1 Analysis of the Sequential Logic Example1Ex.1 Determine the logic function.Synchronous Sequential LogicWrite down the clock and excitation expressi

8、ons for each FF.Toggle at the positive edge.T FFJ=K=110.第10頁，共121頁。8-2-1 Analysis of the Sequential Logic Example14. Assume the present sate, and analyze the next state, and draw its state diagram / state sequence table or its timing diagram.11.第11頁，共121頁。8-2-1 1 Analysis of the Sequential Logic Sta

9、te Sequence Table (狀態(tài)轉(zhuǎn)換表)State Sequence Table12.第12頁，共121頁。8-2-1 Analysis of the Sequential Logic State Diagram (狀態(tài)轉(zhuǎn)換圖)00011011State Sequence TableState DiagramQ1Q013.第13頁，共121頁。8-2-1 Analysis of the Sequential Logic Timing Diagram (時(shí)序圖)Timing Diagram14.第14頁，共121頁。8-2-2 A 2-Bit Synchronous Binary Co

10、unter00011011A 2-bit synchronous binary counter(2位同步二進(jìn)制/4進(jìn)制 加法計(jì)數(shù)器）15.第15頁，共121頁。8-2-3 A 3-Bit Synchronous Binary CounterEx.2 Determine the logic function.16.第16頁，共121頁。8-2-3 A 3-Bit Synchronous Binary Counter17.第17頁，共121頁。8-2-3 A 3-Bit Synchronous Binary CounterA 3-bit synchronous binary counter(3位同

11、步二進(jìn)制/8進(jìn)制 加法計(jì)數(shù)器）18.第18頁，共121頁。8-2-4 A 4-Bit Synchronous Decade Counter19.第19頁，共121頁。8-2-4 A 4-Bit Synchronous Decade Counter20.第20頁，共121頁。8-2-4 A 4-Bit Synchronous Decade CounterA 1-bit synchronous decade counter(同步十進(jìn)制加法計(jì)數(shù)器）21.第21頁，共121頁。8-1 Asynchronous Counter Operation (異步計(jì)數(shù)器)Asynchronous: refers

12、to events that do not have a fixed time relationship with each other and, generally, do not occur at the same time.Asynchronous counter: counter in which the FF do not change states at exactly the same time because they do not have a common clock pulse.22.第22頁，共121頁。8-1-1 Analysis of Asynchronous Se

13、quential LogicDetermine the logic function.Asynchronous Sequential Logic23.第23頁，共121頁。8-1-1 Analysis of Asynchronous Sequential Logic24.第24頁，共121頁。8-1-1 Analysis of Asynchronous Sequential Logic25.第25頁，共121頁。8-1-1 Analysis of Asynchronous Sequential Logic26.第26頁，共121頁。8-1-1 Analysis of Asynchronous

14、Sequential Logic27.第27頁，共121頁。8-1-1 Analysis of Asynchronous Sequential LogicState Sequence TableState DiagramA asynchronous decade counter(異步十進(jìn)制加法計(jì)數(shù)器）28.第28頁，共121頁。8-1-2 Some Useful ConceptsValid states (used states) (有效狀態(tài)) states used by the diagram in normal operation.Invalid states (unused state

15、s)(無效狀態(tài)） states which arent used by the diagram in normal operation.29.第29頁，共121頁。8-1-2 Some Useful ConceptsValid StatesInvalid StatesValid CycleInvalid Cycle30.第30頁，共121頁。8-1-2 Some Useful ConceptsValid Cycle (有效循環(huán)) Cycle that includes the valid states.Invalid Cycle(無效循環(huán)） Cycle that includes the in

16、valid states.31.第31頁，共121頁。8-1-2 Some Useful ConceptsStartup automatically (自啟動功能) If a logic diagram doesnt have invalid cycle(無效循環(huán)), it can startup automatically. (電路進(jìn)入無效狀態(tài)之后,在CP脈沖作用下,能自動返回有效循環(huán),稱電路能夠自啟動,否則為不能自啟動）Self-startup check (自啟動檢查) Check if all the invalid states can enter the valid cycle a

17、utomatically. 32.第32頁，共121頁。State DiagramStartup automaticallySelf-startup check33.第33頁，共121頁。8-3 Counters 8-3-1 Categories of CountersThe counter can be classified as the following categories:34.第34頁，共121頁。8-3-1 Categories of CountersModulus-2 counter (2進(jìn)制）Modulus-10 counter (10進(jìn)制）Modulus-60 counte

18、r (60進(jìn)制）Modulus-M counter (M進(jìn)制,任意進(jìn)制）35.第35頁，共121頁。8-2-5 Synchronous Binary CountersQn+1=TQn+TQnC=Q0Q1Q2Q3Negative edge- triggered 36.第36頁，共121頁。8-2-5 Synchronous Binary Countersf01/2f01/4f01/8f01/16f01/16f0The counter is also called the frequency divider (分頻器).C=Q0Q1Q2Q337.第37頁，共121頁。8-2-5 Synchrono

19、us Binary Counters -74161 MSI modulus-16 counterCounter, Divider,Modulus-16(16進(jìn)制)38.第38頁，共121頁。8-2-5 74161 MSI modulus-16 counterParallel data inputs(并行輸入端） Data outputs/States Clock PulseActive at the positive edgeENT,ENP: Enable Pins 39.第39頁，共121頁。8-2-5 74161 MSI modulus-16 counter40.第40頁，共121頁。8-

20、2-5 74161 MSI modulus-16 counterPreset input (Load)(預(yù)置端）(同步預(yù)置)Active-low, synchronously Clear input (清零端）(異步清零)Active-low, asynchronously 41.第41頁，共121頁。8-2-5 74161 MSI modulus-16 counterAt the terminal count of 15, RCO=1.Ripple clock output(進(jìn)位脈沖)42.第42頁，共121頁。8-2-5 74161 MSI modulus-16 counterState

21、DiagramTiming Diagram43.第43頁，共121頁。8-2-5 74161/74163 MSI modulus-16 counterLogic Function Table(功能表） for 74161/7416344.第44頁，共121頁。8-2-5 74161/74163 MSI modulus-16 counterClear input (清零端）(異步清零)Active-low, asynchronously 45.第45頁，共121頁。8-2-5 74161/74163 MSI modulus-16 counterPreset input (Load)(預(yù)置端）(同

22、步預(yù)置)Active-low, synchronously 46.第46頁，共121頁。8-2-5 74161/74163 MSI modulus-16 counterOnly when both of EP and ET are active, is the counter enabled (in counter operation).The outputs plus one at the positive-edge of CP 47.第47頁，共121頁。8-2-5 74161/74163 MSI modulus-16 counterOnly when both of EP and ET

23、are active, is the counter enabled (in counter operation).48.第48頁，共121頁。8-2-5 74160 MSI modulus-10 counter74160 synchronous BCD decade counter (CTR DIV 10 modulus-10, 10 states)49.第49頁，共121頁。8-2-5 74160 MSI modulus-10 counterClear asynchronously 異步清零The clear input is active-LOW.50.第50頁，共121頁。8-2-5

24、74160 MSI modulus-10 counterA timing diagram showing the counter being preset to count 7 (0111).Preset synchronously 同步預(yù)置When the preset input is nonactive, the parallel inputs have no use.The outputs are preset to the corresponding data input only at the active edge of CP.51.第51頁，共121頁。8-2-5 74160

25、MSI modulus-10 counterWhen the terminal count is 9 (TC=9), RCO=152.第52頁，共121頁。8-2-5 74160 MSI modulus-10 counterIf any of ENP and ENT is nonactive (LOW), the outputs are disabled, remain in present states53.第53頁，共121頁。8-3 Up/Down Synchronous Counters(可逆/加減計(jì)數(shù)器)By the control of the up/down input, the

26、 counter, on one hand, can increase one by one; on the other hand, can also decrease one by one.This kind of counter is called up/down (加減) one, bidirectional （可逆）counter, also.54.第54頁，共121頁。8-3 Up/Down Synchronous CountersA basic 3-bit up/down synchronous counter55.第55頁，共121頁。8-3 Up/Down Synchronou

27、s CountersUp/down sequence for a 3-bit binary counterState Sequence Table for a 3-bit binary counter56.第56頁，共121頁。8-3 Up/Down Synchronous CountersState DiagramQ2Q1Q0000001110111010011100101Up sequenceDown sequence57.第57頁，共121頁。8-3 Up/Down Synchronous CountersLogic function table for MSI 74191- a syn

28、chronous modulus-16 up/down counterPreset Asynchronously 異步預(yù)置58.第58頁，共121頁。8-3 Up/Down Synchronous CountersLogic symbol for MSI 74190- a synchronous modulus-10 up/down counter59.第59頁，共121頁。8-3 Up/Down Synchronous CountersTiming Example For a 74190Preset Asynchronously 異步預(yù)置60.第60頁，共121頁。8-4 Design of

29、 Sequential Logics(時(shí)序電路設(shè)計(jì))Sequential logic designSSI Sequential logic design(小規(guī)模)- Design sequential logic using flip-flops 用觸發(fā)器設(shè)計(jì)時(shí)序電路MSI Sequential logic design(中規(guī)模)- Design modulus-M counter using MSI modulus-N counter用N進(jìn)制中規(guī)模集成計(jì)數(shù)器設(shè)計(jì)任意M進(jìn)制計(jì)數(shù)器61.第61頁，共121頁。8-4-1 SSI Sequential logic design- Sequentia

30、l Logics Design using FFProcedure:Step 1: Convert the given problem to a logic problem. Assume the input, output and state variables.Step 2: Get its state diagram.Step 3: Get its state sequence table.Step 4: According to the number of the states, draw a corresponding number-variable K-map. 62.第62頁，共

31、121頁。8-4-1 Sequential Logics Design using FFStep 5: Get the state expressions using K-map.Step 6: Choose the needed flip-flop. Step 7: Get the excitation expressions according to the state expressions and logic expression for the corresponding flip-flop.Step 8: Sketch the logic diagram.63.第63頁，共121頁

32、。8-4-1 Sequential Logics Design using FFExample 1Ex.1: Design a modulus-13 counter with cascaded output.Step 1: Assume the input, output and state variables. Output: CState variables: S0,S1S12State diagram.64.第64頁，共121頁。8-4-1 Sequential Logics Design using FFExample 113 states: 4 flip-fops (13 =24)S

33、tep 2: State sequence table.65.第65頁，共121頁。8-4-1 Sequential Logics Design using FFExample 1Step 3: next-state K-map.Present state:0000Next state: 0001 Output: 0Dont care conditions66.第66頁，共121頁。8-4-1 Sequential Logics Design using FFExample 1Step 4: Get k-map for each state. (Optional)67.第67頁，共121頁。8

34、-4-1 Sequential Logics Design using FFExample 1Step 5: Get the state expressions.68.第68頁，共121頁。8-4-1 Sequential Logics Design using FFExample 1Step 5: Get the output expression.C=Q3Q2Step 6: Choose the flip-flop: J-K flip-flop.69.第69頁，共121頁。8-4-1 Sequential Logics Design using FFExample 1Step 7: Get

35、 the excitation expression.70.第70頁，共121頁。8-4-1 Sequential Logics Design using FFExample 1Step 8: Draw the logic diagram.C=Q3Q271.第71頁，共121頁。8-4-1 Sequential Logics Design using FFExample 1Step 9: Self-startup check (自啟動檢查)It can startup automatically.72.第72頁，共121頁。8-4-1 Sequential Logics Design usin

36、g FFExample 2Ex. 2: Design a logic diagram that can check the series data. When there are three or more than three HIGH inputs in series, the output is 1; otherwise , the output is 0. 設(shè)計(jì)一個(gè)串行數(shù)據(jù)檢測器。當(dāng)連續(xù)輸入3個(gè)或3個(gè)以上1的時(shí)候，輸出為1；否則為0。 73.第73頁，共121頁。8-4-1 Sequential Logics Design using FFExample 2Step 1: Analyz

37、e the problem, assume the input/output variables, and get its state diagram/state sequence table.Assume:X: the input variable;Y: the output variable;States: S0 the input is 0; S1 there is only one HIGH input. S2 there is two HIGH inputs in series. S3 there is three or more than three HIGH inputs in

38、series.74.第74頁，共121頁。8-4-1 Sequential Logics Design using FFExample 2Step 2: State sequence tableEquivalent States(等價(jià)狀態(tài))The input75.第75頁，共121頁。8-4-1 Sequential Logics Design using FFExample 2Step 3: K-map0001103 states: 2 flip-fops (3 N, more than one MSI device is needed.107.第107頁，共121頁。8-4-3 Seque

39、ntial Logics Design using MSI Counter1. MNSkip N-M statesTwo methods:(1) Implement it using the CLEAR (RESET) input (generally the CLEAR input is asynchronous). (利用清零端，反饋歸零法)(2) Implement it using the PRESET input. (Some of the PRESET input are asynchronous, and others are synchronous) (利用預(yù)置端，置數(shù)法)10

40、8.第108頁，共121頁。8-4-3 Sequential Logics Design using MSI CounterMomentary/Astable state (瞬態(tài)), not included in the valid cycle.異步清零，瞬態(tài)不包括在有效循環(huán)中Preset the states at any state可在任意狀態(tài)下進(jìn)行預(yù)置同步預(yù)置沒有瞬態(tài)，異頻預(yù)置有瞬態(tài)。109.第109頁，共121頁。8-4-3 Sequential Logics Design using MSI CounterOnly when both of EP and ET are active

41、, is the counter enabled (in counter operation).Ex. 1 Implement a modulus-6 counter using 74160. Logic Function Table for 74160Clear inputActive-low, asynchronously(異步清零) Preset input (Load)Active-low, synchronously(同步預(yù)置) 110.第110頁，共121頁。8-4-3 Sequential Logics Design using MSI CounterModulus-10 Counter111.第111頁，共121頁。8-4-3 Sequential Logics Design using MSI Counter(1) Logic circuit using the Clear