VHDL復(fù)雜電路描述方法精品課件

1、第六講 復(fù)雜電路的描述方法第1頁，共130頁。ECE 545 Introduction to VHDLVHDL for SpecificationVHDL for SimulationVHDL for Synthesis第2頁，共130頁。ECE 545 Introduction to VHDLLevels of design descriptionAlgorithmic levelRegister Transfer LevelLogic (gate) levelCircuit (transistor) levelPhysical (layout) levelLevel of descript

2、ion most suitable for synthesis第3頁，共130頁。ECE 545 Introduction to VHDLRegister Transfer Logic (RTL) Design Description Combinational Logic Combinational LogicRegistersTodays Topic第4頁，共130頁。ECE 545 Introduction to VHDLVHDL Design StylesComponents andinterconnectsstructuralVHDL Design StylesdataflowCon

3、current statementsbehavioral Registers State machines Test benchesSequential statementsSubset most suitable for synthesis 第5頁，共130頁。VHDL的執(zhí)行語句描述結(jié)構(gòu)體中電路硬件的變化特點；結(jié)構(gòu)體中的任何執(zhí)行語句都是并行語句；并行語句的種類有：賦值類語句：數(shù)據(jù)流描述 (邏輯函數(shù)的運算)元件類語句：結(jié)構(gòu)描述 （邏輯符號的連接）進程語句：行為描述 （電路功能的流程）第6頁，共130頁。ECE 545 Introduction to VHDLXOR3 Example第7頁，共1

4、30頁。ECE 545 Introduction to VHDLEntity (XOR3 Gate)entity XOR3 is port( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; RESULT : out STD_LOGIC );end XOR3;第8頁，共130頁。ECE 545 Introduction to VHDLDataflow Architecture (XOR3 Gate)architecture XOR3_DATAFLOW of XOR3 issignal U1_OUT: STD_LOGIC;begin U1

5、_OUT=A xor B;RESULT A, I2 = B, Y = U1_OUT); U2: XOR2 port map (I1 = U1_OUT, I2 = C, Y = RESULT);end XOR3_STRUCTURAL;ABCRESULTXOR3第10頁，共130頁。ECE 545 Introduction to VHDLBehavioral Architecture (XOR Gate)architecture XOR3_BEHAVIORAL of XOR3 isbeginXOR3_BEHAVE: process (A,B,C)beginif (A xor B xor C) =

6、1) thenRESULT = 1;elseRESULT = 0;end if;end process XOR3_BEHAVE;end XOR3_BEHAVIORAL;第11頁，共130頁。ECE 545 Introduction to VHDLDataflow Description Describes how data moves through the system and the various processing steps. Data Flow uses series of concurrent statements to realize logic. Concurrent st

7、atements are evaluated at the same time; thus, order of these statements doesnt matter.Data Flow is most useful style when series of Boolean equations can represent a logic. 第12頁，共130頁。ECE 545 Introduction to VHDLData-flow VHDL concurrent signal assignment () conditional concurrent signal assignment

8、 (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate)Major instructionsConcurrent statements第13頁，共130頁。ECE 545 Introduction to VHDLData-flow VHDL concurrent signal assignment () conditional concurrent signal assignment (when-else) selected

9、 concurrent signal assignment (with-select-when) generate scheme for equations (for-generate)Major instructionsConcurrent statements第14頁，共130頁。ECE 545 Introduction to VHDLData-flow VHDL: Example第15頁，共130頁。ECE 545 Introduction to VHDLData-flow VHDL: ExampleLIBRARY ieee ;USE ieee.std_logic_1164.all ;E

10、NTITY fulladd ISPORT (x, y, Cin: IN STD_LOGIC ; s, Cout: OUT STD_LOGIC ) ;END fulladd ;ARCHITECTURE LogicFunc OF fulladd ISBEGINs = x XOR y XOR Cin ;Cout = (x AND y) OR (Cin AND x) OR (Cin AND y) ;END LogicFunc ;第16頁，共130頁。ECE 545 Introduction to VHDLLogic OperatorsLogic operatorsLogic operators pre

11、cedenceand or nand nor xor not xnor notand or nand nor xor xnorHighestLowest第17頁，共130頁。ECE 545 Introduction to VHDL Wanted: Y = ab + cdIncorrectY = a and b or c and d equivalent toY = (a and b) or c) and d equivalent toY = (ab + c)dCorrectY = (a and b) or (c and d)No Implied Precedence 第18頁，共130頁。EC

12、E 545 Introduction to VHDLConcatenationsignal A: STD_LOGIC_VECTOR(3 downto 0);signal B: STD_LOGIC_VECTOR(3 downto 0);signal C, D, E: STD_LOGIC_VECTOR(7 downto 0);A = ”0000”; B = ”1111”; C = A & B; - C = ”00001111”D = 0 & ”0001111”; - D = ”00001111”E = 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1; - E = ”00001111”第

13、19頁，共130頁。ECE 545 Introduction to VHDLRotations in VHDLA(3)A(2)A(1)A(0)A(2)A(1)A(0)A(3)A1A_rotL = A(2 downto 0) & A(3)第20頁，共130頁。ECE 545 Introduction to VHDLArithmetic Functions in VHDL (1)To use basic arithmetic operations involving std_logic_vectors you need to include thefollowing library package

14、s:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;第21頁，共130頁。ECE 545 Introduction to VHDLArithmetic Functions in VHDL (2)You can use standard +, - operatorsto perform addition and subtraction: signal A : STD_LOGIC_VECTOR(3 downto 0); signal B : STD_LOGIC_VECTOR(3 downto 0);

15、signal C : STD_LOGIC_VECTOR(3 downto 0); C = A + B;第22頁，共130頁。ECE 545 Introduction to VHDLData-flow VHDL concurrent signal assignment () conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate)Major ins

16、tructionsConcurrent statements第23頁，共130頁。ECE 545 Introduction to VHDLData Flow Instructions (1)target_signal = value1 when condition1 else value2 when condition2 else . . . valueN-1 when conditionN-1 else valueN;When - Else.Value NValue N-1Condition N-1Condition 2Condition 1Value 2Value 1Target Sign

17、al第24頁，共130頁。ECE 545 Introduction to VHDLOperatorsRelational operatorsLogic and relational operators precedence= /= = not= /= =and or nand nor xor xnorHighestLowest第25頁，共130頁。ECE 545 Introduction to VHDL compare a = bcIncorrect when a = b and c else equivalent to when (a = b) and c else Correct when

18、 a = (b and c) else Priority of logic and relational operators 第26頁，共130頁。ECE 545 Introduction to VHDLData-flow VHDL concurrent signal assignment () conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-genera

19、te)Major instructionsConcurrent statements第27頁，共130頁。ECE 545 Introduction to VHDLData Flow Instructions (2)with choice_expression select target_signal = expression1 when choices1, expression2 when choices2, . . . expressionN when choicesN;With - Selectchoices1choices2choicesNexpression1target_signal

20、choice expressionexpression2expressionN第28頁，共130頁。ECE 545 Introduction to VHDLMLU Example第29頁，共130頁。ECE 545 Introduction to VHDLMLU: Block Diagram第30頁，共130頁。ECE 545 Introduction to VHDLMLU: Entity Declarationlibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity MLU is port( NEG_A : in STD_LOGIC; NEG_B : i

21、n STD_LOGIC; NEG_Y : in STD_LOGIC; A : in STD_LOGIC; B : in STD_LOGIC; L1 : in STD_LOGIC; L0 : in STD_LOGIC; Y : out STD_LOGIC );end MLU;第31頁，共130頁。ECE 545 Introduction to VHDLMLU: Architecture Declarative Sectionarchitecture MLU_DATAFLOW of MLU issignal A1:STD_LOGIC;signal B1:STD_LOGIC;signal Y1:ST

22、D_LOGIC;signal MUX_0:STD_LOGIC;signal MUX_1:STD_LOGIC;signal MUX_2:STD_LOGIC;signal MUX_3:STD_LOGIC;signal L: STD_LOGIC_VECTOR(1 downto 0);第32頁，共130頁。ECE 545 Introduction to VHDLMLU - Architecture BodybeginA1= not A when (NEG_A=1) elseA;B1= not B when (NEG_B=1) else B;Y = not Y1 when (NEG_Y=1) elseY

23、1;MUX_0 = A1 and B1;MUX_1 = A1 or B1;MUX_2 = A1 xor B1;MUX_3 = A1 xnor B1; L=L1 & L0;with (L) select Y1 = MUX_0 when 00, MUX_1 when 01, MUX_2 when 10, MUX_3 when others;end MLU_DATAFLOW;第33頁，共130頁。ECE 545 Introduction to VHDLData-flow VHDL concurrent signal assignment () conditional concurrent signa

24、l assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate)Major instructionsConcurrent statements第34頁，共130頁。ECE 545 Introduction to VHDLPARITY Example第35頁，共130頁。ECE 545 Introduction to VHDLPARITY: Block Diagram第36頁，共130頁。ECE 545 Int

25、roduction to VHDLFor Generate StatementFor Generatename: for parameter_specification generate Declaration Statements begin Concurrent Statements end generate name;第37頁，共130頁。ECE 545 Introduction to VHDLPARITY: Entity Declarationlibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity PARITY is port( Parity_i

26、n : in STD_LOGIC_VECTOR(7 downto 0); Parity_out : out STD_LOGIC );end PARITY;第38頁，共130頁。ECE 545 Introduction to VHDLPARITY: Block DiagramXor_out(1)Xor_out(2)Xor_out(3)Xor_out(4)Xor_out(5)Xor_out(6)Xor_out(7)第39頁，共130頁。ECE 545 Introduction to VHDLPARITY: Architecturearchitecture PARITY_DATAFLOW of PA

27、RITY is signal Xor_out: std_logic_vector (7 downto 1);beginXor_out(1) = Parity_in(0) xor Parity_in(1);G2: for i in 1 to 6 generateXor_out(i+1) = Xor_out(i) xor Parity_in(i+1);end generate G2; Parity_out B01 if AB1010 independently of A and B0101 independently of A and B11 (invalid inputs)-第48頁，共130頁

28、。ECE 545 Introduction to VHDLABX_OUTY_OUTBIT_COMPAREentity BIT_COMPARE is port(A, B, X_IN, Y_IN: in STD_LOGIC; X_OUT, Y_OUT: out STD_LOGIC);end BIT_COMPARE;X_INY_INBasic building block第49頁，共130頁。ECE 545 Introduction to VHDLX_IN & Y_INX_OUT & Y_OUT0000 if A=B if A=1 and B=001 if A=0 and B=11010 indep

29、endently of A and B0101 independently of A and B11 (invalid inputs)-Basic building block Truth Table第50頁，共130頁。ECE 545 Introduction to VHDL8-bit comparator - ArchitectureA(7)B(7)CMP_IN(1)CMP_IN(0)A(6)B(6)A(0)B(0)CMP_OUT(1)CMP_OUT(0)INT_X(7)INT_X(1)INT_Y(7)INT_Y(1)INT_X(6)INT_Y(6)第51頁，共130頁。ECE 545 I

30、ntroduction to VHDLarchitecture STRUCTURE of COMPARE8 is component BIT_COMPARE port(A, B, X_IN, Y_IN: in STD_LOGIC; X_OUT, Y_OUT: out STD_LOGIC); end component; signal INT_X, INT_Y: STD_LOGIC_VECTOR(7 downto 1);begin C7: BIT_COMPARE port map(A(7), B(7), CMP_IN(1), CMP_IN(0), INT_X(7), INT_Y(7); C6:

31、BIT_COMPARE port map(A(6), B(6), INT_X(7), INT_Y(7), INT_X(6), INT_Y(6); . . . C0: BIT_COMPARE port map(A(0), B(0), INT_X(1), INT_Y(1), CMP_OUT(0), CMP_OUT(1);end STRUCTURE;Architecture without for-generate第52頁，共130頁。ECE 545 Introduction to VHDL8-bit comparator - ArchitectureA(7)B(7)CMP_IN(1)CMP_IN(

32、0)A(6)B(6)A(0)B(0)CMP_OUT(1)CMP_OUT(0)INT_X(7)INT_X(1)INT_Y(7)INT_Y(1)INT_X(8)INT_Y(8)INT_X(0)INT_Y(0)第53頁，共130頁。ECE 545 Introduction to VHDLarchitecture STRUCTURE of COMPARE8 is component BIT_COMPARE port(A, B, X_IN, Y_IN: in STD_LOGIC; X_OUT, Y_OUT: out STD_LOGIC); end component; signal INT_X, INT

33、_Y: STD_LOGIC_VECTOR(8 downto 0);begin INT_X(8) = CMP_IN(1); INT_Y(8) = CMP_IN(0); CASCADE: for I in 7 downto 0 generate C: BIT_COMPARE port map(A(I), B(I), INT_X(I+1), INT_Y(I+1), INT_X(I), INT_Y(I); end generate; CMP_OUT(1) = INT_X(0); CMP_OUT(0) = INT_Y(0);end STRUCTURE;Architecture with for-gene

34、rate第54頁，共130頁。ECE 545 Introduction to VHDLStructural VHDL component instantiation (port map) generate scheme for component instantiations (for-generate) component instantiation with generic (generic map, port map)Major instructions第55頁，共130頁。ECE 545 Introduction to VHDLN-bit Comparator Entity decla

35、rationentity COMPAREN is generic(N: positive); - N width of operands port( A, B: in BIT_VECTOR(N-1 downto 0); CMP_IN: in BIT_VECTOR(1 downto 0); CMP_OUT: out BIT_VECTOR(1 downto 0);end COMPAREN;第56頁，共130頁。ECE 545 Introduction to VHDLarchitecture STRUCTURE of COMPAREN is component BIT_COMPARE port(A,

36、 B, X_IN, Y_IN: in STD_LOGIC; X_OUT, Y_OUT: out STD_LOGIC); end component; signal INT_X, INT_Y: STD_LOGIC_VECTOR(N downto 0);begin INT_X(N) = CMP_IN(1); INT_Y(N) = CMP_IN(0); CASCADE: for I in N-1 downto 0 generate C: BIT_COMPARE port map(A(I), B(I), INT_X(I+1), INT_Y(I+1), INT_X(I), INT_Y(I); end g

37、enerate; CMP_OUT(1) = INT_X(0); CMP_OUT(0) 16) port map(A = P1, B = P2, CMP_IN = SIG_IN, CMP_OUT = SIG_OUT );N-bit Comparator Instantiation第58頁，共130頁。ECE 545 Introduction to VHDLBehavioral Design Style第59頁，共130頁。ECE 545 Introduction to VHDLBehavioral VHDL (subset) process statement (process) sequent

38、ial signal assignment ()Major instructionsSequential statementsGeneralRegisters, counters, shift registers, etc. if-then-else statementState machines case-when statementTestbenches loops (for-loop, while-loop) 第60頁，共130頁。ECE 545 Introduction to VHDLAnatomy of a Processlabel: process (sensitivity lis

39、t) declaration partbegin statement partend process;OPTIONAL第61頁，共130頁。ECE 545 Introduction to VHDLA process can be given a unique name using an optional LABELThis is followed by the keyword PROCESSThe keyword BEGIN is used to indicate the start of the processAll statements within the process are exe

40、cuted SEQUENTIALLY. Hence, order of statements is important.A process must end with the keywords END PROCESS.TESTING: process beginTEST_VECTOR=“00”;wait for 10 ns;TEST_VECTOR=“01”;wait for 10 ns;TEST_VECTOR=“10”;wait for 10 ns;TEST_VECTOR=“11”;wait for 10 ns;end process;A process is a sequence of in

41、structions referred to as sequential statements.What is a PROCESS?The Keyword PROCESS第62頁，共130頁。ECE 545 Introduction to VHDLPROCESS with a SENSITIVITY LISTList of signals to which the process is sensitive.Whenever there is an event on any of the signals in the sensitivity list, the process fires.Eve

42、ry time the process fires, it will run in its entirety.WAIT statements are NOT ALLOWED in a processes with SENSITIVITY LIST.label: process (sensitivity list) declaration part begin statement part end process; 第63頁，共130頁。ECE 545 Introduction to VHDLProcesses in VHDLProcesses Describe Sequential Behav

43、iorProcesses in VHDL Are Very Powerful StatementsAllow to define an arbitrary behavior that may be difficult to represent by a real circuitNot every process can be synthesizedUse Processes with Caution in the Code to Be SynthesizedUse Processes Freely in Testbenches第64頁，共130頁。ECE 545 Introduction to

44、 VHDLUse of Processes in the Synthesizable Code第65頁，共130頁。ECE 545 Introduction to VHDLComponent Equivalent of a ProcessAll signals which appear on the left of signal assignment statement (=) are outputs e.g. y, zAll signals which appear on the right of signal assignment statement (=) or in logic exp

45、ressions are inputs e.g. w, a, b, cAll signals which appear in the sensitivity list are inputs e.g. clkNote that not all inputs need to be included in the sensitivity listpriority: PROCESS (clk)BEGINIF w(3) = 1 THENy = 11 ;ELSIF w(2) = 1 THEN y = 10 ;ELSIF w(1) = c THENy = a and b;ELSEz = 00 ;END IF

46、 ;END PROCESS ;wayzprioritybcclk第66頁，共130頁。ECE 545 Introduction to VHDLRegisters第67頁，共130頁。ECE 545 Introduction to VHDLClock D 0 1 1 0 1 0 1 Truth table Graphical symbolt 1 t 2 t 3 t 4 TimeClock D Q Timing diagramQ(t+1)Q(t)D latchD Q Clock 第68頁，共130頁。ECE 545 Introduction to VHDLClk D 0 1 0 1 Truth t

47、able t 1 t 2 t 3 t 4 TimeClock D Q Timing diagramQ(t+1)Q(t)D flip-flopD Q Clock Graphical symbol0 Q(t)1 第69頁，共130頁。ECE 545 Introduction to VHDLLIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY latch IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END latch ;ARCHITECTURE Behavior OF latch

48、IS BEGINPROCESS ( D, Clock ) BEGINIF Clock = 1 THEN Q = D ; END IF ; END PROCESS ; END Behavior; D latchD Q Clock 第70頁，共130頁。ECE 545 Introduction to VHDLLIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock: INSTD_LOGIC ; Q: OUTSTD_LOGIC) ; END flipflop ;ARCHITECTURE Behavi

49、or_1 OF flipflop IS BEGINPROCESS ( Clock ) BEGIN IF ClockEVENT AND Clock = 1 THEN Q = D ; END IF ; END PROCESS ; END Behavior_1 ; D flip-flopD Q Clock 第71頁，共130頁。ECE 545 Introduction to VHDLLIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock: INSTD_LOGIC ; Q: OUTSTD_LOGIC

50、) ; END flipflop ;ARCHITECTURE Behavior_2 OF flipflop IS BEGINPROCESSBEGIN WAIT UNTIL ClockEVENT AND Clock = 1 ; Q = D ; END PROCESS ; END Behavior_2 ; D flip-flopD Q Clock 第72頁，共130頁。ECE 545 Introduction to VHDLLIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock

51、: IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ;ARCHITECTURE Behavior OF flipflop IS BEGINPROCESS ( Resetn, Clock ) BEGIN IF Resetn = 0 THEN Q = 0 ; ELSIF ClockEVENT AND Clock = 1 THEN Q = D ; END IF ; END PROCESS ;END Behavior ; D flip-flop with asynchronous resetD Q Clock Resetn 第73頁，共130頁。ECE

52、 545 Introduction to VHDLLIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ;ARCHITECTURE Behavior OF flipflop IS BEGINPROCESS BEGIN WAIT UNTIL ClockEVENT AND Clock = 1 ; IF Resetn = 0 THEN Q = 0 ; ELSEQ = D ; EN

53、D IF ; END PROCESS ;END Behavior ; D flip-flop with synchronous resetD Q Clock Resetn 第74頁，共130頁。ECE 545 Introduction to VHDL8-bit register with asynchronous resetLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY reg8 ISPORT ( D: IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;Resetn, Clock: IN STD_LOGIC ;Q : OUT

54、STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;END reg8 ;ARCHITECTURE Behavior OF reg8 ISBEGINPROCESS ( Resetn, Clock )BEGINIF Resetn = 0 THENQ = 00000000 ;ELSIF ClockEVENT AND Clock = 1 THENQ = D ;END IF ;END PROCESS ;END Behavior ;ResetnClockreg888DQ第75頁，共130頁。ECE 545 Introduction to VHDLN-bit register with asyn

55、chronous resetLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY regn ISGENERIC ( N : INTEGER := 16 ) ;PORT ( D: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;Resetn, Clock: IN STD_LOGIC ;Q: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;END regn ;ARCHITECTURE Behavior OF regn ISBEGINPROCESS ( Resetn, Clock )BEGINIF Res

56、etn = 0 THENQ 0) ;ELSIF ClockEVENT AND Clock = 1 THENQ = D ;END IF ;END PROCESS ;END Behavior ;ResetnClockregnNNDQ第76頁，共130頁。ECE 545 Introduction to VHDLLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY regn ISGENERIC ( N : INTEGER := 8 ) ;PORT (D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;Enable, Clock:

57、IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;END regn ;ARCHITECTURE Behavior OF regn ISBEGINPROCESS (Clock)BEGINIF (ClockEVENT AND Clock = 1 ) THENIF Enable = 1 THENQ = D ;END IF ;END IF;END PROCESS ;END Behavior ;N-bit register with enableQDEnableClockregnNN第77頁，共130頁。ECE 545 Introductio

58、n to VHDLCounters第78頁，共130頁。ECE 545 Introduction to VHDLLIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;ENTITY upcount ISPORT (Clear, Clock: IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0) ) ;END upcount ;ARCHITECTURE Behavior OF upcount ISBEGINupcount: PROCESS ( Cl

59、ock )BEGINIF (ClockEVENT AND Clock = 1) THENIF Clear = 1 THENQ = 00 ;ELSEQ = Q + “01” ;END IF ;END IF;END PROCESS;END Behavior ;2-bit up-counter with synchronous resetQClearClockupcount2第79頁，共130頁。ECE 545 Introduction to VHDLLIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all

60、;ENTITY upcount ISPORT ( Clock, Resetn, Enable : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ;END upcount ;4-bit up-counter with asynchronous reset (1)QEnableClockupcount4Resetn第80頁，共130頁。ECE 545 Introduction to VHDLARCHITECTURE Behavior OF upcount ISSIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO