時(shí)序邏輯的設(shè)計(jì)優(yōu)化VHDL與數(shù)字集成電路設(shè)計(jì)理論

1、第三章 時(shí)序邏輯的設(shè)計(jì)優(yōu)化VHDL與數(shù)字集成電路設(shè)計(jì)2 storage mechanisms positive feedback charge-based鎖存器：電平敏感時(shí)序邏輯電路類(lèi)型寄存器：邊沿敏感DClkQClkDQDClkQClkDQ 鎖存器類(lèi)型基于鎖存器的設(shè)計(jì) N latch is transparentwhen f = 0 P latch is transparent when f = 1NLatchLogicLogicPLatchf時(shí)間約束tCLKtDtc2qtholdtsutQDATASTABLEDATASTABLERegisterCLKDQ正反饋與雙穩(wěn)態(tài)Vi1ACBVo2Vi

2、1=Vo2Vo1Vi2Vi2=Vo1雙穩(wěn)態(tài)Gain should be larger than 1 in the transition region基本鎖存器電路DCLKCLKDConverting into a MUXForcing the state(can implement as NMOS-only)多路選擇器鎖存器Negative latch(transparent when CLK= 0)Positive latch(transparent when CLK= 1)CLK10DQ0CLK1DQ具體電路主從寄存器Two opposite latches trigger on edge

3、Also called master-slave latch pair 具體電路Multiplexer-based latch pair建立時(shí)間降低時(shí)鐘負(fù)載的主從寄存器RS觸發(fā)器帶有時(shí)鐘控制的RS觸發(fā)器Cross-coupled NANDsAdded clock不同的狀態(tài)儲(chǔ)存機(jī)制DCLKCLKQDynamic (charge-based)StaticC2MOS寄存器施密特觸發(fā)器VTC with hysteresisRestores signal slopes CMOS施密特觸發(fā)器Moves switching thresholdof the first inverter CMOS施密特觸發(fā)器2

4、數(shù)據(jù)寄存器及相關(guān)電路最快數(shù)據(jù)傳遞：時(shí)鐘周期數(shù)據(jù)寄存器及相關(guān)電路最快數(shù)據(jù)傳遞時(shí)間：時(shí)鐘周期在輸入端添加控制電路，構(gòu)成其他類(lèi)型的觸發(fā)器D觸發(fā)器的控制與擴(kuò)展數(shù)據(jù)寄存器及相關(guān)電路數(shù)據(jù)寄存器及相關(guān)電路D觸發(fā)器的控制與擴(kuò)展并行寄存與移位寄存數(shù)據(jù)寄存器及相關(guān)電路多功能移位寄存器數(shù)據(jù)寄存器及相關(guān)電路第四章 算數(shù)邏輯單元4.1 加法器4.2 乘法器VHDL與數(shù)字集成電路設(shè)計(jì)加法器設(shè)計(jì)加法運(yùn)算從最低位開(kāi)始，逐步向高位進(jìn)行；每一位相加時(shí)，產(chǎn)生1位結(jié)果（s），同時(shí)產(chǎn)生1位進(jìn)位（c）；最低位相加時(shí)，只需要考慮2個(gè)數(shù)據(jù)的相加：半加；其余位相加時(shí)，需要考慮3個(gè)數(shù)據(jù)的相加：全加。4.1 加法器、算數(shù)邏輯單元加法器設(shè)計(jì)半加器4

5、.1 加法器、算數(shù)邏輯單元加法器設(shè)計(jì)全加器4.2 加法器、算數(shù)邏輯單元利用半加單元設(shè)計(jì)全加器4.2 加法器、算數(shù)邏輯單元可擴(kuò)展的串行加法器： 采用全加器級(jí)聯(lián)構(gòu)成4.2 加法器、算數(shù)邏輯單元4位串行加法器：ASIC設(shè)計(jì) 第1級(jí)采用半加； 最高級(jí)取消進(jìn)位。4.2 加法器、算數(shù)邏輯單元3536Define 3 new variable which ONLY depend on A, BGenerate (G) = ABPropagate (P) = A BDelete = A BCan also derive expressions for S and Co based on D and P Pro

6、pagate (P) = A + BNote that we will be sometimes using an alternate definition for 37Worst case delay linear with the number of bitsGoal: Make the fastest possible carry path circuittd = O(N)tadder = (N-1)tcarry + tsum3828 Transistors3940Exploit Inversion Property4142434445Also called Carry-Skip46ta

7、dder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum47484950515253Expanding Lookahead equations:All the way:5455Can continue building the tree hierarchically.5616-bit radix-2 Kogge-Stone tree57PropagateGenerate58PropagateGenerate59第四章算數(shù)邏輯單元4.1 加法器4.2 乘法器VHDL與數(shù)字集成電路設(shè)計(jì)8位乘法器設(shè)計(jì)：基于基本單元的擴(kuò)展設(shè)計(jì)2位乘法器：由1位乘法結(jié)果相加而成成本：4+4+4 門(mén)時(shí)間：1+34.3 數(shù)據(jù)累加與乘法器設(shè)計(jì)8位乘法器設(shè)計(jì)：基于基本單元的擴(kuò)展設(shè)計(jì)4位乘法器：由2位乘法結(jié)果相加而成4個(gè)2位乘法器并