基于PLD的矩陣鍵盤狀態(tài)機控制

1、FPGA設(shè)計技術(shù)課程報告課程報告題目：基于PLD的矩陣鍵盤狀態(tài)機控制專 業(yè)：電路與系統(tǒng)學(xué) 號：2016080904姓名：熊文杰日 期： 2015 年 12月15 日 一、FPGA矩陣鍵盤電路圖在FPGA中的電路，與單片機電路基本相同，圖如下：在上電默認(rèn)情況下，L3:0 =4b1，因為上拉了3.3V，而默認(rèn)情況下H.3:0為低電平；一旦有某一個按鍵被按下，便是是的該路電路流向該按鍵的H，是的L檢測不到電流。因此可以通過對每一行H輸出的控制，來檢索是哪一個按鍵被按下了，這也原理和單片機中一樣，只是寫法不一樣罷了。了。二、FPGA矩陣鍵盤FSM1. 代碼代碼如下所示，采用了三段式狀態(tài)機來描述矩陣鍵盤

2、。本模塊形式與上一張按鍵消抖動雷同，方便移植。/* Module Name : matrix_key_design.v* Engineer : Crazy Bingo* Target Device : EP2C8Q208C8* Tool versions : Quartus II 11.0* Create Date : 2011-6-26* Revision : v1.0* Description : */module matrix_key_design(input clk,input rst_n,input 3:0 col_data,output reg 3:0 row_data,outpu

3、t key_flag, output reg 3:0 key_value );reg 19:0 cnt; always (posedge clk or negedge rst_n)beginif(!rst_n)cnt = 0;elsecnt -0-1-2-3* | | | |* R2 -4-5-6-7* | | | |* R1 -8-9-A-B* | | | |* R0 -C-D-E-F* | | | |* C3 C2 C1 C0*/parameter SCAN_IDLE = 3b000;parameter SCAN_JITTER= 3b001;parameter SCAN_COL0 = 3b

4、011;parameter SCAN_COL1 = 3b010;parameter SCAN_COL2 = 3b110;parameter SCAN_COL3 = 3b100;parameter SCAN_READ = 3b101;parameter SCAN_JTTTER2= 3b111;reg 2:0 current_state;reg 2:0 next_state;always(posedge clk or negedge rst_n)beginif(!rst_n)current_state = SCAN_IDLE;else if(cnt = 20hfffff)current_state

5、 = next_state;endalways*begincase(current_state)SCAN_IDLE : if(col_data != 4b1111) next_state = SCAN_JITTER;else next_state = SCAN_IDLE;SCAN_JITTER: if(col_data != 4b1111) next_state = SCAN_COL0;else next_state = SCAN_IDLE;SCAN_COL0 : if(col_data != 4b1111) next_state = SCAN_READ;else next_state = S

6、CAN_COL1;SCAN_COL1 : if(col_data != 4b1111) next_state = SCAN_READ;else next_state = SCAN_COL2;SCAN_COL2 : if(col_data != 4b1111) next_state = SCAN_READ;else next_state = SCAN_COL3;SCAN_COL3 : if(col_data != 4b1111) next_state = SCAN_READ;else next_state = SCAN_IDLE;SCAN_READ : if(col_data != 4b1111

7、) next_state = SCAN_JTTTER2;else next_state = SCAN_IDLE;SCAN_JTTTER2: if(col_data != 4b1111) next_state = SCAN_JTTTER2;else next_state = SCAN_IDLE;endcaseendreg 3:0 col_data_r;reg 3:0 row_data_r;reg key_flag_r0;always(posedge clk or negedge rst_n)beginif(!rst_n)beginrow_data = 4b0000;Key_flag_r0 = 0

8、;endelse if(cnt = 20hfffff)begincase(next_state)SCAN_IDLE : beginrow_data = 4b0000;key_flag_r0 = 0;endSCAN_COL0 : row_data = 4b1110;SCAN_COL1 : row_data = 4b1101;SCAN_COL2 : row_data = 4b1011;SCAN_COL3 : row_data = 4b0111;SCAN_READ : beginrow_data_r = row_data;col_data_r = col_data;key_flag_r0 = 1;e

9、nddefault:; /default vauleendcaseendendalways (posedge clk or negedge rst_n)beginif(!rst_n)key_value = 0;else if(cnt = 20hfffff)beginif(key_flag_r0 = 1b1) /the mark of key is pressedbegincase (row_data_r,col_data_r)8b0111_0111: key_value = 4h0;8b0111_1011: key_value = 4h1;8b0111_1101: key_value = 4h

10、2;8b0111_1110: key_value = 4h3;8b1011_0111: key_value = 4h4;8b1011_1011: key_value = 4h5;8b1011_1101: key_value = 4h6;8b1011_1110: key_value = 4h7;8b1101_0111: key_value = 4h8;8b1101_1011: key_value = 4h9;8b1101_1101: key_value = 4hA;8b1101_1110: key_value = 4hB;8b1110_0111: key_value = 4hC;8b1110_1011: key_value = 4hD;8b1110_1101: key_value = 4hE;8b1110_1110: key_value = 4hF;default : key_value = key_value;endcaseendelsekey_value = key_value;endendreg key_flag_r2,key_flag_r1;always(posedge clk or negedge rst_n)beginif(!rst_n)beginkey_fl