北科大數(shù)字電子技術(shù)生教學(xué)課件授課

選選擇物（飲料兩罐：6元吐出：物（飲料兩罐投入：硬幣投入：硬幣（10元吐出：應(yīng)找零（吐出：應(yīng)找零（4元Combinationallogic

Definition:theoutputisonlydependedoncurrentcomponents：Logic

ChapterSequentiallogic

Definition:Theoutputisnotonlydependedonthecurrentinputsbutalsodependedonthepastcomponents：LogicGates FlipFlops,ChapterDigitalDigitalCHAPTERCHAPTERLatches,Flip-Flopsand（鎖存器、觸發(fā)器和定時(shí)器 觸發(fā)

7-17-17-1-17-1-1S-R(Set-Resetlatch（基本R-S觸發(fā)器）7-1-2GatedS-Rlatch（門(mén)控R-S觸發(fā)器）7-1-3GatedDlatch（門(mén)控D觸發(fā)器7-1-1S-R(Set-Reset)7-1-1S-R(Set-Reset)&a&b7-1-17-1-1S-R(Set-Reset)CrossedNAND

CrossedNOR S-R(Set-Reset)CrossedNAND

&a &a&bRD SD

WHENRD=1,OriginalState:Q

Q

OriginalState:Q

Q &a10&b11&a11&b0&a10&b11&a11&b01RD RD Thepresent

ThepresentQ

Q

Q

QWHENRD=1, 0or &b&b1

RD &a1Q Q&a1

WHENRD=0, or&a&b1&a&b1

0

Q Q

&bWHENRD=0 &b&a0RD &a0ThetwooutputsarenotcomplementofeachInvalid禁WHENRD=0, 禁&b1&a&b1&a01SD RD SDThetwooutputsarenotcomplementofeachRSRS1100置0同時(shí)變后不確001101SR SR 輸輸入端低電平有SD( Direct 直接置“1”端(置D(Reset 直接置“0”端(復(fù)DQn+1)加觸發(fā)信號(hào)后新的狀態(tài)，稱(chēng)為次態(tài)或 ---原來(lái)的狀態(tài)，稱(chēng)為初態(tài)或Logic

CrossedNANDCrossedNOR

S-RP241:ExampleP241:Example7-Application:TheLatchasaContact-BounceApplication:TheLatchasaContact-BounceIC:7-1-2Gated7-1-2GatedS-R7-1-37-1-3GatedDLogic

FunctionGatedDFigureFigureThe74LS75quadgatedD7-27-2Edge-TriggeredFlip-（邊沿觸發(fā)的觸發(fā)器7-2-17-2-1Edge-triggeredS-Rflip-flop7-2-2Edge-triggeredDflip-flop7-2-3Edge-triggeredJ-Kflip-Edge-triggeredflip-floplogic 7-2-17-2-1Edge-TriggeredS-RFlip-P247:ExampleP247:Example7-AMethodofEdge-AMethodofEdge-AMethodAMethodofEdge-7-2-27-2-2Edge-TriggeredDFlip-7-2-3Edge-TriggeredJ-KFlip-Edge-TriggeredEdge-TriggeredJ-KFlip-P253:P253:Example7-7-2-47-2-4AsynchronousPresetandClearAsynchronousPreset(PRE)andClear(CLR)DirectSet Directresetactive-LOWP274（254）:Example7-AJ-Kflip-flopconnectedfortoggleoperationisalsocalledaT’ Figure 74AHC74dualpositiveedge-triggeredDflip-Figure 74HC112dualnegativeedge-triggeredJ-Kflip-Exercise:Theinputwaveformsgivenbelowareappliedtooneofthenegativeedge-triggeredflip-flops.Determinetheoutput7-3Flip-FlopOperating（觸發(fā)器的運(yùn)行特性Propagationdelaytimes（傳輸延遲時(shí)間Set-uptime（建立時(shí)間Holdtime（保持時(shí)間umclockfrequency（最大時(shí)鐘頻率Pulsewidths（脈沖寬度Powerdissipation（功率消耗Propagationdelaytimeisspecifiedfortherisingandfallingoutputs.Itismeasuredbetweenthe50%leveloftheclocktothe50%leveloftheoutputtransition.50%pointon

50%

to-HIGHof

50%pointHIGH-to-transitionofAnotherpropagationdelaytimespecificationisthetimerequiredforanasynchronousinputtocauseachangeintheoutput.Againitismeasuredfromthe50%levels.50%50%Q50%50%Q50%Set-uptimeandholdtimearetimesrequiredbeforeandaftertheclocktransitionthatdatamustbepresenttobereliablyclockedintotheflip-flop.Setuptimeistheminimumtimeforthedatatobepresentbeforetheclock.

DHoldtimeistheminimumtimeforthedatatoremainafterthe

Set-uptime,Holdtime,7-47-4Flip-Flop（觸發(fā)器的應(yīng)用7-4-17-4-1Paralleldatastorage7-4-2Frequencydivision7-4-37-4-4Other7-4-1Paralleldata（并行數(shù) Typically,fordatastorageapplications,agroupofflip-flopsareconnectedtoparalleldatalinesandclocked

OutputDDCCRRDDCCParallelinputDataisstoreduntiltheclock

RRCDCDRRCD CDRR7-4-27-4-2Frequencydivision（分頻Oneflip-flopwilldividefinby2twoflip-flopswilldividefinby4(andso

KJtheKJ7-4-37-4-3Counting（計(jì)數(shù)7-4-4Other電路的是74LS175四D觸發(fā)器。其包含了四個(gè)D觸發(fā)器，各輸入、輸

公用時(shí)

公用清

74LS175管腳

0賽前先

QQ1 Q2Q QQ3 QQ4 CPQ4& &&&

CP進(jìn)

QQ1 Q2Q QQ3 QQ4 CPQ4&

& 反相端都為&&1D觸發(fā)

1 1 Q2Q QQ3 QQ4

CPQ4&

& 被& 0

CP 狀態(tài)(1或0)。 D觸發(fā)器JK觸發(fā)7-5One-Shots（單穩(wěn)態(tài)觸發(fā)器one-shotisamonostableItisnormallyinitsstablestateandwillchangetounstablestateonlywhenOnceitistriggered,theone-shotremainsinitsunstablestateforapredeterminedlengthoftimeandthenautomaticallyreturnstoitsstablestate.穩(wěn)定狀 Nonretriggerableone-（不可再觸發(fā)的單穩(wěn)態(tài)觸發(fā)器RetriggerableRetriggerableone-（可再觸發(fā)的單穩(wěn)態(tài)觸發(fā)器OneOneshotanANDgateperforminganenable/inhibitfunctionforafrequencycounterAbasicone-shotAsinglenarrowtriggerpulseproducesasingleoutputpulsewhosetimedurationiscontrolledbytheRCtimeconstantBasicBasicone-shotlogicP285-288（267-IC:74121Non-retriggerableOne-shotIC:74122RetriggerableOne-shotExample12,13Application:Sequentialtimer(順序定時(shí)器7-6The555Timer（555定時(shí)器The555timerisaversatileandwidelyusedICItcanbeconfiguredintwodifferentmodesaseitheramonostabledevice(one-shot)orasanastablemultivibrator(oscillator).Anastablemultivibratorhasnostablestatesandthereforechangesbackandforthbetweentwounstablestateswithoutanyexternaltriggering.InternalB+:VCC/A-B+:VCC/RRSVCC/2VCC/比較的RS大于2VCC大于VCC10小于 01小于 大于VCC00RSQQ1RSQQ100101100011RSQ1010010100T1大于2VCC大于VCC01小于2VCCVCC11小于2VCCVCC00Monostable(one-shot)（構(gòu)成單穩(wěn)態(tài)觸發(fā)器閾值閾值 觸發(fā)端晶體管1大于2VCC大于VCC01小于2VCC VCC1100Prior小于2小于2VCC 大于VCC 保 保 555內(nèi)的晶體管TC1小于2VCC小于2VCC VCC 截閾值 觸發(fā)端晶體管1大于2VCC大于VCC0112VCC大于VCC000tuTR下降沿：uo=1，TC1

2VCCt0閾值 DAtendof閾值 D122VCC10

晶體管小于2VCC 小于2VCC VCC 截大于2VCC 大于VCC 0VCC觸發(fā)端tu充電至uC1>2VCC/3同時(shí)>VCC/3(TR=1)時(shí),T變?yōu)閷?dǎo)通

2VCCt0Atendofcharging閾值 觸發(fā)端晶體管11小于2VCC小 VCC11小于2VCC 大于VCC 保 00

大于2VCC 大于大于2VCC 大于VCC 導(dǎo)TR每出現(xiàn)一次下降沿uo便輸出一個(gè)正脈沖,其寬度TW由R1C1決定。

02VCCt000t 1.1R Astable（構(gòu)成無(wú)穩(wěn)態(tài)觸發(fā)器－多諧振蕩器

設(shè)電容C原先未充uO=1，T截止，R1C

uC1充電達(dá)到VCC/3,沒(méi)有到2VCC/3uo保持1充電時(shí)間常數(shù)放電