PowerLayoutNote華碩研發(fā)專用課件

PowerLayoutNote華碩研發(fā)專用PowerLayoutNote華碩研發(fā)專用OutlinePlacementOverview:POLexampleofMB,Server,NBandVGA.PowerStage:I/PCap,O/PCap,Sunbber,MOSFETplacementnoticeController:shortpinand外圍元件placement.Driver:locationand外圍元件placement.PartitionLayersOverview:PCBStack-UpexamplePhase/Vcc/GND:PartitionofPhase/Vcc/GNDTraceandPartitionTracewidthandGroupdistanceNoisesourceandsensitivecircuitTracelayoutguideOthers:Via,TracedropcalculationOutlinePlacementPlacement-OverviewPlacement-OverviewPlacement-OverviewPOL(PointofLoad)是PowerStage元件擺放的原則.PowerStage是指(又見下兩圖):較大的電源分怖環(huán)路中的元件.如:BulkCap,MOSFET,OutputInductor,PWMIC,…去耦合環(huán)路的元件.如:MLCC,Bead,..IOCPUSocketNBSBPCIPCIEDIMMUSBUSBVcoreswforCPU+1p2VCLforNB+1p8Vswand+0p9VforDIMM+1p05VforSB+1p2VcoreswforNB+3p3VSBforSBandLAN+5V_DualforUSBand1p8VswIntelMB:SATA24pinsandIDELANILOWERPWMIUPPERILOIOUTVPHASEVOUTVINPlacement-OverviewPOL(PointoPlacement-OverviewIOCPUSocketNB+SBPCIPCIEDIMMUSBUSBVcoreswandVDDNBswforCPU+1p2VHTforCPU,NB+SB+1p8Vand+0p9VforDIMM+2p5VforCPU+1p1VswforNB+SB+3p3VSBand+1p1VSBforNB+SBandLAN+5V_DualforUSBand1p8VswAMDMB:SATA24pinsandIDELANCPUSocketNBPowerInBladeServer:SBDIMMIO+VcoreswforCPU+1p05VswforNB+1p25VMforNB+1p25VforNB+1p05VMforNB+1p5VforSB+1p8V_DualswforDIMM+VTTDDRfroDIMMPlacement-OverviewIOCPUNB+SBPCPlacement-OverviewVGA(ATX):CPUBotSocketNBBotNB:SBTopDIMMBotChargerPowerINNBvoltagerailnotes:V->DualPowerVs->MainPowerVsus->VSBHDMITVDVIDDRDDRGPUHeat-SinkVcoreforCPU+1p8VforDIMM&NB+VTTDDRforDIMMCharger+12Vs+1p5VsforNB&SB+1p05VsforNB&SB&CPU+5VforUSB,Camera+5VSforODD,HDD,Codec+3VSforMiniCard,HDD,BT+3VsusforLAN,MDCandMiniCardTVDVIDDRGPUHeat-SinkVGA(LowProfile):+2p5VforI/O+NVVDD/VDDCswforGPU+1p1VforGPU+5VforI/OFBVDDQ/MVDDsw

forDDR(orGPU/AMD)Note:nVIDIA/AMDPlacement-OverviewVGA(ATX):CPPlacement-OverviewServer:PowerINDIMM-1DIMM-2CPU-1CPU-0PCIBMCPCI8NBSBLANLANIOPCIPCI8+Vcore0/2swforCPU-0/1CPU0/1_+1p1VswforCPU-0/1CPU0/1_+1p5VswforCPU-0/1-+0p75V_CPU0/1forCPU-0/1+3VswforAccessories+5VswforAccessories+3VAUX3VSBswforBMC,PCI+1p2VAUX_BMC+1p8VAUXIoH_+1p8VSBIoH_+0p9VSBIoH_+1p1VswIoH_+1p1VAUXLAN_+1VAUXICH_+1p5VICH_+1p05VPlacement-OverviewServer:PowerPlacement-PowerStage:ConnectorPlacement-PowerStage:ConnectPlacement-PowerStage:Connector現(xiàn)象:Connector的防呆端離立式電感太近!原因:插拔powersupply時(shí)，會(huì)卡到電感。改進(jìn)措施:將Connector調(diào)轉(zhuǎn)，使防呆端遠(yuǎn)離立式電感。Summary:Connector的防呆端不要朝向DIP電容和立式電感，防止卡機(jī)構(gòu)。Placement-PowerStage:ConnectPlacement-PowerStage:輸入電容（ELCAP和MLCC）Placement-PowerStage:輸入電容（ELPlacement-PowerStage:輸入電容（ELCAP和MLCC）現(xiàn)象:輸入電容離H/SMOSFET太近!原因:由於MOSFET的溫度較高，如果離輸入電容太近，其熱量可能傳到電容上，從而縮短電容的壽命。改進(jìn)措施:在條件允許（有空間且沒有走綫）的情況下，盡量將電容移開，離H/SMOSFET稍遠(yuǎn)，且均勻擺放。InputcapInputcapPlacement-PowerStage:輸入電容（ELPlacement-PowerStage:輸入電容（ELCAP和MLCC）現(xiàn)象:輸入電容離輸入電感太遠(yuǎn)!原因:在H/SMOSFET打開的瞬間，可能不能及時(shí)從輸入電容抽取電流，從而將L+12V拉低，導(dǎo)致輸入不穩(wěn)定或UVLO。改進(jìn)措施:將輸入電容放到靠近輸入電感処。InputchokeInputcapInputchokeInputcapPlacement-PowerStage:輸入電容（ELPlacement-PowerStage:輸入電容（ELCAP和MLCC）現(xiàn)象:輸入MLCC沒放到H/SMOSFET的Drainpin旁!原因:離H/SMOSFET太遠(yuǎn)不能有效濾除MOSFETDrain端因開關(guān)引起的spike，可能超過MOSFET的breakdownVoltage，燒掉H/SMOSFET且O/PRipple會(huì)被Inducespike影響。改進(jìn)措施:將輸入MLCC放到H/SMOSFET的Drainpin旁。HSI/PMLCCHSI/PMLCCPlacement-PowerStage:輸入電容（ELPlacement-PowerStage:輸入電容（ELCAP和MLCC）Summary:對(duì)於輸入電容的placement應(yīng)注意以下幾點(diǎn),輸入電容要放在輸入電感的后端且盡量均勻的擺放在每一相，起到及時(shí)補(bǔ)充電流的作用;為延長ELCAP和OS-CON的壽命，在條件允許的情況下，應(yīng)使其遠(yuǎn)離熱源H/SMOSFET;輸入的MLCC必須均勻擺放在每一相H/SMOSFET的DrainPin旁邊，來濾除L+12V的雜訊,降低spike以及O/PRippleVoltage。I/PCap需注意限高，尤其是DIMMlatch以及PCIE部分。Placement-PowerStage:輸入電容（ELPlacement-PowerStage:MOSFET,Snubber&ChokePlacement-PowerStage:MOSFET,Placement-PowerStage:MOSFET,Snubber&Choke現(xiàn)象:L/SMOSFET擺放不合理!原因:layout在鋪phase的shape時(shí)可能出現(xiàn)瓶頸，導(dǎo)致電流不均勻分?jǐn)傡秲深wMOSFET。改進(jìn)措施:將MOSFET換個(gè)方向擺放，使其在layout時(shí)不會(huì)出現(xiàn)瓶頸。Note:

Power建議20~40milshape流1A電流，但尚需考慮Thermal,VoltageDrop。H/SOutputChokeL/SH/SO/PChokeL/SPlacement-PowerStage:MOSFET,Placement-PowerStage:MOSFET,Snubber&Choke現(xiàn)象:L/SMOSFETGate電阻離L/SMOSFET太遠(yuǎn)!原因:gate電阻應(yīng)靠近MOSFETgate端擺放。改進(jìn)措施:將Gate電阻放到MOSFET的Gatepin旁邊。L/SRgDriverL/SRgPlacement-PowerStage:MOSFET,Placement-PowerStage:MOSFET,Snubber&Choke現(xiàn)象:Phase破層!原因:Phaseshape不完整不利于散熱，可能導(dǎo)致這塊shape的thermal過高。改進(jìn)措施:將Snubber電容向下移，保證phaseshape的完整性。SnubberSnubberPlacement-PowerStage:MOSFET,Placement-PowerStage:MOSFET,Snubber&Choke現(xiàn)象:snubber擺放位置不正確!原因:對(duì)phasenode的spike吸收效果不好，導(dǎo)致spike過高，超過MOSFET的breakdownVoltage，可能導(dǎo)致MOSFET燒掉。改進(jìn)措施:將Snubber擺放在L/SMOSFET的drainpin和sourcepin之間，使其更好的吸收phasenode的spike。Note:Snubber請(qǐng)擺在靠近O/PCap的L/SMOSFET，這可以大大改善Spike。O/PchokeH/SL/SSnubberH/SO/PchokeSnubberL/SPlacement-PowerStage:MOSFET,Placement-PowerStage:MOSFET,Snubber&Choke現(xiàn)象:DIPMOS靠得太近!原因:由於DIP的MOSFET會(huì)倒向前後兩個(gè)方向，Operator在插件時(shí)就可能會(huì)卡件。改進(jìn)措施:將DIPMOSFET之間的距離加大，至少相距一個(gè)0603電阻的距離。H/SL/SH/SL/SPlacement-PowerStage:MOSFET,Placement-PowerStage:MOSFET,Snubber&ChokeSummary:對(duì)於MOSFET和Snubber的placement應(yīng)注意以下幾點(diǎn)：H/SMOSFET的sourcepin、L/SMOSFET的drainpin以及Choke必須放在一起，保持phaseshape的完整性，並且保證shape不會(huì)出現(xiàn)瓶頸，更有利於散熱，降低thermal；兩個(gè)DIP的MOSFET的間距要保持一個(gè)0603電阻寬度(50mils)的距離，避免Operator在插件時(shí)出現(xiàn)卡件的問題，另外，DIP的MOSFET與Choke請(qǐng)保持0805電阻寬度(80mils)距離；MOSFET的Rg必須放在MOSFET的gatepin旁邊，Rgs必須放在H/SMOSFET的gatepin和phase之間，加速H/SMOSFET的放電速度，減少在HZ的MOSFET(G)上的Ring；Snubber電容及電阻必須靠近O/PCap的那一顆L/SMOSFET，其GND盡量和L/SMOSFET的sourcepin包在一起，更有利於吸收phasenode的spike，防止MOSFET燒掉。Choke注意限高，尤其是DIMMlatch以及PCIE部分。Placement-PowerStage:MOSFET,Placement-PowerStage:輸出電容Placement-PowerStage:輸出電容Placement-PowerStage:輸出電容現(xiàn)象:輸出電容輸出電感太遠(yuǎn)!原因:雜訊會(huì)不經(jīng)過電容濾波就直接作爲(wèi)輸出，使Vcore的performance變差。改進(jìn)措施:將輸出電容擺到輸出電感的左邊，使其更靠近與輸出電感。O/PCapO/PCapPlacement-PowerStage:輸出電容現(xiàn)象:Placement-PowerStage:輸出電容現(xiàn)象:輸出電容擺放位置不恰當(dāng)!原因:電容擋住了MOSFET的airflow，導(dǎo)致MOSFET的thermal過高。改進(jìn)措施:應(yīng)與ThermalEngineercheckcoolerairflow，將電容移開，使MOSFET能吹到風(fēng)。Note:尤其在ServerDIMMslot的左右兩側(cè)及中間各放一只電容,且solution為switching為了降低output的ripplenoiseand平衡輸出電容所承擔(dān)的ripplecurrent,所以O(shè)/Pchoke後端必須放置可以承受經(jīng)由O/Pchoke流出ripplecurrent的電容。L/SO/PCapL/SO/PCapPlacement-PowerStage:輸出電容現(xiàn)象:輸Placement-PowerStage:輸出電容Summary:對(duì)於輸出電容的placement應(yīng)注意以下幾點(diǎn)：輸出電容應(yīng)放在Choke和負(fù)載之間，起到濾波作用，transient會(huì)更好；在擺放輸出電容時(shí)，應(yīng)與ThermalEngineercheckcoolerairflow，盡量不要擋住MOSFET的airflow，從而降低MOSFET的thermal。輸出電容經(jīng)上述考量後，要儘量集中靠近輸出負(fù)載，以達(dá)到較佳的輸出特性與成本。注意限高.Placement-PowerStage:輸出電容SummPlacement-PowerStage:ControllerPlacement-PowerStage:ControlPlacement-PowerStage:Controller/Short-PinPlacement-PowerStage:ControlPlacement-PowerStage:Controller/Short-Pin現(xiàn)象:Currentsense的short-pin位置擺放不正確!原因:由於Currentsense是用outputchoke兩端的電壓來作爲(wèi)sense的依據(jù)，如果short-pin不放在電感的pin腳旁邊，在lay綫時(shí)可能就不會(huì)將這條sense綫拉到choke的pin腳上，就可能導(dǎo)致currentsense不準(zhǔn)確。改進(jìn)措施:將Currentsense的short-pin放在Choke的pin腳旁邊。Note:APW7120,RT8105,ISL6227…之OCPCurrentSense須靠近L/SMOSFETs。O/PchokeCurrentSenseshort-pinO/PchokeCurrentSenseshort-pinPlacement-PowerStage:ControlPlacement-PowerStage:Controller/Short-Pin現(xiàn)象:VcoreVoltagesense的short-pin位置擺放不正確!原因:由於Voltagesense是senseVcore的電壓，如果不放在socket下面，就可能導(dǎo)致Voltagesense不準(zhǔn)確。改進(jìn)措施:將short-pin放到socket的下面。VoltageSenseshort-pinPlacement-PowerStage:ControlPlacement-PowerStage:Controller/Short-PinSummary:對(duì)於controller的placement的擺放應(yīng)注意以下幾點(diǎn)：1、用於Currentsense的short-pin必須緊靠choke的兩個(gè)pin腳擺放使layout人員明確sense綫要拉到outputchoke的兩個(gè)pin腳上，使sense的電流準(zhǔn)確；2、用於Voltagesense的short-pin必須放在socket的下面來senseVcore的電壓來作爲(wèi)反饋。請(qǐng)Check各別CPUSense點(diǎn)來放置Short-Pins。Placement-PowerStage:ControlPlacement-PowerStage:Controller/外圍元件Placement-PowerStage:ControlPlacement-PowerStage:Controller/外圍元件現(xiàn)象:Bypass電容沒放到IC相對(duì)應(yīng)的pin腳旁邊!原因:MLCC濾波作用減小，雜訊進(jìn)入IC，可能使IC損壞或誤動(dòng)作。改進(jìn)措施:將Bypass電容放到對(duì)應(yīng)的pin腳旁邊。ICPowerpinBypassMLCCICPowerpinBypassMLCCPlacement-PowerStage:ControlPlacement-PowerStage:Controller/外圍元件現(xiàn)象:NTC電阻放在沒放在choke的旁邊!原因:由於controller是通過sensecurrentsensecomponent（outputchoke）的溫度來調(diào)整其溫度補(bǔ)償?shù)?，所以如果NTC電阻放的位置不對(duì)，可能導(dǎo)致溫度補(bǔ)償不正確。改進(jìn)措施:將NTC放在currentsensecomponent即choke的旁邊。Note:要依PWMIC的溫度補(bǔ)償元件而決定是ChokeorMOSFET。NTC電阻NTC電阻Placement-PowerStage:ControlPlacement-PowerStage:Controller/外圍元件現(xiàn)象:Ncompensationcomponent沒放在相應(yīng)的pin腳旁邊!原因:compensationcomponent沒放在相應(yīng)的pin腳旁邊會(huì)導(dǎo)致layout走綫困難。改進(jìn)措施:將compensationcomponent放在相對(duì)應(yīng)的pin腳旁邊。CompensationcomponentCompensationcomponentPlacement-PowerStage:ControlPlacement-PowerStage:Controller/外圍元件Summary:對(duì)於controller的Bypass電容和TMNTC電阻的placement應(yīng)注意以下幾點(diǎn)；Bypass的電容必須放在相應(yīng)的pin腳旁邊，起到濾波的作用，防止IC損壞和誤動(dòng)作；溫度補(bǔ)償用的NTC電阻必須放在choke的旁邊，通過senseoutputchoke(orMOSFET,要依PWMIC的溫度補(bǔ)償元件而決定是ChokeorMOSFET)的溫度來作爲(wèi)溫度補(bǔ)償?shù)囊罁?jù)；Compensation的component要盡量放在相對(duì)應(yīng)的pin腳附近，方便layout走綫。Placement-PowerStage:ControlPlacement-PowerStage:DriverPlacement-PowerStage:DriverPlacement-PowerStage:Driver現(xiàn)象:Boost電容的位置沒放對(duì)!原因:Boost電容沒有放在phasepin和boostpin之間，不滿足最短路徑，使layout困難。改進(jìn)措施:將boost電容移到如下位置。Boost電容路徑Placement-PowerStage:Driver現(xiàn)Placement-PowerStage:Driver現(xiàn)象:Driver離MOSFET太遠(yuǎn)!原因:gate信號(hào)拉得太遠(yuǎn)，trace拉得太長，driver到MOSFET的壓降會(huì)變大，會(huì)降低driver的驅(qū)動(dòng)能力，且trace過長可能會(huì)與其他信號(hào)產(chǎn)生互擾，layout困難。改進(jìn)措施:在條件允許的情況下，將driver放在靠近L/SMOSFET的旁邊，擺放如圖。Placement-PowerStage:Driver現(xiàn)Placement-PowerStage:DriverSummary:對(duì)於Driver的placement應(yīng)注意以下幾點(diǎn)：在條件允許的情況下，Driver的擺放位置應(yīng)盡量擺在此相MOSFET的附近，以減少trace閒的互繞，降低layout走綫難度；Boost電容和電阻要放在Driver的boostpin和phasepin之間，降低layout走綫難度。Placement-PowerStage:DriverSPartitionLayers-OverviewPartitionLayers-OverviewPartitionLayers-OverviewPower部份的PartitionLayer,其除了考慮敏感信號(hào),驅(qū)動(dòng)信號(hào),電力路徑外,另外也包含EMI抑制的基本觀念。以下是4layerPCBStack-UpEx:L1:Signal-1L2:PowerL3:GroundL4:Signal-2BestlayerforfluxcancellationMayexhibitpoorfluxcancellation以下是6layerPCBStack-UpEx:L1:Signal-1L2:GroundL3:Signal-2L4:PowerL5:Ground/SignalL6:Signal-3以下是8layerPCBStack-UpEx:L1:Signal-1L2:GroundL3:Signal-2L4:GroundL5:PowerL6:Signal-3L7:GroundL8:Signal-4Note:L3:Signal-2,也可走VcoreL4:Ground,可走Vcore/Signal L6:Signal,走GatePartitionLayers-OverviewPowerPartitionLayers-Phase/Vcc/GNDPartitionLayers-Phase/Vcc/GNPartitionLayers-Phase/Vcc/GND說明:Snubber及L/SMOSFETs之GND為雜訊源，不得與其共用；尤其是VGA訊號(hào)線，不得接近此GND!Snubber及L/SMOSFETs之GND說明:Phase與周圍的信號(hào)線要距離20mil(moat)!PartitionLayers-Phase/Vcc/GNPartitionLayers-Phase/Vcc/GND說明:除了Phase之Power層切割moat線為20mil以外（因?yàn)镻hase之線距為20mil），其餘切割線之線寬請(qǐng)依據(jù)RD2EE準(zhǔn)則。Phase在TOP之shape，必須與Power層切割線一致。(僅能以Core為分界,決定Phase下面是否可走線)Phaseshape保持完整性，不可一分為二。下圖的Vias擋住了Snubberpath!戒之!說明:利用適當(dāng)?shù)那懈罹€，可控制電流路徑，使I/PCap的ripplecurrent均勻分?jǐn)偂?1P8V_DUAL_VIN、+12V_VCORE_VIN驅(qū)動(dòng)訊號(hào)或+SW1_VIN必須離訊號(hào)線15mil(moat)以上距離。PartitionLayers-Phase/Vcc/GNPartitionLayers-Phase/Vcc/GND說明:IntelDTRecommendforCPUSocketPartitionshape:Layer1:VcoreLayer2:Vss(GND)Layer3:Vss(GND)Layer4:Vcore原則上，須使等效的ESL最小(Vcorelayers=Vsslayers)。說明:Controller及Driver必須參考到GND,Ex:Vcoredriverandcontroller,APW7102,RT8105,ISL6227…。PartitionLayers-Phase/Vcc/GNPartitionLayers-Phase/Vcc/GND說明:Driver之GNDpin為雜訊源，不得與其共用；尤其是VGA訊號(hào)線，不得接近此GND。L/S:IPD09N03LAGL/S:IPD13N03LAGVcc:12V->5V說明:Controllerw/Driver的GND(ex:ISL6312,…)，不建議分AGND與dDGND。除非廠商特定要求，否則一律與GNDLayer相接。referencevoltage是在pin1topin2,所以R798必須靠近U87並直接連到pin1與pin2.feedback的電阻成為R799,擺在U87,routing時(shí)請(qǐng)使用約8mils的traceR799此元件的Placement需靠近CE59否則trace需拉至CE59或負(fù)載端(可加Short-Pin),不要直接下GNDplane。PartitionLayers-Phase/Vcc/GNTraceandPartition-TracewidthandGroupdistanceTraceandPartition-TracewidTraceandPartition-TracewidthandGroupdistance說明:PowerRD會(huì)將線寬標(biāo)於netname字尾分別為_A,_B,_C…，所標(biāo)示的線寬定義對(duì)照如下：（LayoutDept可依據(jù)此規(guī)則，設(shè)定線寬）。5mil:netname10mil:netname_A15mil:netname_B20mil:netname_C25mil:netname_D30mil:netname_E一般而言，netname字尾未標(biāo)示即為5mil，但需鋪shape除外。Ex:Phase,Vin,+XXX…說明:Gate驅(qū)動(dòng)訊號(hào)，必須離訊號(hào)線15mil以上距離。Gate訊號(hào)線，路徑每拉長3cm，就必須增加5mil線寬TraceandPartition-TracewidTraceandPartition-TracewidthandGroupdistance說明:VoutSenseofVcore兩線並排、緊鄰，兩線相距5~10mil。避免換層。與自己的Group的線距15mil以上。與非自己的Group的線距20mil以上。說明:SingleSwitchVoutSense。與自己的Group的線距15mil以上。與非自己的Group的線距20mil以上。請(qǐng)由電容端或負(fù)載端拉回TraceandPartition-TracewidTraceandPartition-TracewidthandGroupdistance說明:Vcore/Switchingcurrentsensetrace圖例。Note:CurrentSense請(qǐng)繞行choke下方TraceandPartition-TracewidTraceandPartition-TracewidthandGroupdistance說明:NTCSense兩線並排、緊鄰，兩線相距5~10mil。避免換層！與自己的Group的線距15mil以上。與非自己的Group的線距20mil以上。下圖的Short-Pin位置不恰當(dāng),戒之!TraceandPartition-TracewidTraceandPartition-NoisesourceandsensitivecircuitTraceandPartition-NoisesouTraceandPartition-Noisesourceandsensitivecircuit說明:NoiseSource雜訊源:Pulsecurrent:I/PCap,LSandHSVoltageSpike:PhaseFlux:I/PchokeandL說明:易被干擾線路VoutSense:FB_JP1_A,FB_JP2_A,Vcore,+1P8V_DUAL_SENSE,SW1_SENSE…CurrentSense(VcoreDCRcurrentsense,OCPcurrentsense)。NTCthermalSense。Controllersignal。Layout原則：與自己的Group線距15mil以上與非自己的Group線距20mil以上（尤其是EE數(shù)位訊號(hào)）。LCLoadL/SQH/SQVinI/PchokeVGHVGLTraceandPartition-NoisesouTraceandPartition-TraceLayoutGuideTraceandPartition-TraceLayTraceandPartition-TraceLayoutGuide說明:LayoutGuidefor+1P1V_CoreTraceandPartition-TraceLayTraceandPartition-TraceLayoutGuide說明:LayoutGuidefor+1P8V_DualTraceandPartition-TraceLayTraceandPartition-TraceLayoutGuide說明:LayoutGuideforVcore/PWM-ICTraceandPartition-TraceLayTraceandPartition-TraceLayoutGuide說明:LayoutGuideforVcore/DriversTraceandPartition-TraceLayTraceandPartition-TraceLayoutGuide說明:LayoutGuideforVcore/ShapeTraceandPartition-TraceLayOthers-Via,TracedropcalculationandothernoticesOthers-Via,TracedropcalculOthers-Via,Tracedropcalculation說明:1chDriver之GNDpin至少要打兩個(gè)Via到GNDlayer。。說明:Viatype：VIA30D18A40。Viacurrentcapacity：2Apervia。ViatoViadistance：≥12mil。ViatoPindistance：≥12mil。DIP零件不需打ViaVcoresolution的I/P&O/P電感。Vcore的I/P&O/P電容。Switchingregulator的I/P&O/P電感。Switchingregulator的I/P&O/P電容。DIPMOSFETTO-251(IPAK)。Others-Via,TracedropcalculOthers-Via,Tracedropcalculation說明:ViaexamplesVia的擺放位置及數(shù)目，隨著實(shí)際Placement和layout及輸出負(fù)載不同，而有所改變，以下所列的為常用範(fàn)例，RD及Layout人員必須秉持專業(yè)及最佳化精神，去作適當(dāng)調(diào)整。ChipPolymerCapandMLCC:＋positive-NegativeGND說明:ViaexamplesHSMOSFET:加強(qiáng)導(dǎo)通,強(qiáng)化filterLSMOSFET:減少Viaimpedance,強(qiáng)化Snubber.Others-Via,TracedropcalculOthers-Via,Tracedropcalculation說明:+5V_USBdrop需要考慮以下:MOSFETRds_onTraceohmsbylength/widthPTCohmsNote:Rds,on+PTC後,Tracedrop一般約僅剩<130mV可用說明:TracedropcalculationOthers-Via,TracedropcalculAttachmentsAttachmentsPowerLayoutNote華碩研發(fā)專用PowerLayoutNote華碩研發(fā)專用OutlinePlacementOverview:POLexampleofMB,Server,NBandVGA.PowerStage:I/PCap,O/PCap,Sunbber,MOSFETplacementnoticeController:shortpinand外圍元件placement.Driver:locationand外圍元件placement.PartitionLayersOverview:PCBStack-UpexamplePhase/Vcc/GND:PartitionofPhase/Vcc/GNDTraceandPartitionTracewidthandGroupdistanceNoisesourceandsensitivecircuitTracelayoutguideOthers:Via,TracedropcalculationOutlinePlacementPlacement-OverviewPlacement-OverviewPlacement-OverviewPOL(PointofLoad)是PowerStage元件擺放的原則.PowerStage是指(又見下兩圖):較大的電源分怖環(huán)路中的元件.如:BulkCap,MOSFET,OutputInductor,PWMIC,…去耦合環(huán)路的元件.如:MLCC,Bead,..IOCPUSocketNBSBPCIPCIEDIMMUSBUSBVcoreswforCPU+1p2VCLforNB+1p8Vswand+0p9VforDIMM+1p05VforSB+1p2VcoreswforNB+3p3VSBforSBandLAN+5V_DualforUSBand1p8VswIntelMB:SATA24pinsandIDELANILOWERPWMIUPPERILOIOUTVPHASEVOUTVINPlacement-OverviewPOL(PointoPlacement-OverviewIOCPUSocketNB+SBPCIPCIEDIMMUSBUSBVcoreswandVDDNBswforCPU+1p2VHTforCPU,NB+SB+1p8Vand+0p9VforDIMM+2p5VforCPU+1p1VswforNB+SB+3p3VSBand+1p1VSBforNB+SBandLAN+5V_DualforUSBand1p8VswAMDMB:SATA24pinsandIDELANCPUSocketNBPowerInBladeServer:SBDIMMIO+VcoreswforCPU+1p05VswforNB+1p25VMforNB+1p25VforNB+1p05VMforNB+1p5VforSB+1p8V_DualswforDIMM+VTTDDRfroDIMMPlacement-OverviewIOCPUNB+SBPCPlacement-OverviewVGA(ATX):CPUBotSocketNBBotNB:SBTopDIMMBotChargerPowerINNBvoltagerailnotes:V->DualPowerVs->MainPowerVsus->VSBHDMITVDVIDDRDDRGPUHeat-SinkVcoreforCPU+1p8VforDIMM&NB+VTTDDRforDIMMCharger+12Vs+1p5VsforNB&SB+1p05VsforNB&SB&CPU+5VforUSB,Camera+5VSforODD,HDD,Codec+3VSforMiniCard,HDD,BT+3VsusforLAN,MDCandMiniCardTVDVIDDRGPUHeat-SinkVGA(LowProfile):+2p5VforI/O+NVVDD/VDDCswforGPU+1p1VforGPU+5VforI/OFBVDDQ/MVDDsw

forDDR(orGPU/AMD)Note:nVIDIA/AMDPlacement-OverviewVGA(ATX):CPPlacement-OverviewServer:PowerINDIMM-1DIMM-2CPU-1CPU-0PCIBMCPCI8NBSBLANLANIOPCIPCI8+Vcore0/2swforCPU-0/1CPU0/1_+1p1VswforCPU-0/1CPU0/1_+1p5VswforCPU-0/1-+0p75V_CPU0/1forCPU-0/1+3VswforAccessories+5VswforAccessories+3VAUX3VSBswforBMC,PCI+1p2VAUX_BMC+1p8VAUXIoH_+1p8VSBIoH_+0p9VSBIoH_+1p1VswIoH_+1p1VAUXLAN_+1VAUXICH_+1p5VICH_+1p05VPlacement-OverviewServer:PowerPlacement-PowerStage:ConnectorPlacement-PowerStage:ConnectPlacement-PowerStage:Connector現(xiàn)象:Connector的防呆端離立式電感太近!原因:插拔powersupply時(shí)，會(huì)卡到電感。改進(jìn)措施:將Connector調(diào)轉(zhuǎn)，使防呆端遠(yuǎn)離立式電感。Summary:Connector的防呆端不要朝向DIP電容和立式電感，防止卡機(jī)構(gòu)。Placement-PowerStage:ConnectPlacement-PowerStage:輸入電容（ELCAP和MLCC）Placement-PowerStage:輸入電容（ELPlacement-PowerStage:輸入電容（ELCAP和MLCC）現(xiàn)象:輸入電容離H/SMOSFET太近!原因:由於MOSFET的溫度較高，如果離輸入電容太近，其熱量可能傳到電容上，從而縮短電容的壽命。改進(jìn)措施:在條件允許（有空間且沒有走綫）的情況下，盡量將電容移開，離H/SMOSFET稍遠(yuǎn)，且均勻擺放。InputcapInputcapPlacement-PowerStage:輸入電容（ELPlacement-PowerStage:輸入電容（ELCAP和MLCC）現(xiàn)象:輸入電容離輸入電感太遠(yuǎn)!原因:在H/SMOSFET打開的瞬間，可能不能及時(shí)從輸入電容抽取電流，從而將L+12V拉低，導(dǎo)致輸入不穩(wěn)定或UVLO。改進(jìn)措施:將輸入電容放到靠近輸入電感処。InputchokeInputcapInputchokeInputcapPlacement-PowerStage:輸入電容（ELPlacement-PowerStage:輸入電容（ELCAP和MLCC）現(xiàn)象:輸入MLCC沒放到H/SMOSFET的Drainpin旁!原因:離H/SMOSFET太遠(yuǎn)不能有效濾除MOSFETDrain端因開關(guān)引起的spike，可能超過MOSFET的breakdownVoltage，燒掉H/SMOSFET且O/PRipple會(huì)被Inducespike影響。改進(jìn)措施:將輸入MLCC放到H/SMOSFET的Drainpin旁。HSI/PMLCCHSI/PMLCCPlacement-PowerStage:輸入電容（ELPlacement-PowerStage:輸入電容（ELCAP和MLCC）Summary:對(duì)於輸入電容的placement應(yīng)注意以下幾點(diǎn),輸入電容要放在輸入電感的后端且盡量均勻的擺放在每一相，起到及時(shí)補(bǔ)充電流的作用;為延長ELCAP和OS-CON的壽命，在條件允許的情況下，應(yīng)使其遠(yuǎn)離熱源H/SMOSFET;輸入的MLCC必須均勻擺放在每一相H/SMOSFET的DrainPin旁邊，來濾除L+12V的雜訊,降低spike以及O/PRippleVoltage。I/PCap需注意限高，尤其是DIMMlatch以及PCIE部分。Placement-PowerStage:輸入電容（ELPlacement-PowerStage:MOSFET,Snubber&ChokePlacement-PowerStage:MOSFET,Placement-PowerStage:MOSFET,Snubber&Choke現(xiàn)象:L/SMOSFET擺放不合理!原因:layout在鋪phase的shape時(shí)可能出現(xiàn)瓶頸，導(dǎo)致電流不均勻分?jǐn)傡秲深wMOSFET。改進(jìn)措施:將MOSFET換個(gè)方向擺放，使其在layout時(shí)不會(huì)出現(xiàn)瓶頸。Note:

Power建議20~40milshape流1A電流，但尚需考慮Thermal,VoltageDrop。H/SOutputChokeL/SH/SO/PChokeL/SPlacement-PowerStage:MOSFET,Placement-PowerStage:MOSFET,Snubber&Choke現(xiàn)象:L/SMOSFETGate電阻離L/SMOSFET太遠(yuǎn)!原因:gate電阻應(yīng)靠近MOSFETgate端擺放。改進(jìn)措施:將Gate電阻放到MOSFET的Gatepin旁邊。L/SRgDriverL/SRgPlacement-PowerStage:MOSFET,Placement-PowerStage:MOSFET,Snubber&Choke現(xiàn)象:Phase破層!原因:Phaseshape不完整不利于散熱，可能導(dǎo)致這塊shape的thermal過高。改進(jìn)措施:將Snubber電容向下移，保證phaseshape的完整性。SnubberSnubberPlacement-PowerStage:MOSFET,Placement-PowerStage:MOSFET,Snubber&Choke現(xiàn)象:snubber擺放位置不正確!原因:對(duì)phasenode的spike吸收效果不好，導(dǎo)致spike過高，超過MOSFET的breakdownVoltage，可能導(dǎo)致MOSFET燒掉。改進(jìn)措施:將Snubber擺放在L/SMOSFET的drainpin和sourcepin之間，使其更好的吸收phasenode的spike。Note:Snubber請(qǐng)擺在靠近O/PCap的L/SMOSFET，這可以大大改善Spike。O/PchokeH/SL/SSnubberH/SO/PchokeSnubberL/SPlacement-PowerStage:MOSFET,Placement-PowerStage:MOSFET,Snubber&Choke現(xiàn)象:DIPMOS靠得太近!原因:由於DIP的MOSFET會(huì)倒向前後兩個(gè)方向，Operator在插件時(shí)就可能會(huì)卡件。改進(jìn)措施:將DIPMOSFET之間的距離加大，至少相距一個(gè)0603電阻的距離。H/SL/SH/SL/SPlacement-PowerStage:MOSFET,Placement-PowerStage:MOSFET,Snubber&ChokeSummary:對(duì)於MOSFET和Snubber的placement應(yīng)注意以下幾點(diǎn)：H/SMOSFET的sourcepin、L/SMOSFET的drainpin以及Choke必須放在一起，保持phaseshape的完整性，並且保證shape不會(huì)出現(xiàn)瓶頸，更有利於散熱，降低thermal；兩個(gè)DIP的MOSFET的間距要保持一個(gè)0603電阻寬度(50mils)的距離，避免Operator在插件時(shí)出現(xiàn)卡件的問題，另外，DIP的MOSFET與Choke請(qǐng)保持0805電阻寬度(80mils)距離；MOSFET的Rg必須放在MOSFET的gatepin旁邊，Rgs必須放在H/SMOSFET的gatepin和phase之間，加速H/SMOSFET的放電速度，減少在HZ的MOSFET(G)上的Ring；Snubber電容及電阻必須靠近O/PCap的那一顆L/SMOSFET，其GND盡量和L/SMOSFET的sourcepin包在一起，更有利於吸收phasenode的spike，防止MOSFET燒掉。Choke注意限高，尤其是DIMMlatch以及PCIE部分。Placement-PowerStage:MOSFET,Placement-PowerStage:輸出電容Placement-PowerStage:輸出電容Placement-PowerStage:輸出電容現(xiàn)象:輸出電容輸出電感太遠(yuǎn)!原因:雜訊會(huì)不經(jīng)過電容濾波就直接作爲(wèi)輸出，使Vcore的performance變差。改進(jìn)措施:將輸出電容擺到輸出電感的左邊，使其更靠近與輸出電感。O/PCapO/PCapPlacement-PowerStage:輸出電容現(xiàn)象:Placement-PowerStage:輸出電容現(xiàn)象:輸出電容擺放位置不恰當(dāng)!原因:電容擋住了MOSFET的airflow，導(dǎo)致MOSFET的thermal過高。改進(jìn)措施:應(yīng)與ThermalEngineercheckcoolerairflow，將電容移開，使MOSFET能吹到風(fēng)。Note:尤其在ServerDIMMslot的左右兩側(cè)及中間各放一只電容,且solution為switching為了降低output的ripplenoiseand平衡輸出電容所承擔(dān)的ripplecurrent,所以O(shè)/Pchoke後端必須放置可以承受經(jīng)由O/Pchoke流出ripplecurrent的電容。L/SO/PCapL/SO/PCapPlacement-PowerStage:輸出電容現(xiàn)象:輸Placement-PowerStage:輸出電容Summary:對(duì)於輸出電容的placement應(yīng)注意以下幾點(diǎn)：輸出電容應(yīng)放在Choke和負(fù)載之間，起到濾波作用，transient會(huì)更好；在擺放輸出電容時(shí)，應(yīng)與ThermalEngineercheckcoolerairflow，盡量不要擋住MOSFET的airflow，從而降低MOSFET的thermal。輸出電容經(jīng)上述考量後，要儘量集中靠近輸出負(fù)載，以達(dá)到較佳的輸出特性與成本。注意限高.Placement-PowerStage:輸出電容SummPlacement-PowerStage:ControllerPlacement-PowerStage:ControlPlacement-PowerStage:Controller/Short-PinPlacement-PowerStage:ControlPlacement-PowerStage:Controller/Short-Pin現(xiàn)象:Currentsense的short-pin位置擺放不正確!原因:由於Currentsense是用outputchoke兩端的電壓來作爲(wèi)sense的依據(jù)，如果short-pin不放在電感的pin腳旁邊，在lay綫時(shí)可能就不會(huì)將這條sense綫拉到choke的pin腳上，就可能導(dǎo)致currentsense不準(zhǔn)確。改進(jìn)措施:將Currentsense的short-pin放在Choke的pin腳旁邊。Note:APW7120,RT8105,ISL6227…之OCPCurrentSense須靠近L/SMOSFETs。O/PchokeCurrentSenseshort-pinO/PchokeCurrentSenseshort-pinPlacement-PowerStage:ControlPlacement-PowerStage:Controller/Short-Pin現(xiàn)象:VcoreVoltagesense的short-pin位置擺放不正確!原因:由於Voltagesense是senseVcore的電壓，如果不放在socket下面，就可能導(dǎo)致Voltagesense不準(zhǔn)確。改進(jìn)措施:將short-pin放到socket的下面。VoltageSenseshort-pinPlacement-PowerStage:ControlPlacement-PowerStage:Controller/Short-PinSummary:對(duì)於controller的placement的擺放應(yīng)注意以下幾點(diǎn)：1、用於Currentsense的short-pin必須緊靠choke的兩個(gè)pin腳擺放使layout人員明確sense綫要拉到outputchoke的兩個(gè)pin腳上，使sense的電流準(zhǔn)確；2、用於Voltagesense的short-pin必須放在socket的下面來senseVcore的電壓來作爲(wèi)反饋。請(qǐng)Check各別CPUSense點(diǎn)來放置Short-Pins。Placement-PowerStage:ControlPlacement-PowerStage:Controller/外圍元件Placement-PowerStage:ControlPlacement-PowerStage:Controller/外圍元件現(xiàn)象:Bypass電容沒放到IC相對(duì)應(yīng)的pin腳旁邊!原因:MLCC濾波作用減小，雜訊進(jìn)入IC，可能使IC損壞或誤動(dòng)作。改進(jìn)措施:將Bypass電容放到對(duì)應(yīng)的pin腳旁邊。ICPowerpinBypassMLCCICPowerpinBypassMLCCPlacement-PowerStage:ControlPlacement-PowerStage:Controller/外圍元件現(xiàn)象:NTC電阻放在沒放在choke的旁邊!原因:由於controller是通過sensecurrentsensecomponent（outputchoke）的溫度來調(diào)整其溫度補(bǔ)償?shù)模匀绻鸑TC電阻放的位置不對(duì)，可能導(dǎo)致溫度補(bǔ)償不正確。改進(jìn)措施:將NTC放在currentsensecomponent即choke的旁邊。Note:要依PWMIC的溫度補(bǔ)償元件而決定是ChokeorMOSFET。NTC電阻NTC電阻Placement-PowerStage:ControlPlacement-PowerStage:Controller/外圍元件現(xiàn)象:Ncompensationcomponent沒放在相應(yīng)的pin腳旁邊!原因:compensationcomponent沒放在相應(yīng)的pin腳旁邊會(huì)導(dǎo)致layout走綫困難。改進(jìn)措施:將compensationcomponent放在相對(duì)應(yīng)的pin腳旁邊。CompensationcomponentCompensationcomponentPlacement-PowerStage:ControlPlacement-PowerStage:Controller/外圍元件Summary:對(duì)於controller的Bypass電容和TMNTC電阻的placement應(yīng)注意以下幾點(diǎn)；Bypass的電容必須放在相應(yīng)的pin腳旁邊，起到濾波的作用，防止IC損壞和誤動(dòng)作；溫度補(bǔ)償用的NTC電阻必須放在choke的旁邊，通過senseoutputchoke(orMOSFET,要依PWMIC的溫度補(bǔ)償元件而決定是ChokeorMOSFET)的溫度來作爲(wèi)溫度補(bǔ)償?shù)囊罁?jù)；Compensation的component要盡量放在相對(duì)應(yīng)的pin腳附近，方便layout走綫。Placement-PowerStage:ControlPlacement-PowerStage:DriverPlacement-PowerStage:DriverPlacement-PowerStage:Driver現(xiàn)象:Boost電容的位置沒放對(duì)!原因:Boost電容沒有放在phasepin和boostpin之間，不滿足最短路徑，使layout困難。改進(jìn)措施:將boost電容移到如下位置。Boost電容路徑Placement-PowerStage:Driver現(xiàn)Placement-PowerStage:Driver現(xiàn)象:Driver離MOSFET太遠(yuǎn)!原因:gate信號(hào)拉得太遠(yuǎn)，trace拉得太長，driver到MOSFET的壓降會(huì)變大，會(huì)降低driver的驅(qū)動(dòng)能力，且trace過長可能會(huì)與其他信號(hào)產(chǎn)生互擾，layout困難。改進(jìn)措施:在條件允許的情況下，將driver放在靠近L/SMOSFET的旁邊，擺放如圖。Placement-PowerStage:Driver現(xiàn)Placement-PowerStage:DriverSummary:對(duì)於Driver的placement應(yīng)注意以下幾點(diǎn)：在條件允許的情況下，Driver的擺放位置應(yīng)盡量擺在此相MOSFET的附近，以減少trace閒的互繞，降低layout走綫難度；Boost電容和電阻要放在Driver的boostpin和phasepin之間，降低layout走綫難度。Placement-PowerStage:DriverSPartitionLayers-OverviewPartitionLayers-OverviewPartitionLayers-OverviewPower部份的PartitionLayer,其除了考慮敏感信號(hào),驅(qū)動(dòng)信號(hào),電力路徑外,另外也包含EMI抑制的基本觀念。以下是4layerPCBStack-UpEx:L1:Signal-1L2:PowerL3:GroundL4:Signal-2BestlayerforfluxcancellationMayexhibitpoorfluxcancellation以下是6layerPCBStack-UpEx:L1:Signal-1L2:GroundL3:Signal-2L4:PowerL5:Ground/SignalL6:Signal-3以下是8layerPCBStack-UpEx:L1:Signal-1L2:GroundL3:Signal-2L4:GroundL5:PowerL6:Signal-3L7:GroundL8:Signal-4Note:L3:Signal-2,也可走VcoreL4:Ground,可走Vcore/Signal L6:Signal,走GatePartitionLayers-OverviewPowerPartitionLayers-Phase/Vcc/GNDPartitionLayers-Phase/Vcc/GNPartitionLayers-Phase/Vcc/GND說明:Snubber及L/SMOSFETs之GND為雜訊源，不得與其共用；尤其是VGA訊號(hào)線，不得接近此GND!Snubber及L/SMOSFETs之GND說明:Phase與周圍的信號(hào)線要距離20mil(moat)!PartitionLayers-Phase/Vcc/GNPartitionLayers-Phase/Vcc/GND說明:除了Phase之Power層切割moat線為20mil以外（因?yàn)镻hase之線距為20mil），其餘切割線之線寬請(qǐng)依據(jù)RD2EE準(zhǔn)則。Phase在TOP之shape，必須與Power層切割線一致。(僅能以Core為分界,決定Phase下面是否可走線)Phaseshape保持完整性，不可一分為二。下圖的Vias擋住了Snubberpath!戒之!說明:利用適當(dāng)?shù)那懈罹€，可控制電流路徑，使I/PCap的ripplecurrent均勻分?jǐn)偂?1P8V_DUAL_VIN、+12V_VCORE_VIN驅(qū)動(dòng)訊號(hào)或+SW1_VIN必須離訊號(hào)線15mil(moat)以上距離。PartitionLayers-Phase/Vcc/GNPartitionLayers-Phase/Vcc/GND說明:IntelDTRecommendforCPUSocketPartitionshape:Layer1:VcoreLayer2:Vss(GND)Layer3:Vss(GND)Layer4:Vcore原則上，須使等效的ESL最小(Vcorelayers=Vsslayers)。說明:Controller及Driver必須參考到GND,Ex:Vcoredriverandcontroller,APW7102,RT8105,ISL6227…。PartitionLayers-Phase/Vcc/GNPartitionLayers-Phase/Vcc/GND說明:Driver之GNDpin為雜訊源，不得與其共用；尤其是VGA訊號(hào)線，不得接近此GND。L/S:IPD09N03LAGL/S:IPD13N03LAGVcc:12V->5V說明:Controllerw/Driver的GND(ex:ISL6312,…)，不建議分AGND與dDGND。除非廠商特定要求，否則一律與GNDLayer相接。referencevoltage是在pin1topin2,所以R798必須靠近U87並直接連到pin1與pin2.feedback的電阻成為R799,擺在U87,routing時(shí)請(qǐng)使用約8mils的traceR799此元件的Placement需靠近CE59否則trace需拉至CE59或負(fù)載端(可加Short-Pin),不要直接下GNDplane。PartitionLayers-Phase/Vcc/GNTraceandPartition-TracewidthandGroupdistanceTraceandPartition-TracewidTraceandPartition-TracewidthandGroupdistance說明:PowerRD會(huì)將線寬標(biāo)於netname字尾分別為_A,_B,_C…，所標(biāo)示的線寬定義對(duì)照如下：（LayoutDept可依據(jù)此規(guī)則，設(shè)定線寬）。5mil:netname10mil:netname_A15mil:netname_B20mil:netname_